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Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
213516ef | 3 | Copyright (C) 2003-2023 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
ee967b5f | 22 | #include "solib-svr4.h" |
ca3bf3bd | 23 | #include "symtab.h" |
ca3bf3bd DJ |
24 | #include "gdbtypes.h" |
25 | #include "gdbcore.h" | |
26 | #include "value.h" | |
40045d91 | 27 | #include "osabi.h" |
ca3bf3bd DJ |
28 | #include "regcache.h" |
29 | #include "reggroups.h" | |
30 | #include "regset.h" | |
31 | ||
82ca8957 | 32 | #include "dwarf2/frame.h" |
ca3bf3bd DJ |
33 | #include "frame-base.h" |
34 | #include "frame-unwind.h" | |
35 | ||
36 | #include "arch-utils.h" | |
37 | #include "gdbarch.h" | |
ca3bf3bd DJ |
38 | |
39 | #include "command.h" | |
40 | #include "gdbcmd.h" | |
ca3bf3bd | 41 | |
bdb4c075 | 42 | #include "xtensa-isa.h" |
ca3bf3bd | 43 | #include "xtensa-tdep.h" |
94a0e877 | 44 | #include "xtensa-config.h" |
325fac50 | 45 | #include <algorithm> |
ca3bf3bd DJ |
46 | |
47 | ||
ccce17b0 | 48 | static unsigned int xtensa_debug_level = 0; |
ca3bf3bd DJ |
49 | |
50 | #define DEBUGWARN(args...) \ | |
51 | if (xtensa_debug_level > 0) \ | |
6cb06a8c | 52 | gdb_printf (gdb_stdlog, "(warn ) " args) |
ca3bf3bd DJ |
53 | |
54 | #define DEBUGINFO(args...) \ | |
55 | if (xtensa_debug_level > 1) \ | |
6cb06a8c | 56 | gdb_printf (gdb_stdlog, "(info ) " args) |
ca3bf3bd DJ |
57 | |
58 | #define DEBUGTRACE(args...) \ | |
59 | if (xtensa_debug_level > 2) \ | |
6cb06a8c | 60 | gdb_printf (gdb_stdlog, "(trace) " args) |
ca3bf3bd DJ |
61 | |
62 | #define DEBUGVERB(args...) \ | |
63 | if (xtensa_debug_level > 3) \ | |
6cb06a8c | 64 | gdb_printf (gdb_stdlog, "(verb ) " args) |
ca3bf3bd DJ |
65 | |
66 | ||
67 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
68 | #define SP_ALIGNMENT 16 |
69 | ||
70 | ||
bdb4c075 MG |
71 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
72 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
73 | #define ARGS_NUM_REGS 6 |
74 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 75 | |
ca3bf3bd | 76 | |
bdb4c075 MG |
77 | /* Extract the call size from the return address or PS register. */ |
78 | #define PS_CALLINC_SHIFT 16 | |
79 | #define PS_CALLINC_MASK 0x00030000 | |
80 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
81 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 82 | |
98689b25 MG |
83 | /* On TX, hardware can be configured without Exception Option. |
84 | There is no PS register in this case. Inside XT-GDB, let us treat | |
85 | it as a virtual read-only register always holding the same value. */ | |
86 | #define TX_PS 0x20 | |
87 | ||
bdb4c075 | 88 | /* ABI-independent macros. */ |
345bd07c SM |
89 | #define ARG_NOF(tdep) \ |
90 | (tdep->call_abi \ | |
91d8eb23 | 91 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) |
345bd07c SM |
92 | #define ARG_1ST(tdep) \ |
93 | (tdep->call_abi == CallAbiCall0Only \ | |
94 | ? (tdep->a0_base + C0_ARGS) \ | |
95 | : (tdep->a0_base + 6)) | |
ca3bf3bd | 96 | |
ca3bf3bd DJ |
97 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
98 | indicates that the instruction is an ENTRY instruction. */ | |
99 | ||
91d8eb23 MD |
100 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
101 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 102 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 103 | |
bdb4c075 | 104 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
105 | |
106 | /* windowing_enabled() returns true, if windowing is enabled. | |
107 | WOE must be set to 1; EXCM to 0. | |
108 | Note: We assume that EXCM is always 0 for XEA1. */ | |
109 | ||
bdb4c075 MG |
110 | #define PS_WOE (1<<18) |
111 | #define PS_EXC (1<<4) | |
112 | ||
0dd5cbc5 AH |
113 | /* Big enough to hold the size of the largest register in bytes. */ |
114 | #define XTENSA_MAX_REGISTER_SIZE 64 | |
115 | ||
b801de47 | 116 | static int |
98689b25 MG |
117 | windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) |
118 | { | |
08106042 | 119 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 120 | |
98689b25 | 121 | /* If we know CALL0 ABI is set explicitly, say it is Call0. */ |
345bd07c | 122 | if (tdep->call_abi == CallAbiCall0Only) |
98689b25 MG |
123 | return 0; |
124 | ||
125 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); | |
126 | } | |
127 | ||
581e13c1 MS |
128 | /* Convert a live A-register number to the corresponding AR-register |
129 | number. */ | |
91d8eb23 | 130 | static int |
ee967b5f | 131 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 | 132 | { |
08106042 | 133 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ee967b5f | 134 | int arreg; |
91d8eb23 | 135 | |
ee967b5f MG |
136 | arreg = a_regnum - tdep->a0_base; |
137 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
138 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 139 | |
ee967b5f MG |
140 | return arreg + tdep->ar_base; |
141 | } | |
142 | ||
143 | /* Convert a live AR-register number to the corresponding A-register order | |
144 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
145 | static int | |
146 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
147 | { | |
08106042 | 148 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ee967b5f MG |
149 | int areg; |
150 | ||
151 | areg = ar_regnum - tdep->ar_base; | |
152 | if (areg < 0 || areg >= tdep->num_aregs) | |
153 | return -1; | |
154 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
155 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
156 | } |
157 | ||
68d6df83 | 158 | /* Read Xtensa register directly from the hardware. */ |
b801de47 | 159 | static unsigned long |
08b9c608 MG |
160 | xtensa_read_register (int regnum) |
161 | { | |
162 | ULONGEST value; | |
163 | ||
9c742269 SM |
164 | regcache_raw_read_unsigned (get_thread_regcache (inferior_thread ()), regnum, |
165 | &value); | |
08b9c608 MG |
166 | return (unsigned long) value; |
167 | } | |
168 | ||
68d6df83 | 169 | /* Write Xtensa register directly to the hardware. */ |
b801de47 | 170 | static void |
08b9c608 MG |
171 | xtensa_write_register (int regnum, ULONGEST value) |
172 | { | |
9c742269 SM |
173 | regcache_raw_write_unsigned (get_thread_regcache (inferior_thread ()), regnum, |
174 | value); | |
08b9c608 MG |
175 | } |
176 | ||
ca3bf3bd DJ |
177 | /* Return the window size of the previous call to the function from which we |
178 | have just returned. | |
179 | ||
180 | This function is used to extract the return value after a called function | |
bdb4c075 | 181 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
182 | value (from the perspective of the caller) depends on what call |
183 | instruction was used. For now, we are assuming that the call instruction | |
184 | precedes the current address, so we simply analyze the call instruction. | |
185 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
186 | method to call the inferior function. */ | |
187 | ||
188 | static int | |
91d8eb23 | 189 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 190 | { |
e17a4113 | 191 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 | 192 | int winsize = 4; |
ca3bf3bd | 193 | int insn; |
ff7a4c00 | 194 | gdb_byte buf[4]; |
ca3bf3bd DJ |
195 | |
196 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
197 | ||
198 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
199 | read_memory (pc-3, buf, 3); | |
e17a4113 | 200 | insn = extract_unsigned_integer (buf, 3, byte_order); |
ca3bf3bd DJ |
201 | |
202 | /* Decode call instruction: | |
203 | Little Endian | |
204 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
205 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
206 | Big Endian | |
207 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
208 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
209 | ||
e17a4113 | 210 | if (byte_order == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
211 | { |
212 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 213 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
214 | } |
215 | else | |
216 | { | |
217 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 218 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
219 | } |
220 | return winsize; | |
221 | } | |
222 | ||
223 | ||
224 | /* REGISTER INFORMATION */ | |
225 | ||
08b9c608 MG |
226 | /* Find register by name. */ |
227 | static int | |
a121b7c1 | 228 | xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name) |
08b9c608 MG |
229 | { |
230 | int i; | |
08106042 | 231 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
08b9c608 | 232 | |
f6efe3f8 | 233 | for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) |
345bd07c | 234 | if (strcasecmp (tdep->regmap[i].name, name) == 0) |
08b9c608 MG |
235 | return i; |
236 | ||
237 | return -1; | |
238 | } | |
239 | ||
ca3bf3bd | 240 | /* Returns the name of a register. */ |
ca3bf3bd | 241 | static const char * |
d93859e2 | 242 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd | 243 | { |
08106042 | 244 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 245 | |
ca3bf3bd | 246 | /* Return the name stored in the register map. */ |
9b9e61c7 | 247 | return tdep->regmap[regnum].name; |
ca3bf3bd DJ |
248 | } |
249 | ||
ca3bf3bd DJ |
250 | /* Return the type of a register. Create a new type, if necessary. */ |
251 | ||
ca3bf3bd DJ |
252 | static struct type * |
253 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
254 | { | |
08106042 | 255 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
df4df182 | 256 | |
ca3bf3bd | 257 | /* Return signed integer for ARx and Ax registers. */ |
df4df182 UW |
258 | if ((regnum >= tdep->ar_base |
259 | && regnum < tdep->ar_base + tdep->num_aregs) | |
260 | || (regnum >= tdep->a0_base | |
261 | && regnum < tdep->a0_base + 16)) | |
0dfff4cb | 262 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 263 | |
6b50c0b0 | 264 | if (regnum == gdbarch_pc_regnum (gdbarch) |
df4df182 | 265 | || regnum == tdep->a0_base + 1) |
fde6c819 | 266 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
267 | |
268 | /* Return the stored type for all other registers. */ | |
f6efe3f8 | 269 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 270 | { |
df4df182 | 271 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd | 272 | |
bdb4c075 | 273 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
274 | |
275 | if (reg->ctype == 0) | |
276 | { | |
277 | struct ctype_cache *tp; | |
278 | int size = reg->byte_size; | |
279 | ||
bdb4c075 MG |
280 | /* We always use the memory representation, |
281 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
282 | switch (size) |
283 | { | |
284 | case 1: | |
df4df182 | 285 | reg->ctype = builtin_type (gdbarch)->builtin_uint8; |
ca3bf3bd DJ |
286 | break; |
287 | ||
288 | case 2: | |
df4df182 | 289 | reg->ctype = builtin_type (gdbarch)->builtin_uint16; |
ca3bf3bd DJ |
290 | break; |
291 | ||
292 | case 4: | |
df4df182 | 293 | reg->ctype = builtin_type (gdbarch)->builtin_uint32; |
ca3bf3bd DJ |
294 | break; |
295 | ||
296 | case 8: | |
df4df182 | 297 | reg->ctype = builtin_type (gdbarch)->builtin_uint64; |
ca3bf3bd DJ |
298 | break; |
299 | ||
300 | case 16: | |
df4df182 | 301 | reg->ctype = builtin_type (gdbarch)->builtin_uint128; |
ca3bf3bd DJ |
302 | break; |
303 | ||
304 | default: | |
df4df182 | 305 | for (tp = tdep->type_entries; tp != NULL; tp = tp->next) |
ca3bf3bd DJ |
306 | if (tp->size == size) |
307 | break; | |
308 | ||
309 | if (tp == NULL) | |
310 | { | |
528e1572 | 311 | std::string name = string_printf ("int%d", size * 8); |
8d749320 SM |
312 | |
313 | tp = XNEW (struct ctype_cache); | |
df4df182 UW |
314 | tp->next = tdep->type_entries; |
315 | tdep->type_entries = tp; | |
ca3bf3bd | 316 | tp->size = size; |
2d39ccd3 | 317 | type_allocator alloc (gdbarch); |
e9bb382b | 318 | tp->virtual_type |
2d39ccd3 | 319 | = init_integer_type (alloc, size * 8, 1, name.c_str ()); |
ca3bf3bd DJ |
320 | } |
321 | ||
322 | reg->ctype = tp->virtual_type; | |
323 | } | |
324 | } | |
325 | return reg->ctype; | |
326 | } | |
327 | ||
f34652de | 328 | internal_error (_("invalid register number %d"), regnum); |
ca3bf3bd DJ |
329 | return 0; |
330 | } | |
331 | ||
332 | ||
bdb4c075 | 333 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
334 | The debugging information enumerates registers starting from 0 for A0 |
335 | to n for An. So, we only have to add the base number for A0. */ | |
336 | ||
337 | static int | |
d3f73121 | 338 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
339 | { |
340 | int i; | |
08106042 | 341 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd DJ |
342 | |
343 | if (regnum >= 0 && regnum < 16) | |
345bd07c | 344 | return tdep->a0_base + regnum; |
ca3bf3bd | 345 | |
f6efe3f8 | 346 | for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) |
345bd07c | 347 | if (regnum == tdep->regmap[i].target_number) |
ca3bf3bd DJ |
348 | return i; |
349 | ||
0fde2c53 | 350 | return -1; |
ca3bf3bd DJ |
351 | } |
352 | ||
353 | ||
bdb4c075 MG |
354 | /* Write the bits of a masked register to the various registers. |
355 | Only the masked areas of these registers are modified; the other | |
356 | fields are untouched. The size of masked registers is always less | |
357 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
358 | |
359 | static void | |
9c9acae0 UW |
360 | xtensa_register_write_masked (struct regcache *regcache, |
361 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd | 362 | { |
0dd5cbc5 | 363 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
364 | const xtensa_mask_t *mask = reg->mask; |
365 | ||
366 | int shift = 0; /* Shift for next mask (mod 32). */ | |
367 | int start, size; /* Start bit and size of current mask. */ | |
368 | ||
369 | unsigned int *ptr = value; | |
370 | unsigned int regval, m, mem = 0; | |
371 | ||
372 | int bytesize = reg->byte_size; | |
373 | int bitsize = bytesize * 8; | |
374 | int i, r; | |
375 | ||
376 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
377 | ||
378 | /* Copy the masked register to host byte-order. */ | |
ac7936df | 379 | if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
380 | for (i = 0; i < bytesize; i++) |
381 | { | |
382 | mem >>= 8; | |
383 | mem |= (buffer[bytesize - i - 1] << 24); | |
384 | if ((i & 3) == 3) | |
385 | *ptr++ = mem; | |
386 | } | |
387 | else | |
388 | for (i = 0; i < bytesize; i++) | |
389 | { | |
390 | mem >>= 8; | |
391 | mem |= (buffer[i] << 24); | |
392 | if ((i & 3) == 3) | |
393 | *ptr++ = mem; | |
394 | } | |
395 | ||
396 | /* We might have to shift the final value: | |
397 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
398 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
399 | ||
400 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
401 | ptr = value; | |
402 | mem = *ptr; | |
403 | ||
404 | /* Write the bits to the masked areas of the other registers. */ | |
405 | for (i = 0; i < mask->count; i++) | |
406 | { | |
407 | start = mask->mask[i].bit_start; | |
408 | size = mask->mask[i].bit_size; | |
409 | regval = mem >> shift; | |
410 | ||
411 | if ((shift += size) > bitsize) | |
412 | error (_("size of all masks is larger than the register")); | |
413 | ||
414 | if (shift >= 32) | |
415 | { | |
416 | mem = *(++ptr); | |
417 | shift -= 32; | |
418 | bitsize -= 32; | |
419 | ||
420 | if (shift > 0) | |
421 | regval |= mem << (size - shift); | |
422 | } | |
423 | ||
424 | /* Make sure we have a valid register. */ | |
425 | r = mask->mask[i].reg_num; | |
426 | if (r >= 0 && size > 0) | |
427 | { | |
428 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
429 | ULONGEST old_val; |
430 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
431 | m = 0xffffffff >> (32 - size) << start; |
432 | regval <<= start; | |
9c9acae0 UW |
433 | regval = (regval & m) | (old_val & ~m); |
434 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
435 | } |
436 | } | |
437 | } | |
438 | ||
439 | ||
bdb4c075 MG |
440 | /* Read a tie state or mapped registers. Read the masked areas |
441 | of the registers and assemble them into a single value. */ | |
ca3bf3bd | 442 | |
05d1431c | 443 | static enum register_status |
849d0ba8 | 444 | xtensa_register_read_masked (readable_regcache *regcache, |
9c9acae0 | 445 | xtensa_register_t *reg, gdb_byte *buffer) |
ca3bf3bd | 446 | { |
0dd5cbc5 | 447 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
448 | const xtensa_mask_t *mask = reg->mask; |
449 | ||
450 | int shift = 0; | |
451 | int start, size; | |
452 | ||
453 | unsigned int *ptr = value; | |
454 | unsigned int regval, mem = 0; | |
455 | ||
456 | int bytesize = reg->byte_size; | |
457 | int bitsize = bytesize * 8; | |
458 | int i; | |
459 | ||
460 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
461 | reg->name == 0 ? "" : reg->name); | |
462 | ||
463 | /* Assemble the register from the masked areas of other registers. */ | |
464 | for (i = 0; i < mask->count; i++) | |
465 | { | |
466 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
467 | if (r >= 0) |
468 | { | |
05d1431c | 469 | enum register_status status; |
9c9acae0 | 470 | ULONGEST val; |
05d1431c | 471 | |
11f57cb6 | 472 | status = regcache->cooked_read (r, &val); |
05d1431c PA |
473 | if (status != REG_VALID) |
474 | return status; | |
9c9acae0 UW |
475 | regval = (unsigned int) val; |
476 | } | |
477 | else | |
478 | regval = 0; | |
479 | ||
ca3bf3bd DJ |
480 | start = mask->mask[i].bit_start; |
481 | size = mask->mask[i].bit_size; | |
482 | ||
483 | regval >>= start; | |
484 | ||
485 | if (size < 32) | |
486 | regval &= (0xffffffff >> (32 - size)); | |
487 | ||
488 | mem |= regval << shift; | |
489 | ||
490 | if ((shift += size) > bitsize) | |
491 | error (_("size of all masks is larger than the register")); | |
492 | ||
493 | if (shift >= 32) | |
494 | { | |
495 | *ptr++ = mem; | |
496 | bitsize -= 32; | |
497 | shift -= 32; | |
498 | ||
499 | if (shift == 0) | |
500 | mem = 0; | |
501 | else | |
502 | mem = regval >> (size - shift); | |
503 | } | |
504 | } | |
505 | ||
506 | if (shift > 0) | |
507 | *ptr = mem; | |
508 | ||
509 | /* Copy value to target byte order. */ | |
510 | ptr = value; | |
511 | mem = *ptr; | |
512 | ||
ac7936df | 513 | if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
514 | for (i = 0; i < bytesize; i++) |
515 | { | |
516 | if ((i & 3) == 0) | |
517 | mem = *ptr++; | |
518 | buffer[bytesize - i - 1] = mem & 0xff; | |
519 | mem >>= 8; | |
520 | } | |
521 | else | |
522 | for (i = 0; i < bytesize; i++) | |
523 | { | |
524 | if ((i & 3) == 0) | |
525 | mem = *ptr++; | |
526 | buffer[i] = mem & 0xff; | |
527 | mem >>= 8; | |
528 | } | |
05d1431c PA |
529 | |
530 | return REG_VALID; | |
ca3bf3bd DJ |
531 | } |
532 | ||
533 | ||
534 | /* Read pseudo registers. */ | |
535 | ||
05d1431c | 536 | static enum register_status |
ca3bf3bd | 537 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 538 | readable_regcache *regcache, |
ca3bf3bd DJ |
539 | int regnum, |
540 | gdb_byte *buffer) | |
541 | { | |
542 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
d93859e2 | 543 | regnum, xtensa_register_name (gdbarch, regnum)); |
08106042 | 544 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd | 545 | |
bdb4c075 | 546 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
345bd07c SM |
547 | if (tdep->isa_use_windowed_registers |
548 | && (regnum >= tdep->a0_base) | |
549 | && (regnum <= tdep->a0_base + 15)) | |
ca3bf3bd | 550 | { |
c185f580 | 551 | ULONGEST value; |
05d1431c | 552 | enum register_status status; |
ca3bf3bd | 553 | |
345bd07c | 554 | status = regcache->raw_read (tdep->wb_regnum, |
03f50fc8 | 555 | &value); |
05d1431c PA |
556 | if (status != REG_VALID) |
557 | return status; | |
c185f580 | 558 | regnum = arreg_number (gdbarch, regnum, value); |
ca3bf3bd DJ |
559 | } |
560 | ||
bdb4c075 | 561 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 562 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
03f50fc8 | 563 | return regcache->raw_read (regnum, buffer); |
94a0e877 | 564 | |
33b5899f | 565 | /* We have to find out how to deal with privileged registers. |
94a0e877 MG |
566 | Let's treat them as pseudo-registers, but we cannot read/write them. */ |
567 | ||
345bd07c SM |
568 | else if (tdep->call_abi == CallAbiCall0Only |
569 | || regnum < tdep->a0_base) | |
94a0e877 MG |
570 | { |
571 | buffer[0] = (gdb_byte)0; | |
572 | buffer[1] = (gdb_byte)0; | |
573 | buffer[2] = (gdb_byte)0; | |
574 | buffer[3] = (gdb_byte)0; | |
05d1431c | 575 | return REG_VALID; |
94a0e877 | 576 | } |
ca3bf3bd | 577 | /* Pseudo registers. */ |
f6efe3f8 | 578 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 579 | { |
345bd07c | 580 | xtensa_register_t *reg = &tdep->regmap[regnum]; |
ca3bf3bd | 581 | xtensa_register_type_t type = reg->type; |
345bd07c | 582 | int flags = tdep->target_flags; |
ca3bf3bd | 583 | |
bdb4c075 | 584 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
585 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
586 | { | |
587 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
588 | { | |
589 | warning (_("cannot read register %s"), | |
d93859e2 | 590 | xtensa_register_name (gdbarch, regnum)); |
05d1431c | 591 | return REG_VALID; |
ca3bf3bd DJ |
592 | } |
593 | } | |
594 | ||
595 | /* Some targets cannot read TIE register files. */ | |
596 | else if (type == xtRegisterTypeTieRegfile) | |
dda83cd7 | 597 | { |
ca3bf3bd DJ |
598 | /* Use 'fetch' to get register? */ |
599 | if (flags & xtTargetFlagsUseFetchStore) | |
600 | { | |
601 | warning (_("cannot read register")); | |
05d1431c | 602 | return REG_VALID; |
ca3bf3bd DJ |
603 | } |
604 | ||
605 | /* On some targets (esp. simulators), we can always read the reg. */ | |
606 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
607 | { | |
608 | warning (_("cannot read register")); | |
05d1431c | 609 | return REG_VALID; |
ca3bf3bd DJ |
610 | } |
611 | } | |
612 | ||
613 | /* We can always read mapped registers. */ | |
614 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
05d1431c | 615 | return xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
616 | |
617 | /* Assume that we can read the register. */ | |
03f50fc8 | 618 | return regcache->raw_read (regnum, buffer); |
ca3bf3bd | 619 | } |
ca3bf3bd | 620 | else |
f34652de | 621 | internal_error (_("invalid register number %d"), regnum); |
ca3bf3bd DJ |
622 | } |
623 | ||
624 | ||
625 | /* Write pseudo registers. */ | |
626 | ||
627 | static void | |
628 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
629 | struct regcache *regcache, | |
630 | int regnum, | |
631 | const gdb_byte *buffer) | |
632 | { | |
633 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
d93859e2 | 634 | regnum, xtensa_register_name (gdbarch, regnum)); |
08106042 | 635 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd | 636 | |
30baf67b | 637 | /* Renumber register, if aliases a0..a15 on Windowed ABI. */ |
345bd07c SM |
638 | if (tdep->isa_use_windowed_registers |
639 | && (regnum >= tdep->a0_base) | |
640 | && (regnum <= tdep->a0_base + 15)) | |
ca3bf3bd | 641 | { |
c185f580 AH |
642 | ULONGEST value; |
643 | regcache_raw_read_unsigned (regcache, | |
345bd07c | 644 | tdep->wb_regnum, &value); |
c185f580 | 645 | regnum = arreg_number (gdbarch, regnum, value); |
ca3bf3bd DJ |
646 | } |
647 | ||
648 | /* We can always write 'core' registers. | |
649 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 650 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
10eaee5f | 651 | regcache->raw_write (regnum, buffer); |
ca3bf3bd | 652 | |
33b5899f | 653 | /* We have to find out how to deal with privileged registers. |
94a0e877 MG |
654 | Let's treat them as pseudo-registers, but we cannot read/write them. */ |
655 | ||
345bd07c | 656 | else if (regnum < tdep->a0_base) |
94a0e877 MG |
657 | { |
658 | return; | |
659 | } | |
ca3bf3bd | 660 | /* Pseudo registers. */ |
f6efe3f8 | 661 | else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch)) |
ca3bf3bd | 662 | { |
345bd07c | 663 | xtensa_register_t *reg = &tdep->regmap[regnum]; |
ca3bf3bd | 664 | xtensa_register_type_t type = reg->type; |
345bd07c | 665 | int flags = tdep->target_flags; |
ca3bf3bd | 666 | |
bdb4c075 MG |
667 | /* On most targets, we cannot write registers |
668 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd | 669 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
dda83cd7 | 670 | { |
ca3bf3bd DJ |
671 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
672 | { | |
673 | warning (_("cannot write register %s"), | |
d93859e2 | 674 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
675 | return; |
676 | } | |
677 | } | |
678 | ||
679 | /* Some targets cannot read TIE register files. */ | |
680 | else if (type == xtRegisterTypeTieRegfile) | |
dda83cd7 | 681 | { |
ca3bf3bd DJ |
682 | /* Use 'store' to get register? */ |
683 | if (flags & xtTargetFlagsUseFetchStore) | |
684 | { | |
685 | warning (_("cannot write register")); | |
686 | return; | |
687 | } | |
688 | ||
689 | /* On some targets (esp. simulators), we can always write | |
690 | the register. */ | |
ca3bf3bd DJ |
691 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
692 | { | |
693 | warning (_("cannot write register")); | |
694 | return; | |
695 | } | |
696 | } | |
697 | ||
698 | /* We can always write mapped registers. */ | |
699 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
dda83cd7 | 700 | { |
9c9acae0 | 701 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
702 | return; |
703 | } | |
704 | ||
705 | /* Assume that we can write the register. */ | |
10eaee5f | 706 | regcache->raw_write (regnum, buffer); |
ca3bf3bd | 707 | } |
ca3bf3bd | 708 | else |
f34652de | 709 | internal_error (_("invalid register number %d"), regnum); |
ca3bf3bd DJ |
710 | } |
711 | ||
e7fe1011 AB |
712 | static const reggroup *xtensa_ar_reggroup; |
713 | static const reggroup *xtensa_user_reggroup; | |
714 | static const reggroup *xtensa_vectra_reggroup; | |
715 | static const reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; | |
ca3bf3bd DJ |
716 | |
717 | static void | |
718 | xtensa_init_reggroups (void) | |
719 | { | |
98689b25 | 720 | int i; |
98689b25 | 721 | |
ca3bf3bd DJ |
722 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); |
723 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
724 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 725 | |
98689b25 | 726 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
8579fd13 AB |
727 | xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i).release (), |
728 | USER_REGGROUP); | |
7b871568 | 729 | } |
ca3bf3bd DJ |
730 | |
731 | static void | |
732 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
733 | { | |
7b871568 MG |
734 | /* Xtensa-specific groups. */ |
735 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
736 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
737 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 738 | |
e7d69e72 | 739 | for (int i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
7b871568 | 740 | reggroup_add (gdbarch, xtensa_cp[i]); |
ca3bf3bd DJ |
741 | } |
742 | ||
7b871568 | 743 | static int |
dbf5d61b | 744 | xtensa_coprocessor_register_group (const struct reggroup *group) |
7b871568 MG |
745 | { |
746 | int i; | |
747 | ||
748 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
749 | if (group == xtensa_cp[i]) | |
750 | return i; | |
751 | ||
752 | return -1; | |
753 | } | |
ca3bf3bd DJ |
754 | |
755 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
756 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
757 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
758 | ||
759 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
760 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
761 | ||
762 | static int | |
763 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
764 | int regnum, | |
dbf5d61b | 765 | const struct reggroup *group) |
ca3bf3bd | 766 | { |
08106042 | 767 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 768 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd DJ |
769 | xtensa_register_type_t type = reg->type; |
770 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 771 | int cp_number; |
ca3bf3bd | 772 | |
57041825 MG |
773 | if (group == save_reggroup) |
774 | /* Every single register should be included into the list of registers | |
775 | to be watched for changes while using -data-list-changed-registers. */ | |
776 | return 1; | |
777 | ||
ca3bf3bd DJ |
778 | /* First, skip registers that are not visible to this target |
779 | (unknown and unmapped registers when not using ISS). */ | |
780 | ||
781 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
782 | return 0; | |
783 | if (group == all_reggroup) | |
784 | return 1; | |
785 | if (group == xtensa_ar_reggroup) | |
786 | return rg & xtRegisterGroupAddrReg; | |
787 | if (group == xtensa_user_reggroup) | |
788 | return rg & xtRegisterGroupUser; | |
789 | if (group == float_reggroup) | |
790 | return rg & xtRegisterGroupFloat; | |
791 | if (group == general_reggroup) | |
792 | return rg & xtRegisterGroupGeneral; | |
ca3bf3bd DJ |
793 | if (group == system_reggroup) |
794 | return rg & xtRegisterGroupState; | |
795 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
796 | return rg & xtRegisterGroupVectra; | |
57041825 | 797 | if (group == restore_reggroup) |
6b50c0b0 | 798 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 799 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
1448a0a2 PM |
800 | cp_number = xtensa_coprocessor_register_group (group); |
801 | if (cp_number >= 0) | |
7b871568 | 802 | return rg & (xtRegisterGroupCP0 << cp_number); |
ca3bf3bd DJ |
803 | else |
804 | return 1; | |
805 | } | |
806 | ||
807 | ||
ca3bf3bd DJ |
808 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
809 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 810 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
811 | |
812 | static void | |
813 | xtensa_supply_gregset (const struct regset *regset, | |
814 | struct regcache *rc, | |
815 | int regnum, | |
816 | const void *gregs, | |
817 | size_t len) | |
818 | { | |
19ba03f4 | 819 | const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs; |
ac7936df | 820 | struct gdbarch *gdbarch = rc->arch (); |
08106042 | 821 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd DJ |
822 | int i; |
823 | ||
cce7e648 | 824 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); |
ca3bf3bd | 825 | |
6b50c0b0 | 826 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
73e1c03f | 827 | rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); |
6b50c0b0 | 828 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) |
73e1c03f | 829 | rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); |
345bd07c SM |
830 | if (regnum == tdep->wb_regnum || regnum == -1) |
831 | rc->raw_supply (tdep->wb_regnum, | |
73e1c03f | 832 | (char *) ®s->windowbase); |
345bd07c SM |
833 | if (regnum == tdep->ws_regnum || regnum == -1) |
834 | rc->raw_supply (tdep->ws_regnum, | |
73e1c03f | 835 | (char *) ®s->windowstart); |
345bd07c SM |
836 | if (regnum == tdep->lbeg_regnum || regnum == -1) |
837 | rc->raw_supply (tdep->lbeg_regnum, | |
73e1c03f | 838 | (char *) ®s->lbeg); |
345bd07c SM |
839 | if (regnum == tdep->lend_regnum || regnum == -1) |
840 | rc->raw_supply (tdep->lend_regnum, | |
73e1c03f | 841 | (char *) ®s->lend); |
345bd07c SM |
842 | if (regnum == tdep->lcount_regnum || regnum == -1) |
843 | rc->raw_supply (tdep->lcount_regnum, | |
73e1c03f | 844 | (char *) ®s->lcount); |
345bd07c SM |
845 | if (regnum == tdep->sar_regnum || regnum == -1) |
846 | rc->raw_supply (tdep->sar_regnum, | |
73e1c03f | 847 | (char *) ®s->sar); |
345bd07c SM |
848 | if (regnum >=tdep->ar_base |
849 | && regnum < tdep->ar_base | |
850 | + tdep->num_aregs) | |
73e1c03f | 851 | rc->raw_supply |
345bd07c | 852 | (regnum, (char *) ®s->ar[regnum - tdep->ar_base]); |
ca3bf3bd DJ |
853 | else if (regnum == -1) |
854 | { | |
345bd07c SM |
855 | for (i = 0; i < tdep->num_aregs; ++i) |
856 | rc->raw_supply (tdep->ar_base + i, | |
73e1c03f | 857 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
858 | } |
859 | } | |
860 | ||
861 | ||
862 | /* Xtensa register set. */ | |
863 | ||
864 | static struct regset | |
865 | xtensa_gregset = | |
866 | { | |
867 | NULL, | |
868 | xtensa_supply_gregset | |
869 | }; | |
870 | ||
871 | ||
97094034 | 872 | /* Iterate over supported core file register note sections. */ |
ca3bf3bd | 873 | |
97094034 AA |
874 | static void |
875 | xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
876 | iterate_over_regset_sections_cb *cb, | |
877 | void *cb_data, | |
878 | const struct regcache *regcache) | |
ca3bf3bd | 879 | { |
97094034 | 880 | DEBUGTRACE ("xtensa_iterate_over_regset_sections\n"); |
ca3bf3bd | 881 | |
a616bb94 AH |
882 | cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t), |
883 | &xtensa_gregset, NULL, cb_data); | |
ca3bf3bd DJ |
884 | } |
885 | ||
886 | ||
bdb4c075 | 887 | /* Handling frames. */ |
ca3bf3bd | 888 | |
bdb4c075 MG |
889 | /* Number of registers to save in case of Windowed ABI. */ |
890 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 891 | |
bdb4c075 MG |
892 | /* Frame cache part for Windowed ABI. */ |
893 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 894 | { |
ee967b5f MG |
895 | int wb; /* WINDOWBASE of the previous frame. */ |
896 | int callsize; /* Call size of this frame. */ | |
08b9c608 MG |
897 | int ws; /* WINDOWSTART of the previous frame. It keeps track of |
898 | life windows only. If there is no bit set for the | |
899 | window, that means it had been already spilled | |
900 | because of window overflow. */ | |
901 | ||
902 | /* Addresses of spilled A-registers. | |
903 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 904 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
905 | } xtensa_windowed_frame_cache_t; |
906 | ||
907 | /* Call0 ABI Definitions. */ | |
908 | ||
581e13c1 MS |
909 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue |
910 | analysis. */ | |
bdb4c075 MG |
911 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ |
912 | #define C0_SP 1 /* Register used as SP. */ | |
913 | #define C0_FP 15 /* Register used as FP. */ | |
914 | #define C0_RA 0 /* Register used as return address. */ | |
915 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
916 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
917 | ||
918 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
919 | A-register where the current content of the reg came from (in terms | |
920 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
85102364 | 921 | mean that the original content of the register was saved to the stack. |
bdb4c075 MG |
922 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't |
923 | know where SP will end up until the entire prologue has been analyzed. */ | |
924 | ||
925 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
926 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
927 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
928 | ||
929 | extern xtensa_isa xtensa_default_isa; | |
930 | ||
931 | typedef struct xtensa_c0reg | |
932 | { | |
dbab50de MG |
933 | int fr_reg; /* original register from which register content |
934 | is derived, or C0_CONST, or C0_INEXP. */ | |
935 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
936 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
937 | or C0_NOSTK if register has not been saved. */ | |
bdb4c075 MG |
938 | } xtensa_c0reg_t; |
939 | ||
bdb4c075 MG |
940 | /* Frame cache part for Call0 ABI. */ |
941 | typedef struct xtensa_call0_frame_cache | |
942 | { | |
dbab50de MG |
943 | int c0_frmsz; /* Stack frame size. */ |
944 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
945 | int fp_regnum; /* A-register used as FP. */ | |
946 | int c0_fp; /* Actual value of frame pointer. */ | |
85102364 | 947 | int c0_fpalign; /* Dynamic adjustment for the stack |
dbab50de MG |
948 | pointer. It's an AND mask. Zero, |
949 | if alignment was not adjusted. */ | |
950 | int c0_old_sp; /* In case of dynamic adjustment, it is | |
951 | a register holding unaligned sp. | |
952 | C0_INEXP, when undefined. */ | |
953 | int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a | |
954 | stack offset. C0_NOSTK otherwise. */ | |
955 | ||
956 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
bdb4c075 MG |
957 | } xtensa_call0_frame_cache_t; |
958 | ||
959 | typedef struct xtensa_frame_cache | |
960 | { | |
ee967b5f | 961 | CORE_ADDR base; /* Stack pointer of this frame. */ |
08b9c608 MG |
962 | CORE_ADDR pc; /* PC of this frame at the function entry point. */ |
963 | CORE_ADDR ra; /* The raw return address of this frame. */ | |
964 | CORE_ADDR ps; /* The PS register of the previous (older) frame. */ | |
965 | CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */ | |
bdb4c075 MG |
966 | int call0; /* It's a call0 framework (else windowed). */ |
967 | union | |
968 | { | |
969 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
970 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
971 | }; | |
ca3bf3bd DJ |
972 | } xtensa_frame_cache_t; |
973 | ||
974 | ||
975 | static struct xtensa_frame_cache * | |
bdb4c075 | 976 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
977 | { |
978 | xtensa_frame_cache_t *cache; | |
979 | int i; | |
980 | ||
981 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
982 | ||
983 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
984 | ||
985 | cache->base = 0; | |
986 | cache->pc = 0; | |
987 | cache->ra = 0; | |
ca3bf3bd | 988 | cache->ps = 0; |
ca3bf3bd | 989 | cache->prev_sp = 0; |
bdb4c075 MG |
990 | cache->call0 = !windowed; |
991 | if (cache->call0) | |
992 | { | |
993 | cache->c0.c0_frmsz = -1; | |
994 | cache->c0.c0_hasfp = 0; | |
995 | cache->c0.fp_regnum = -1; | |
996 | cache->c0.c0_fp = -1; | |
dbab50de MG |
997 | cache->c0.c0_fpalign = 0; |
998 | cache->c0.c0_old_sp = C0_INEXP; | |
999 | cache->c0.c0_sp_ofs = C0_NOSTK; | |
ca3bf3bd | 1000 | |
bdb4c075 MG |
1001 | for (i = 0; i < C0_NREGS; i++) |
1002 | { | |
1003 | cache->c0.c0_rt[i].fr_reg = i; | |
1004 | cache->c0.c0_rt[i].fr_ofs = 0; | |
1005 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
1006 | } | |
1007 | } | |
1008 | else | |
1009 | { | |
1010 | cache->wd.wb = 0; | |
ee967b5f | 1011 | cache->wd.ws = 0; |
bdb4c075 | 1012 | cache->wd.callsize = -1; |
ca3bf3bd | 1013 | |
bdb4c075 MG |
1014 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1015 | cache->wd.aregs[i] = -1; | |
1016 | } | |
ca3bf3bd DJ |
1017 | return cache; |
1018 | } | |
1019 | ||
1020 | ||
1021 | static CORE_ADDR | |
1022 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1023 | { | |
1024 | return address & ~15; | |
1025 | } | |
1026 | ||
1027 | ||
1028 | static CORE_ADDR | |
bd2b40ac | 1029 | xtensa_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
ca3bf3bd | 1030 | { |
ff7a4c00 | 1031 | gdb_byte buf[8]; |
0dfff4cb | 1032 | CORE_ADDR pc; |
ca3bf3bd | 1033 | |
a74ce742 | 1034 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
bd2b40ac | 1035 | host_address_to_string (next_frame.get ())); |
ca3bf3bd | 1036 | |
6b50c0b0 | 1037 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1038 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1039 | |
0dfff4cb | 1040 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1041 | |
0dfff4cb | 1042 | return pc; |
ca3bf3bd DJ |
1043 | } |
1044 | ||
1045 | ||
1046 | static struct frame_id | |
bd2b40ac | 1047 | xtensa_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
ca3bf3bd DJ |
1048 | { |
1049 | CORE_ADDR pc, fp; | |
08106042 | 1050 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd | 1051 | |
5142f611 | 1052 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1053 | |
5142f611 MG |
1054 | pc = get_frame_pc (this_frame); |
1055 | fp = get_frame_register_unsigned | |
345bd07c | 1056 | (this_frame, tdep->a0_base + 1); |
ca3bf3bd DJ |
1057 | |
1058 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1059 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1060 | } |
1061 | ||
08b9c608 MG |
1062 | /* Returns true, if instruction to execute next is unique to Xtensa Window |
1063 | Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */ | |
1064 | ||
1065 | static int | |
1066 | xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1067 | { | |
1068 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1069 | unsigned int insn = read_memory_integer (pc, 4, byte_order); | |
1070 | unsigned int code; | |
1071 | ||
1072 | if (byte_order == BFD_ENDIAN_BIG) | |
1073 | { | |
1074 | /* Check, if this is L32E or S32E. */ | |
1075 | code = insn & 0xf000ff00; | |
1076 | if ((code == 0x00009000) || (code == 0x00009400)) | |
1077 | return 1; | |
1078 | /* Check, if this is RFWU or RFWO. */ | |
1079 | code = insn & 0xffffff00; | |
1080 | return ((code == 0x00430000) || (code == 0x00530000)); | |
1081 | } | |
1082 | else | |
1083 | { | |
1084 | /* Check, if this is L32E or S32E. */ | |
1085 | code = insn & 0x00ff000f; | |
1086 | if ((code == 0x090000) || (code == 0x490000)) | |
1087 | return 1; | |
1088 | /* Check, if this is RFWU or RFWO. */ | |
1089 | code = insn & 0x00ffffff; | |
1090 | return ((code == 0x00003400) || (code == 0x00003500)); | |
1091 | } | |
1092 | } | |
1093 | ||
ee967b5f MG |
1094 | /* Returns the best guess about which register is a frame pointer |
1095 | for the function containing CURRENT_PC. */ | |
1096 | ||
d4709618 MG |
1097 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ |
1098 | #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ | |
ee967b5f MG |
1099 | |
1100 | static unsigned int | |
1101 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1102 | { | |
1103 | #define RETURN_FP goto done | |
1104 | ||
08106042 | 1105 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 1106 | unsigned int fp_regnum = tdep->a0_base + 1; |
ee967b5f MG |
1107 | CORE_ADDR start_addr; |
1108 | xtensa_isa isa; | |
1109 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1110 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
ee967b5f MG |
1111 | CORE_ADDR ia, bt, ba; |
1112 | xtensa_format ifmt; | |
1113 | int ilen, islots, is; | |
1114 | xtensa_opcode opc; | |
1115 | const char *opcname; | |
1116 | ||
1117 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1118 | if (start_addr == 0) | |
1119 | return fp_regnum; | |
1120 | ||
ee967b5f MG |
1121 | isa = xtensa_default_isa; |
1122 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1123 | ins = xtensa_insnbuf_alloc (isa); | |
1124 | slot = xtensa_insnbuf_alloc (isa); | |
1125 | ba = 0; | |
1126 | ||
1127 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1128 | { | |
1129 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 1130 | { |
ee967b5f MG |
1131 | ba = ia; |
1132 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1133 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
d4709618 MG |
1134 | if (target_read_memory (ba, ibuf, bt - ba) != 0) |
1135 | RETURN_FP; | |
ee967b5f MG |
1136 | } |
1137 | ||
1138 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1139 | ifmt = xtensa_format_decode (isa, ins); | |
1140 | if (ifmt == XTENSA_UNDEFINED) | |
1141 | RETURN_FP; | |
1142 | ilen = xtensa_format_length (isa, ifmt); | |
1143 | if (ilen == XTENSA_UNDEFINED) | |
1144 | RETURN_FP; | |
1145 | islots = xtensa_format_num_slots (isa, ifmt); | |
1146 | if (islots == XTENSA_UNDEFINED) | |
1147 | RETURN_FP; | |
1148 | ||
1149 | for (is = 0; is < islots; ++is) | |
1150 | { | |
1151 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1152 | RETURN_FP; | |
1153 | ||
1154 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1155 | if (opc == XTENSA_UNDEFINED) | |
1156 | RETURN_FP; | |
1157 | ||
1158 | opcname = xtensa_opcode_name (isa, opc); | |
1159 | ||
1160 | if (strcasecmp (opcname, "mov.n") == 0 | |
1161 | || strcasecmp (opcname, "or") == 0) | |
1162 | { | |
1163 | unsigned int register_operand; | |
1164 | ||
1165 | /* Possible candidate for setting frame pointer | |
581e13c1 | 1166 | from A1. This is what we are looking for. */ |
ee967b5f MG |
1167 | |
1168 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1169 | is, slot, ®ister_operand) != 0) | |
1170 | RETURN_FP; | |
1171 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1172 | RETURN_FP; | |
1173 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1174 | { | |
1175 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1176 | ®ister_operand) != 0) | |
1177 | RETURN_FP; | |
1178 | if (xtensa_operand_decode (isa, opc, 0, | |
1179 | ®ister_operand) != 0) | |
1180 | RETURN_FP; | |
1181 | ||
581e13c1 | 1182 | fp_regnum |
345bd07c | 1183 | = tdep->a0_base + register_operand; |
ee967b5f MG |
1184 | RETURN_FP; |
1185 | } | |
1186 | } | |
1187 | ||
1188 | if ( | |
1189 | /* We have problems decoding the memory. */ | |
1190 | opcname == NULL | |
1191 | || strcasecmp (opcname, "ill") == 0 | |
1192 | || strcasecmp (opcname, "ill.n") == 0 | |
1193 | /* Hit planted breakpoint. */ | |
1194 | || strcasecmp (opcname, "break") == 0 | |
1195 | || strcasecmp (opcname, "break.n") == 0 | |
1196 | /* Flow control instructions finish prologue. */ | |
1197 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1198 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1199 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1200 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1201 | || strcasecmp (opcname, "simcall") == 0 | |
1202 | || strcasecmp (opcname, "syscall") == 0) | |
1203 | /* Can not continue analysis. */ | |
1204 | RETURN_FP; | |
1205 | } | |
1206 | } | |
1207 | done: | |
1208 | xtensa_insnbuf_free(isa, slot); | |
1209 | xtensa_insnbuf_free(isa, ins); | |
1210 | return fp_regnum; | |
1211 | } | |
1212 | ||
bdb4c075 MG |
1213 | /* The key values to identify the frame using "cache" are |
1214 | ||
ee967b5f | 1215 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 | 1216 | cache->pc = entry-PC (entry point of the frame function); |
581e13c1 | 1217 | cache->prev_sp = SP of the previous frame. */ |
bdb4c075 MG |
1218 | |
1219 | static void | |
bd2b40ac | 1220 | call0_frame_cache (frame_info_ptr this_frame, |
dbab50de | 1221 | xtensa_frame_cache_t *cache, CORE_ADDR pc); |
ca3bf3bd | 1222 | |
08b9c608 | 1223 | static void |
bd2b40ac | 1224 | xtensa_window_interrupt_frame_cache (frame_info_ptr this_frame, |
08b9c608 MG |
1225 | xtensa_frame_cache_t *cache, |
1226 | CORE_ADDR pc); | |
1227 | ||
ca3bf3bd | 1228 | static struct xtensa_frame_cache * |
bd2b40ac | 1229 | xtensa_frame_cache (frame_info_ptr this_frame, void **this_cache) |
ca3bf3bd DJ |
1230 | { |
1231 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1232 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1233 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1234 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ee967b5f | 1235 | unsigned int fp_regnum; |
98689b25 | 1236 | int windowed, ps_regnum; |
ca3bf3bd | 1237 | |
ca3bf3bd | 1238 | if (*this_cache) |
19ba03f4 | 1239 | return (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1240 | |
98689b25 MG |
1241 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
1242 | ps_regnum = gdbarch_ps_regnum (gdbarch); | |
68d6df83 MG |
1243 | ps = (ps_regnum >= 0 |
1244 | ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS); | |
98689b25 MG |
1245 | |
1246 | windowed = windowing_enabled (gdbarch, ps); | |
bdb4c075 | 1247 | |
ca3bf3bd | 1248 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1249 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1250 | *this_cache = cache; |
1251 | ||
bdb4c075 | 1252 | if (windowed) |
ca3bf3bd | 1253 | { |
a08b52b5 | 1254 | LONGEST op1; |
08106042 | 1255 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
98689b25 | 1256 | |
bdb4c075 | 1257 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 | 1258 | wb = get_frame_register_unsigned (this_frame, |
345bd07c | 1259 | tdep->wb_regnum); |
5142f611 | 1260 | ws = get_frame_register_unsigned (this_frame, |
345bd07c | 1261 | tdep->ws_regnum); |
ca3bf3bd | 1262 | |
a08b52b5 MF |
1263 | if (safe_read_memory_integer (pc, 1, byte_order, &op1) |
1264 | && XTENSA_IS_ENTRY (gdbarch, op1)) | |
ca3bf3bd | 1265 | { |
bdb4c075 | 1266 | int callinc = CALLINC (ps); |
5142f611 | 1267 | ra = get_frame_register_unsigned |
345bd07c | 1268 | (this_frame, tdep->a0_base + callinc * 4); |
bdb4c075 MG |
1269 | |
1270 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1271 | cache->wd.callsize = 0; | |
1272 | cache->wd.wb = wb; | |
1273 | cache->wd.ws = ws; | |
5142f611 | 1274 | cache->prev_sp = get_frame_register_unsigned |
345bd07c | 1275 | (this_frame, tdep->a0_base + 1); |
ee967b5f MG |
1276 | |
1277 | /* This only can be the outermost frame since we are | |
1278 | just about to execute ENTRY. SP hasn't been set yet. | |
1279 | We can assume any frame size, because it does not | |
1280 | matter, and, let's fake frame base in cache. */ | |
98689b25 | 1281 | cache->base = cache->prev_sp - 16; |
ee967b5f MG |
1282 | |
1283 | cache->pc = pc; | |
1284 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1285 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1286 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1287 | ||
1288 | return cache; | |
bdb4c075 MG |
1289 | } |
1290 | else | |
1291 | { | |
ee967b5f | 1292 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 | 1293 | ra = get_frame_register_unsigned (this_frame, |
345bd07c | 1294 | tdep->a0_base); |
bdb4c075 | 1295 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1296 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
345bd07c | 1297 | & (tdep->num_aregs / 4 - 1); |
bdb4c075 | 1298 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1299 | |
5142f611 | 1300 | cache->pc = get_frame_func (this_frame); |
f6402f18 | 1301 | cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); |
ee967b5f MG |
1302 | cache->ps = (ps & ~PS_CALLINC_MASK) |
1303 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1304 | } | |
bdb4c075 MG |
1305 | |
1306 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1307 | { |
bdb4c075 | 1308 | int i; |
ca3bf3bd | 1309 | |
bdb4c075 | 1310 | /* Set A0...A3. */ |
5142f611 | 1311 | sp = get_frame_register_unsigned |
345bd07c | 1312 | (this_frame, tdep->a0_base + 1) - 16; |
bdb4c075 MG |
1313 | |
1314 | for (i = 0; i < 4; i++, sp += 4) | |
1315 | { | |
1316 | cache->wd.aregs[i] = sp; | |
1317 | } | |
ca3bf3bd | 1318 | |
bdb4c075 | 1319 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1320 | { |
bdb4c075 | 1321 | /* Set A4...A7/A11. */ |
ee967b5f | 1322 | /* Get the SP of the frame previous to the previous one. |
dda83cd7 | 1323 | To achieve this, we have to dereference SP twice. */ |
e17a4113 UW |
1324 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); |
1325 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); | |
bdb4c075 MG |
1326 | sp -= cache->wd.callsize * 4; |
1327 | ||
ee967b5f | 1328 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1329 | { |
1330 | cache->wd.aregs[i] = sp; | |
1331 | } | |
ca3bf3bd DJ |
1332 | } |
1333 | } | |
ca3bf3bd | 1334 | |
bdb4c075 | 1335 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
08b9c608 MG |
1336 | /* If RA is equal to 0 this frame is an outermost frame. Leave |
1337 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1338 | { |
ee967b5f | 1339 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1340 | { |
1341 | /* Register window overflow already happened. | |
85102364 | 1342 | We can read caller's SP from the proper spill location. */ |
5142f611 | 1343 | sp = get_frame_register_unsigned |
345bd07c | 1344 | (this_frame, tdep->a0_base + 1); |
e17a4113 | 1345 | cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); |
bdb4c075 MG |
1346 | } |
1347 | else | |
1348 | { | |
1349 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1350 | int regnum = arreg_number |
345bd07c | 1351 | (gdbarch, tdep->a0_base + 1, |
304fe255 | 1352 | cache->wd.wb); |
ca3bf3bd | 1353 | |
08b9c608 | 1354 | cache->prev_sp = xtensa_read_register (regnum); |
bdb4c075 | 1355 | } |
ca3bf3bd DJ |
1356 | } |
1357 | } | |
08b9c608 MG |
1358 | else if (xtensa_window_interrupt_insn (gdbarch, pc)) |
1359 | { | |
1360 | /* Execution stopped inside Xtensa Window Interrupt Handler. */ | |
1361 | ||
1362 | xtensa_window_interrupt_frame_cache (this_frame, cache, pc); | |
1363 | /* Everything was set already, including cache->base. */ | |
1364 | return cache; | |
1365 | } | |
bdb4c075 MG |
1366 | else /* Call0 framework. */ |
1367 | { | |
dbab50de | 1368 | call0_frame_cache (this_frame, cache, pc); |
ee967b5f | 1369 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1370 | } |
ca3bf3bd | 1371 | |
5142f611 | 1372 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1373 | |
ca3bf3bd DJ |
1374 | return cache; |
1375 | } | |
1376 | ||
dbab50de MG |
1377 | static int xtensa_session_once_reported = 1; |
1378 | ||
1379 | /* Report a problem with prologue analysis while doing backtracing. | |
85102364 | 1380 | But, do it only once to avoid annoying repeated messages. */ |
dbab50de | 1381 | |
4e6ca6d5 MG |
1382 | static void |
1383 | warning_once (void) | |
dbab50de MG |
1384 | { |
1385 | if (xtensa_session_once_reported == 0) | |
1386 | warning (_("\ | |
1387 | \nUnrecognised function prologue. Stack trace cannot be resolved. \ | |
1388 | This message will not be repeated in this session.\n")); | |
1389 | ||
1390 | xtensa_session_once_reported = 1; | |
1391 | } | |
1392 | ||
1393 | ||
ca3bf3bd | 1394 | static void |
bd2b40ac | 1395 | xtensa_frame_this_id (frame_info_ptr this_frame, |
ca3bf3bd DJ |
1396 | void **this_cache, |
1397 | struct frame_id *this_id) | |
1398 | { | |
1399 | struct xtensa_frame_cache *cache = | |
5142f611 | 1400 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1401 | |
1402 | if (cache->prev_sp == 0) | |
1403 | return; | |
1404 | ||
5142f611 | 1405 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1406 | } |
ca3bf3bd | 1407 | |
5142f611 | 1408 | static struct value * |
bd2b40ac | 1409 | xtensa_frame_prev_register (frame_info_ptr this_frame, |
ca3bf3bd | 1410 | void **this_cache, |
5142f611 | 1411 | int regnum) |
ca3bf3bd | 1412 | { |
5142f611 MG |
1413 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1414 | struct xtensa_frame_cache *cache; | |
1415 | ULONGEST saved_reg = 0; | |
ca3bf3bd | 1416 | int done = 1; |
08106042 | 1417 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd | 1418 | |
5142f611 MG |
1419 | if (*this_cache == NULL) |
1420 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
19ba03f4 | 1421 | cache = (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1422 | |
6b50c0b0 | 1423 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1424 | saved_reg = cache->ra; |
345bd07c | 1425 | else if (regnum == tdep->a0_base + 1) |
bdb4c075 MG |
1426 | saved_reg = cache->prev_sp; |
1427 | else if (!cache->call0) | |
ca3bf3bd | 1428 | { |
345bd07c | 1429 | if (regnum == tdep->ws_regnum) |
ee967b5f | 1430 | saved_reg = cache->wd.ws; |
345bd07c | 1431 | else if (regnum == tdep->wb_regnum) |
bdb4c075 | 1432 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1433 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1434 | saved_reg = cache->ps; |
ca3bf3bd | 1435 | else |
bdb4c075 | 1436 | done = 0; |
ca3bf3bd | 1437 | } |
ca3bf3bd DJ |
1438 | else |
1439 | done = 0; | |
1440 | ||
1441 | if (done) | |
5142f611 | 1442 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1443 | |
bdb4c075 | 1444 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1445 | { |
ee967b5f MG |
1446 | /* Convert A-register numbers to AR-register numbers, |
1447 | if we deal with A-register. */ | |
345bd07c SM |
1448 | if (regnum >= tdep->a0_base |
1449 | && regnum <= tdep->a0_base + 15) | |
ee967b5f | 1450 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1451 | |
ee967b5f | 1452 | /* Check, if we deal with AR-register saved on stack. */ |
345bd07c SM |
1453 | if (regnum >= tdep->ar_base |
1454 | && regnum <= (tdep->ar_base | |
1455 | + tdep->num_aregs)) | |
bdb4c075 | 1456 | { |
ee967b5f | 1457 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1458 | |
bdb4c075 MG |
1459 | if (areg >= 0 |
1460 | && areg < XTENSA_NUM_SAVED_AREGS | |
1461 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1462 | return frame_unwind_got_memory (this_frame, regnum, |
1463 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1464 | } |
1465 | } | |
bdb4c075 MG |
1466 | else /* Call0 ABI. */ |
1467 | { | |
345bd07c SM |
1468 | int reg = (regnum >= tdep->ar_base |
1469 | && regnum <= (tdep->ar_base | |
304fe255 | 1470 | + C0_NREGS)) |
345bd07c | 1471 | ? regnum - tdep->ar_base : regnum; |
ca3bf3bd | 1472 | |
bdb4c075 MG |
1473 | if (reg < C0_NREGS) |
1474 | { | |
1475 | CORE_ADDR spe; | |
1476 | int stkofs; | |
1477 | ||
1478 | /* If register was saved in the prologue, retrieve it. */ | |
1479 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1480 | if (stkofs != C0_NOSTK) | |
1481 | { | |
1482 | /* Determine SP on entry based on FP. */ | |
1483 | spe = cache->c0.c0_fp | |
1484 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 | 1485 | |
581e13c1 MS |
1486 | return frame_unwind_got_memory (this_frame, regnum, |
1487 | spe + stkofs); | |
bdb4c075 MG |
1488 | } |
1489 | } | |
1490 | } | |
1491 | ||
1492 | /* All other registers have been either saved to | |
1493 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1494 | |
5142f611 | 1495 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1496 | } |
1497 | ||
1498 | ||
1499 | static const struct frame_unwind | |
5142f611 | 1500 | xtensa_unwind = |
ca3bf3bd | 1501 | { |
a154d838 | 1502 | "xtensa prologue", |
ca3bf3bd | 1503 | NORMAL_FRAME, |
8fbca658 | 1504 | default_frame_unwind_stop_reason, |
ca3bf3bd | 1505 | xtensa_frame_this_id, |
5142f611 MG |
1506 | xtensa_frame_prev_register, |
1507 | NULL, | |
1508 | default_frame_sniffer | |
ca3bf3bd DJ |
1509 | }; |
1510 | ||
ca3bf3bd | 1511 | static CORE_ADDR |
bd2b40ac | 1512 | xtensa_frame_base_address (frame_info_ptr this_frame, void **this_cache) |
ca3bf3bd DJ |
1513 | { |
1514 | struct xtensa_frame_cache *cache = | |
5142f611 | 1515 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1516 | |
1517 | return cache->base; | |
1518 | } | |
1519 | ||
1520 | static const struct frame_base | |
1521 | xtensa_frame_base = | |
1522 | { | |
5142f611 | 1523 | &xtensa_unwind, |
ca3bf3bd DJ |
1524 | xtensa_frame_base_address, |
1525 | xtensa_frame_base_address, | |
1526 | xtensa_frame_base_address | |
1527 | }; | |
1528 | ||
1529 | ||
1530 | static void | |
1531 | xtensa_extract_return_value (struct type *type, | |
1532 | struct regcache *regcache, | |
1533 | void *dst) | |
1534 | { | |
ac7936df | 1535 | struct gdbarch *gdbarch = regcache->arch (); |
19ba03f4 | 1536 | bfd_byte *valbuf = (bfd_byte *) dst; |
df86565b | 1537 | int len = type->length (); |
ca3bf3bd DJ |
1538 | ULONGEST pc, wb; |
1539 | int callsize, areg; | |
1540 | int offset = 0; | |
1541 | ||
1542 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1543 | ||
1544 | gdb_assert(len > 0); | |
1545 | ||
08106042 | 1546 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 1547 | if (tdep->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1548 | { |
1549 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1550 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1551 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1552 | |
bdb4c075 MG |
1553 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1554 | if (len > (callsize > 8 ? 8 : 16)) | |
f34652de | 1555 | internal_error (_("cannot extract return value of %d bytes long"), |
581e13c1 | 1556 | len); |
ca3bf3bd | 1557 | |
bdb4c075 MG |
1558 | /* Get the register offset of the return |
1559 | register (A2) in the caller window. */ | |
304fe255 | 1560 | regcache_raw_read_unsigned |
345bd07c | 1561 | (regcache, tdep->wb_regnum, &wb); |
ee967b5f | 1562 | areg = arreg_number (gdbarch, |
345bd07c | 1563 | tdep->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1564 | } |
1565 | else | |
1566 | { | |
1567 | /* No windowing hardware - Call0 ABI. */ | |
345bd07c | 1568 | areg = tdep->a0_base + C0_ARGS; |
bdb4c075 | 1569 | } |
ca3bf3bd DJ |
1570 | |
1571 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1572 | ||
6b50c0b0 | 1573 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1574 | offset = 4 - len; |
1575 | ||
1576 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1577 | { | |
1578 | if (len < 4) | |
502fe83e | 1579 | regcache->raw_read_part (areg, offset, len, valbuf); |
ca3bf3bd | 1580 | else |
0b883586 | 1581 | regcache->raw_read (areg, valbuf); |
ca3bf3bd DJ |
1582 | } |
1583 | } | |
1584 | ||
1585 | ||
1586 | static void | |
1587 | xtensa_store_return_value (struct type *type, | |
1588 | struct regcache *regcache, | |
1589 | const void *dst) | |
1590 | { | |
ac7936df | 1591 | struct gdbarch *gdbarch = regcache->arch (); |
19ba03f4 | 1592 | const bfd_byte *valbuf = (const bfd_byte *) dst; |
ca3bf3bd DJ |
1593 | unsigned int areg; |
1594 | ULONGEST pc, wb; | |
1595 | int callsize; | |
df86565b | 1596 | int len = type->length (); |
ca3bf3bd DJ |
1597 | int offset = 0; |
1598 | ||
1599 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1600 | ||
08106042 | 1601 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 1602 | if (tdep->call_abi != CallAbiCall0Only) |
bdb4c075 | 1603 | { |
6b50c0b0 | 1604 | regcache_raw_read_unsigned |
345bd07c | 1605 | (regcache, tdep->wb_regnum, &wb); |
6b50c0b0 | 1606 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1607 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1608 | |
bdb4c075 | 1609 | if (len > (callsize > 8 ? 8 : 16)) |
f34652de | 1610 | internal_error (_("unimplemented for this length: %s"), |
df86565b | 1611 | pulongest (type->length ())); |
ee967b5f | 1612 | areg = arreg_number (gdbarch, |
345bd07c | 1613 | tdep->a0_base + 2 + callsize, wb); |
ca3bf3bd | 1614 | |
bdb4c075 | 1615 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
dda83cd7 | 1616 | callsize, (int) wb); |
bdb4c075 MG |
1617 | } |
1618 | else | |
1619 | { | |
345bd07c | 1620 | areg = tdep->a0_base + C0_ARGS; |
bdb4c075 | 1621 | } |
ca3bf3bd | 1622 | |
6b50c0b0 | 1623 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1624 | offset = 4 - len; |
1625 | ||
ca3bf3bd DJ |
1626 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1627 | { | |
1628 | if (len < 4) | |
4f0420fd | 1629 | regcache->raw_write_part (areg, offset, len, valbuf); |
ca3bf3bd | 1630 | else |
10eaee5f | 1631 | regcache->raw_write (areg, valbuf); |
ca3bf3bd DJ |
1632 | } |
1633 | } | |
1634 | ||
1635 | ||
bdb4c075 | 1636 | static enum return_value_convention |
ca3bf3bd | 1637 | xtensa_return_value (struct gdbarch *gdbarch, |
6a3a010b | 1638 | struct value *function, |
ca3bf3bd DJ |
1639 | struct type *valtype, |
1640 | struct regcache *regcache, | |
1641 | gdb_byte *readbuf, | |
1642 | const gdb_byte *writebuf) | |
1643 | { | |
bdb4c075 | 1644 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd | 1645 | |
78134374 SM |
1646 | int struct_return = ((valtype->code () == TYPE_CODE_STRUCT |
1647 | || valtype->code () == TYPE_CODE_UNION | |
1648 | || valtype->code () == TYPE_CODE_ARRAY) | |
df86565b | 1649 | && valtype->length () > 16); |
ca3bf3bd DJ |
1650 | |
1651 | if (struct_return) | |
1652 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1653 | ||
1654 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1655 | ||
1656 | if (writebuf != NULL) | |
1657 | { | |
1658 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1659 | } | |
1660 | ||
1661 | if (readbuf != NULL) | |
1662 | { | |
1663 | gdb_assert (!struct_return); | |
1664 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1665 | } | |
1666 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1667 | } | |
1668 | ||
1669 | ||
1670 | /* DUMMY FRAME */ | |
1671 | ||
1672 | static CORE_ADDR | |
1673 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1674 | struct value *function, | |
1675 | struct regcache *regcache, | |
1676 | CORE_ADDR bp_addr, | |
1677 | int nargs, | |
1678 | struct value **args, | |
1679 | CORE_ADDR sp, | |
cf84fa6b | 1680 | function_call_return_method return_method, |
ca3bf3bd DJ |
1681 | CORE_ADDR struct_addr) |
1682 | { | |
e17a4113 | 1683 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 1684 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
ca3bf3bd | 1685 | int size, onstack_size; |
ff7a4c00 | 1686 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1687 | CORE_ADDR ra, ps; |
1688 | struct argument_info | |
1689 | { | |
1690 | const bfd_byte *contents; | |
1691 | int length; | |
1692 | int onstack; /* onstack == 0 => in reg */ | |
1693 | int align; /* alignment */ | |
1694 | union | |
1695 | { | |
581e13c1 MS |
1696 | int offset; /* stack offset if on stack. */ |
1697 | int regno; /* regno if in register. */ | |
ca3bf3bd DJ |
1698 | } u; |
1699 | }; | |
1700 | ||
1701 | struct argument_info *arg_info = | |
1702 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1703 | ||
1704 | CORE_ADDR osp = sp; | |
1705 | ||
1706 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1707 | ||
1708 | if (xtensa_debug_level > 3) | |
1709 | { | |
ca3bf3bd | 1710 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); |
cf84fa6b | 1711 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, " |
ca3bf3bd | 1712 | "struct_addr=0x%x\n", |
cf84fa6b | 1713 | (int) sp, (int) return_method, (int) struct_addr); |
ca3bf3bd | 1714 | |
b926417a | 1715 | for (int i = 0; i < nargs; i++) |
dda83cd7 | 1716 | { |
ca3bf3bd | 1717 | struct value *arg = args[i]; |
d0c97917 | 1718 | struct type *arg_type = check_typedef (arg->type ()); |
6cb06a8c TT |
1719 | gdb_printf (gdb_stdlog, "%2d: %s %3s ", i, |
1720 | host_address_to_string (arg), | |
df86565b | 1721 | pulongest (arg_type->length ())); |
78134374 | 1722 | switch (arg_type->code ()) |
ca3bf3bd DJ |
1723 | { |
1724 | case TYPE_CODE_INT: | |
6cb06a8c | 1725 | gdb_printf (gdb_stdlog, "int"); |
ca3bf3bd DJ |
1726 | break; |
1727 | case TYPE_CODE_STRUCT: | |
6cb06a8c | 1728 | gdb_printf (gdb_stdlog, "struct"); |
ca3bf3bd DJ |
1729 | break; |
1730 | default: | |
6cb06a8c | 1731 | gdb_printf (gdb_stdlog, "%3d", arg_type->code ()); |
ca3bf3bd DJ |
1732 | break; |
1733 | } | |
6cb06a8c | 1734 | gdb_printf (gdb_stdlog, " %s\n", |
efaf1ae0 | 1735 | host_address_to_string (arg->contents ().data ())); |
ca3bf3bd DJ |
1736 | } |
1737 | } | |
1738 | ||
1739 | /* First loop: collect information. | |
1740 | Cast into type_long. (This shouldn't happen often for C because | |
1741 | GDB already does this earlier.) It's possible that GDB could | |
1742 | do it all the time but it's harmless to leave this code here. */ | |
1743 | ||
1744 | size = 0; | |
1745 | onstack_size = 0; | |
ca3bf3bd | 1746 | |
cf84fa6b | 1747 | if (return_method == return_method_struct) |
ca3bf3bd DJ |
1748 | size = REGISTER_SIZE; |
1749 | ||
b926417a | 1750 | for (int i = 0; i < nargs; i++) |
ca3bf3bd DJ |
1751 | { |
1752 | struct argument_info *info = &arg_info[i]; | |
1753 | struct value *arg = args[i]; | |
d0c97917 | 1754 | struct type *arg_type = check_typedef (arg->type ()); |
ca3bf3bd | 1755 | |
78134374 | 1756 | switch (arg_type->code ()) |
ca3bf3bd DJ |
1757 | { |
1758 | case TYPE_CODE_INT: | |
1759 | case TYPE_CODE_BOOL: | |
1760 | case TYPE_CODE_CHAR: | |
1761 | case TYPE_CODE_RANGE: | |
1762 | case TYPE_CODE_ENUM: | |
1763 | ||
1764 | /* Cast argument to long if necessary as the mask does it too. */ | |
df86565b SM |
1765 | if (arg_type->length () |
1766 | < builtin_type (gdbarch)->builtin_long->length ()) | |
ca3bf3bd | 1767 | { |
0dfff4cb | 1768 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1769 | arg = value_cast (arg_type, arg); |
1770 | } | |
bdb4c075 | 1771 | /* Aligment is equal to the type length for the basic types. */ |
df86565b | 1772 | info->align = arg_type->length (); |
ca3bf3bd DJ |
1773 | break; |
1774 | ||
1775 | case TYPE_CODE_FLT: | |
1776 | ||
1777 | /* Align doubles correctly. */ | |
df86565b SM |
1778 | if (arg_type->length () |
1779 | == builtin_type (gdbarch)->builtin_double->length ()) | |
1780 | info->align = builtin_type (gdbarch)->builtin_double->length (); | |
ca3bf3bd | 1781 | else |
df86565b | 1782 | info->align = builtin_type (gdbarch)->builtin_long->length (); |
ca3bf3bd DJ |
1783 | break; |
1784 | ||
1785 | case TYPE_CODE_STRUCT: | |
1786 | default: | |
df86565b | 1787 | info->align = builtin_type (gdbarch)->builtin_long->length (); |
ca3bf3bd DJ |
1788 | break; |
1789 | } | |
df86565b | 1790 | info->length = arg_type->length (); |
efaf1ae0 | 1791 | info->contents = arg->contents ().data (); |
ca3bf3bd DJ |
1792 | |
1793 | /* Align size and onstack_size. */ | |
1794 | size = (size + info->align - 1) & ~(info->align - 1); | |
1795 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1796 | ||
345bd07c | 1797 | if (size + info->length > REGISTER_SIZE * ARG_NOF (tdep)) |
ca3bf3bd DJ |
1798 | { |
1799 | info->onstack = 1; | |
1800 | info->u.offset = onstack_size; | |
1801 | onstack_size += info->length; | |
1802 | } | |
1803 | else | |
1804 | { | |
1805 | info->onstack = 0; | |
345bd07c | 1806 | info->u.regno = ARG_1ST (tdep) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1807 | } |
1808 | size += info->length; | |
1809 | } | |
1810 | ||
1811 | /* Adjust the stack pointer and align it. */ | |
1812 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1813 | ||
bdb4c075 | 1814 | /* Simulate MOVSP, if Windowed ABI. */ |
345bd07c | 1815 | if ((tdep->call_abi != CallAbiCall0Only) |
304fe255 | 1816 | && (sp != osp)) |
ca3bf3bd DJ |
1817 | { |
1818 | read_memory (osp - 16, buf, 16); | |
1819 | write_memory (sp - 16, buf, 16); | |
1820 | } | |
1821 | ||
1822 | /* Second Loop: Load arguments. */ | |
1823 | ||
cf84fa6b | 1824 | if (return_method == return_method_struct) |
ca3bf3bd | 1825 | { |
e17a4113 | 1826 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); |
345bd07c | 1827 | regcache->cooked_write (ARG_1ST (tdep), buf); |
ca3bf3bd DJ |
1828 | } |
1829 | ||
b926417a | 1830 | for (int i = 0; i < nargs; i++) |
ca3bf3bd DJ |
1831 | { |
1832 | struct argument_info *info = &arg_info[i]; | |
1833 | ||
1834 | if (info->onstack) | |
1835 | { | |
1836 | int n = info->length; | |
1837 | CORE_ADDR offset = sp + info->u.offset; | |
1838 | ||
1839 | /* Odd-sized structs are aligned to the lower side of a memory | |
1840 | word in big-endian mode and require a shift. This only | |
1841 | applies for structures smaller than one word. */ | |
1842 | ||
4c6b5505 | 1843 | if (n < REGISTER_SIZE |
6b50c0b0 | 1844 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1845 | offset += (REGISTER_SIZE - n); |
1846 | ||
1847 | write_memory (offset, info->contents, info->length); | |
1848 | ||
1849 | } | |
1850 | else | |
1851 | { | |
1852 | int n = info->length; | |
1853 | const bfd_byte *cp = info->contents; | |
1854 | int r = info->u.regno; | |
1855 | ||
1856 | /* Odd-sized structs are aligned to the lower side of registers in | |
1857 | big-endian mode and require a shift. The odd-sized leftover will | |
1858 | be at the end. Note that this is only true for structures smaller | |
1859 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1860 | will be left-aligned in the register on both endiannesses. */ | |
1861 | ||
e17a4113 | 1862 | if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) |
ca3bf3bd | 1863 | { |
e17a4113 UW |
1864 | ULONGEST v; |
1865 | v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); | |
ca3bf3bd DJ |
1866 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
1867 | ||
e17a4113 | 1868 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); |
b66f5587 | 1869 | regcache->cooked_write (r, buf); |
ca3bf3bd DJ |
1870 | |
1871 | cp += REGISTER_SIZE; | |
1872 | n -= REGISTER_SIZE; | |
1873 | r++; | |
1874 | } | |
1875 | else | |
1876 | while (n > 0) | |
1877 | { | |
b66f5587 | 1878 | regcache->cooked_write (r, cp); |
ca3bf3bd | 1879 | |
ca3bf3bd DJ |
1880 | cp += REGISTER_SIZE; |
1881 | n -= REGISTER_SIZE; | |
1882 | r++; | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
ca3bf3bd | 1887 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1888 | The return address for the current function (in A0) is |
85102364 | 1889 | saved in the dummy frame, so we can safely overwrite A0 here. */ |
ca3bf3bd | 1890 | |
345bd07c | 1891 | if (tdep->call_abi != CallAbiCall0Only) |
bdb4c075 | 1892 | { |
98689b25 | 1893 | ULONGEST val; |
68d6df83 | 1894 | |
bdb4c075 | 1895 | ra = (bp_addr & 0x3fffffff) | 0x40000000; |
98689b25 MG |
1896 | regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val); |
1897 | ps = (unsigned long) val & ~0x00030000; | |
304fe255 | 1898 | regcache_cooked_write_unsigned |
345bd07c | 1899 | (regcache, tdep->a0_base + 4, ra); |
bdb4c075 | 1900 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1901 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1902 | ps | 0x00010000); |
94a0e877 MG |
1903 | |
1904 | /* All the registers have been saved. After executing | |
1905 | dummy call, they all will be restored. So it's safe | |
1906 | to modify WINDOWSTART register to make it look like there | |
1907 | is only one register window corresponding to WINDOWEBASE. */ | |
1908 | ||
345bd07c | 1909 | regcache->raw_read (tdep->wb_regnum, buf); |
e17a4113 | 1910 | regcache_cooked_write_unsigned |
345bd07c | 1911 | (regcache, tdep->ws_regnum, |
e17a4113 | 1912 | 1 << extract_unsigned_integer (buf, 4, byte_order)); |
bdb4c075 MG |
1913 | } |
1914 | else | |
1915 | { | |
1916 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1917 | regcache_cooked_write_unsigned |
345bd07c | 1918 | (regcache, tdep->a0_base, bp_addr); |
bdb4c075 | 1919 | } |
ca3bf3bd DJ |
1920 | |
1921 | /* Set new stack pointer and return it. */ | |
304fe255 | 1922 | regcache_cooked_write_unsigned (regcache, |
345bd07c | 1923 | tdep->a0_base + 1, sp); |
ca3bf3bd DJ |
1924 | /* Make dummy frame ID unique by adding a constant. */ |
1925 | return sp + SP_ALIGNMENT; | |
1926 | } | |
1927 | ||
cd6c3b4f YQ |
1928 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1929 | ||
d19280ad YQ |
1930 | static int |
1931 | xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1932 | { | |
08106042 | 1933 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c SM |
1934 | |
1935 | if (tdep->isa_use_density_instructions) | |
d19280ad YQ |
1936 | return 2; |
1937 | else | |
1938 | return 4; | |
1939 | } | |
ca3bf3bd DJ |
1940 | |
1941 | /* Return a breakpoint for the current location of PC. We always use | |
1942 | the density version if we have density instructions (regardless of the | |
1943 | current instruction at PC), and use regular instructions otherwise. */ | |
1944 | ||
1945 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1946 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1947 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1948 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1949 | ||
cd6c3b4f YQ |
1950 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1951 | ||
d19280ad YQ |
1952 | static const gdb_byte * |
1953 | xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
ca3bf3bd | 1954 | { |
d19280ad | 1955 | *size = kind; |
ca3bf3bd | 1956 | |
d19280ad | 1957 | if (kind == 4) |
ca3bf3bd | 1958 | { |
d19280ad YQ |
1959 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1960 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1961 | ||
67d57894 | 1962 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1963 | return big_breakpoint; |
ca3bf3bd | 1964 | else |
d19280ad | 1965 | return little_breakpoint; |
ca3bf3bd DJ |
1966 | } |
1967 | else | |
1968 | { | |
d19280ad YQ |
1969 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; |
1970 | static unsigned char density_little_breakpoint[] | |
1971 | = DENSITY_LITTLE_BREAKPOINT; | |
1972 | ||
67d57894 | 1973 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1974 | return density_big_breakpoint; |
ca3bf3bd | 1975 | else |
d19280ad | 1976 | return density_little_breakpoint; |
ca3bf3bd DJ |
1977 | } |
1978 | } | |
1979 | ||
bdb4c075 MG |
1980 | /* Call0 ABI support routines. */ |
1981 | ||
f976a05d MG |
1982 | /* Return true, if PC points to "ret" or "ret.n". */ |
1983 | ||
1984 | static int | |
1985 | call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc) | |
1986 | { | |
1987 | #define RETURN_RET goto done | |
1988 | xtensa_isa isa; | |
1989 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1990 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
f976a05d MG |
1991 | CORE_ADDR ia, bt, ba; |
1992 | xtensa_format ifmt; | |
1993 | int ilen, islots, is; | |
1994 | xtensa_opcode opc; | |
1995 | const char *opcname; | |
1996 | int found_ret = 0; | |
1997 | ||
1998 | isa = xtensa_default_isa; | |
1999 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2000 | ins = xtensa_insnbuf_alloc (isa); | |
2001 | slot = xtensa_insnbuf_alloc (isa); | |
2002 | ba = 0; | |
2003 | ||
2004 | for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen) | |
2005 | { | |
2006 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2007 | { |
f976a05d MG |
2008 | ba = ia; |
2009 | bt = (ba + XTENSA_ISA_BSZ) < finish_pc | |
2010 | ? ba + XTENSA_ISA_BSZ : finish_pc; | |
2011 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) | |
2012 | RETURN_RET; | |
2013 | } | |
2014 | ||
2015 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2016 | ifmt = xtensa_format_decode (isa, ins); | |
2017 | if (ifmt == XTENSA_UNDEFINED) | |
2018 | RETURN_RET; | |
2019 | ilen = xtensa_format_length (isa, ifmt); | |
2020 | if (ilen == XTENSA_UNDEFINED) | |
2021 | RETURN_RET; | |
2022 | islots = xtensa_format_num_slots (isa, ifmt); | |
2023 | if (islots == XTENSA_UNDEFINED) | |
2024 | RETURN_RET; | |
2025 | ||
2026 | for (is = 0; is < islots; ++is) | |
2027 | { | |
2028 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2029 | RETURN_RET; | |
2030 | ||
2031 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2032 | if (opc == XTENSA_UNDEFINED) | |
2033 | RETURN_RET; | |
2034 | ||
2035 | opcname = xtensa_opcode_name (isa, opc); | |
2036 | ||
2037 | if ((strcasecmp (opcname, "ret.n") == 0) | |
2038 | || (strcasecmp (opcname, "ret") == 0)) | |
2039 | { | |
2040 | found_ret = 1; | |
2041 | RETURN_RET; | |
2042 | } | |
2043 | } | |
2044 | } | |
2045 | done: | |
2046 | xtensa_insnbuf_free(isa, slot); | |
2047 | xtensa_insnbuf_free(isa, ins); | |
2048 | return found_ret; | |
2049 | } | |
2050 | ||
bdb4c075 MG |
2051 | /* Call0 opcode class. Opcodes are preclassified according to what they |
2052 | mean for Call0 prologue analysis, and their number of significant operands. | |
2053 | The purpose of this is to simplify prologue analysis by separating | |
2054 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
2055 | ||
0d1703b8 | 2056 | enum xtensa_insn_kind |
68d6df83 | 2057 | { |
bdb4c075 MG |
2058 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ |
2059 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
2060 | c0opc_flow, /* Flow control insn. */ | |
2061 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
2062 | c0opc_break, /* Debugger software breakpoints. */ | |
2063 | c0opc_add, /* Adding two registers. */ | |
2064 | c0opc_addi, /* Adding a register and an immediate. */ | |
dbab50de | 2065 | c0opc_and, /* Bitwise "and"-ing two registers. */ |
bdb4c075 MG |
2066 | c0opc_sub, /* Subtracting a register from a register. */ |
2067 | c0opc_mov, /* Moving a register to a register. */ | |
2068 | c0opc_movi, /* Moving an immediate to a register. */ | |
2069 | c0opc_l32r, /* Loading a literal. */ | |
08b9c608 MG |
2070 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ |
2071 | c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */ | |
2072 | c0opc_l32e, /* L32E instruction. */ | |
2073 | c0opc_s32e, /* S32E instruction. */ | |
2074 | c0opc_rfwo, /* RFWO instruction. */ | |
2075 | c0opc_rfwu, /* RFWU instruction. */ | |
bdb4c075 | 2076 | c0opc_NrOf /* Number of opcode classifications. */ |
0d1703b8 | 2077 | }; |
bdb4c075 | 2078 | |
08b9c608 MG |
2079 | /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */ |
2080 | ||
2081 | static int | |
2082 | rwx_special_register (const char *opcname) | |
2083 | { | |
2084 | char ch = *opcname++; | |
2085 | ||
2086 | if ((ch != 'r') && (ch != 'w') && (ch != 'x')) | |
2087 | return 0; | |
2088 | if (*opcname++ != 's') | |
2089 | return 0; | |
2090 | if (*opcname++ != 'r') | |
2091 | return 0; | |
2092 | if (*opcname++ != '.') | |
2093 | return 0; | |
2094 | ||
2095 | return 1; | |
2096 | } | |
bdb4c075 MG |
2097 | |
2098 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
2099 | ||
2100 | static xtensa_insn_kind | |
2101 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
2102 | { | |
2103 | const char *opcname; | |
2104 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
2105 | ||
2106 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
2107 | ||
2108 | /* Get opcode name and handle special classifications. */ | |
2109 | ||
2110 | opcname = xtensa_opcode_name (isa, opc); | |
2111 | ||
2112 | if (opcname == NULL | |
2113 | || strcasecmp (opcname, "ill") == 0 | |
2114 | || strcasecmp (opcname, "ill.n") == 0) | |
2115 | opclass = c0opc_illegal; | |
2116 | else if (strcasecmp (opcname, "break") == 0 | |
2117 | || strcasecmp (opcname, "break.n") == 0) | |
2118 | opclass = c0opc_break; | |
2119 | else if (strcasecmp (opcname, "entry") == 0) | |
2120 | opclass = c0opc_entry; | |
08b9c608 MG |
2121 | else if (strcasecmp (opcname, "rfwo") == 0) |
2122 | opclass = c0opc_rfwo; | |
2123 | else if (strcasecmp (opcname, "rfwu") == 0) | |
2124 | opclass = c0opc_rfwu; | |
bdb4c075 MG |
2125 | else if (xtensa_opcode_is_branch (isa, opc) > 0 |
2126 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
2127 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
2128 | || xtensa_opcode_is_call (isa, opc) > 0 | |
2129 | || strcasecmp (opcname, "simcall") == 0 | |
2130 | || strcasecmp (opcname, "syscall") == 0) | |
2131 | opclass = c0opc_flow; | |
2132 | ||
2133 | /* Also, classify specific opcodes that need to be tracked. */ | |
2134 | else if (strcasecmp (opcname, "add") == 0 | |
2135 | || strcasecmp (opcname, "add.n") == 0) | |
2136 | opclass = c0opc_add; | |
dbab50de MG |
2137 | else if (strcasecmp (opcname, "and") == 0) |
2138 | opclass = c0opc_and; | |
bdb4c075 MG |
2139 | else if (strcasecmp (opcname, "addi") == 0 |
2140 | || strcasecmp (opcname, "addi.n") == 0 | |
2141 | || strcasecmp (opcname, "addmi") == 0) | |
2142 | opclass = c0opc_addi; | |
2143 | else if (strcasecmp (opcname, "sub") == 0) | |
2144 | opclass = c0opc_sub; | |
2145 | else if (strcasecmp (opcname, "mov.n") == 0 | |
2146 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
2147 | opclass = c0opc_mov; | |
2148 | else if (strcasecmp (opcname, "movi") == 0 | |
2149 | || strcasecmp (opcname, "movi.n") == 0) | |
2150 | opclass = c0opc_movi; | |
2151 | else if (strcasecmp (opcname, "l32r") == 0) | |
2152 | opclass = c0opc_l32r; | |
2153 | else if (strcasecmp (opcname, "s32i") == 0 | |
2154 | || strcasecmp (opcname, "s32i.n") == 0) | |
2155 | opclass = c0opc_s32i; | |
08b9c608 MG |
2156 | else if (strcasecmp (opcname, "l32e") == 0) |
2157 | opclass = c0opc_l32e; | |
2158 | else if (strcasecmp (opcname, "s32e") == 0) | |
2159 | opclass = c0opc_s32e; | |
2160 | else if (rwx_special_register (opcname)) | |
2161 | opclass = c0opc_rwxsr; | |
bdb4c075 MG |
2162 | |
2163 | return opclass; | |
2164 | } | |
2165 | ||
2166 | /* Tracks register movement/mutation for a given operation, which may | |
2167 | be within a bundle. Updates the destination register tracking info | |
2168 | accordingly. The pc is needed only for pc-relative load instructions | |
2169 | (eg. l32r). The SP register number is needed to identify stores to | |
85102364 | 2170 | the stack frame. Returns 0, if analysis was successful, non-zero |
dbab50de | 2171 | otherwise. */ |
bdb4c075 | 2172 | |
dbab50de MG |
2173 | static int |
2174 | call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
bdb4c075 | 2175 | xtensa_insn_kind opclass, int nods, unsigned odv[], |
dbab50de | 2176 | CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache) |
bdb4c075 | 2177 | { |
e17a4113 | 2178 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
dbab50de | 2179 | unsigned litbase, litaddr, litval; |
08106042 | 2180 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
bdb4c075 MG |
2181 | |
2182 | switch (opclass) | |
2183 | { | |
2184 | case c0opc_addi: | |
2185 | /* 3 operands: dst, src, imm. */ | |
2186 | gdb_assert (nods == 3); | |
2187 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2188 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
2189 | break; | |
2190 | case c0opc_add: | |
2191 | /* 3 operands: dst, src1, src2. */ | |
08b9c608 | 2192 | gdb_assert (nods == 3); |
bdb4c075 | 2193 | if (src[odv[1]].fr_reg == C0_CONST) |
dda83cd7 | 2194 | { |
bdb4c075 MG |
2195 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; |
2196 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2197 | } | |
2198 | else if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2199 | { |
bdb4c075 MG |
2200 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2201 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2202 | } | |
2203 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2204 | break; | |
dbab50de MG |
2205 | case c0opc_and: |
2206 | /* 3 operands: dst, src1, src2. */ | |
2207 | gdb_assert (nods == 3); | |
2208 | if (cache->c0.c0_fpalign == 0) | |
2209 | { | |
2210 | /* Handle dynamic stack alignment. */ | |
2211 | if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg)) | |
2212 | { | |
2213 | if (src[odv[2]].fr_reg == C0_CONST) | |
2214 | cache->c0.c0_fpalign = src[odv[2]].fr_ofs; | |
2215 | break; | |
2216 | } | |
2217 | else if ((src[odv[0]].fr_reg == spreg) | |
2218 | && (src[odv[2]].fr_reg == spreg)) | |
2219 | { | |
2220 | if (src[odv[1]].fr_reg == C0_CONST) | |
2221 | cache->c0.c0_fpalign = src[odv[1]].fr_ofs; | |
2222 | break; | |
2223 | } | |
2224 | /* else fall through. */ | |
2225 | } | |
2226 | if (src[odv[1]].fr_reg == C0_CONST) | |
dda83cd7 | 2227 | { |
dbab50de MG |
2228 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; |
2229 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs; | |
2230 | } | |
2231 | else if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2232 | { |
dbab50de MG |
2233 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2234 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs; | |
2235 | } | |
2236 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2237 | break; | |
bdb4c075 MG |
2238 | case c0opc_sub: |
2239 | /* 3 operands: dst, src1, src2. */ | |
2240 | gdb_assert (nods == 3); | |
2241 | if (src[odv[2]].fr_reg == C0_CONST) | |
dda83cd7 | 2242 | { |
bdb4c075 MG |
2243 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2244 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2245 | } | |
2246 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2247 | break; | |
2248 | case c0opc_mov: | |
2249 | /* 2 operands: dst, src [, src]. */ | |
2250 | gdb_assert (nods == 2); | |
dbab50de MG |
2251 | /* First, check if it's a special case of saving unaligned SP |
2252 | to a spare register in case of dynamic stack adjustment. | |
2253 | But, only do it one time. The second time could be initializing | |
2254 | frame pointer. We don't want to overwrite the first one. */ | |
2255 | if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP)) | |
2256 | cache->c0.c0_old_sp = odv[0]; | |
2257 | ||
bdb4c075 MG |
2258 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2259 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2260 | break; | |
2261 | case c0opc_movi: | |
2262 | /* 2 operands: dst, imm. */ | |
2263 | gdb_assert (nods == 2); | |
2264 | dst[odv[0]].fr_reg = C0_CONST; | |
2265 | dst[odv[0]].fr_ofs = odv[1]; | |
2266 | break; | |
2267 | case c0opc_l32r: | |
2268 | /* 2 operands: dst, literal offset. */ | |
2269 | gdb_assert (nods == 2); | |
dbab50de | 2270 | /* litbase = xtensa_get_litbase (pc); can be also used. */ |
345bd07c | 2271 | litbase = (tdep->litbase_regnum == -1) |
dbab50de | 2272 | ? 0 : xtensa_read_register |
345bd07c | 2273 | (tdep->litbase_regnum); |
bdb4c075 MG |
2274 | litaddr = litbase & 1 |
2275 | ? (litbase & ~1) + (signed)odv[1] | |
2276 | : (pc + 3 + (signed)odv[1]) & ~3; | |
e17a4113 | 2277 | litval = read_memory_integer (litaddr, 4, byte_order); |
bdb4c075 MG |
2278 | dst[odv[0]].fr_reg = C0_CONST; |
2279 | dst[odv[0]].fr_ofs = litval; | |
2280 | break; | |
2281 | case c0opc_s32i: | |
2282 | /* 3 operands: value, base, offset. */ | |
2283 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
dbab50de MG |
2284 | /* First, check if it's a spill for saved unaligned SP, |
2285 | when dynamic stack adjustment was applied to this frame. */ | |
2286 | if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */ | |
2287 | && (odv[1] == spreg) /* SP usage indicates spill. */ | |
2288 | && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */ | |
2289 | cache->c0.c0_sp_ofs = odv[2]; | |
2290 | ||
bdb4c075 MG |
2291 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ |
2292 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2293 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2294 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2295 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
dda83cd7 | 2296 | { |
bdb4c075 MG |
2297 | /* ISA encoding guarantees alignment. But, check it anyway. */ |
2298 | gdb_assert ((odv[2] & 3) == 0); | |
2299 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2300 | } | |
2301 | break; | |
dbab50de MG |
2302 | /* If we end up inside Window Overflow / Underflow interrupt handler |
2303 | report an error because these handlers should have been handled | |
2304 | already in a different way. */ | |
2305 | case c0opc_l32e: | |
2306 | case c0opc_s32e: | |
2307 | case c0opc_rfwo: | |
2308 | case c0opc_rfwu: | |
2309 | return 1; | |
bdb4c075 | 2310 | default: |
dbab50de | 2311 | return 1; |
bdb4c075 | 2312 | } |
dbab50de | 2313 | return 0; |
bdb4c075 MG |
2314 | } |
2315 | ||
dbab50de | 2316 | /* Analyze prologue of the function at start address to determine if it uses |
bdb4c075 | 2317 | the Call0 ABI, and if so track register moves and linear modifications |
dbab50de MG |
2318 | in the prologue up to the PC or just beyond the prologue, whichever is |
2319 | first. An 'entry' instruction indicates non-Call0 ABI and the end of the | |
2320 | prologue. The prologue may overlap non-prologue instructions but is | |
2321 | guaranteed to end by the first flow-control instruction (jump, branch, | |
2322 | call or return). Since an optimized function may move information around | |
2323 | and change the stack frame arbitrarily during the prologue, the information | |
2324 | is guaranteed valid only at the point in the function indicated by the PC. | |
bdb4c075 MG |
2325 | May be used to skip the prologue or identify the ABI, w/o tracking. |
2326 | ||
2327 | Returns: Address of first instruction after prologue, or PC (whichever | |
2328 | is first), or 0, if decoding failed (in libisa). | |
2329 | Input args: | |
2330 | start Start address of function/prologue. | |
2331 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2332 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2333 | the scan to the end of the function if that can be determined. | |
dbab50de | 2334 | nregs Number of general registers to track. |
bdb4c075 | 2335 | InOut args: |
dbab50de | 2336 | cache Xtensa frame cache. |
bdb4c075 MG |
2337 | |
2338 | Note that these may produce useful results even if decoding fails | |
2339 | because they begin with default assumptions that analysis may change. */ | |
2340 | ||
2341 | static CORE_ADDR | |
e17a4113 | 2342 | call0_analyze_prologue (struct gdbarch *gdbarch, |
dbab50de MG |
2343 | CORE_ADDR start, CORE_ADDR pc, |
2344 | int nregs, xtensa_frame_cache_t *cache) | |
bdb4c075 MG |
2345 | { |
2346 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2347 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2348 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
948f8e3d | 2349 | gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2350 | xtensa_isa isa; /* libisa ISA handle. */ |
2351 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2352 | xtensa_format ifmt; /* libisa instruction format. */ | |
2353 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2354 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2355 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2356 | int nods; /* Opcode number of operands. */ | |
2357 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2358 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2359 | int j; /* General loop counter. */ | |
2360 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2361 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2362 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2363 | ||
2364 | struct symtab_and_line prologue_sal; | |
2365 | ||
2366 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2367 | (int)start, (int)pc); | |
2368 | ||
2369 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2370 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2371 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2372 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
26c4b26f | 2373 | Initialize the Call0 frame and register tracking info. |
bdb4c075 MG |
2374 | Assume it's Call0 until an 'entry' instruction is encountered. |
2375 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2376 | ||
2377 | rtmp = NULL; | |
8179e739 | 2378 | body_pc = UINT_MAX; |
bdb4c075 MG |
2379 | end_pc = 0; |
2380 | ||
2381 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2382 | prologue_sal = find_pc_line (start, 0); | |
2383 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2384 | body_pc = prologue_sal.end; | |
2385 | ||
2386 | /* If we are going to analyze the prologue in general without knowing about | |
85102364 | 2387 | the current PC, make the best assumption for the end of the prologue. */ |
bdb4c075 MG |
2388 | if (pc == 0) |
2389 | { | |
2390 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
325fac50 | 2391 | body_pc = std::min (end_pc, body_pc); |
bdb4c075 MG |
2392 | } |
2393 | else | |
325fac50 | 2394 | body_pc = std::min (pc, body_pc); |
bdb4c075 | 2395 | |
dbab50de MG |
2396 | cache->call0 = 1; |
2397 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
bdb4c075 MG |
2398 | |
2399 | isa = xtensa_default_isa; | |
2ff5e605 | 2400 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2401 | ins = xtensa_insnbuf_alloc (isa); |
2402 | slot = xtensa_insnbuf_alloc (isa); | |
2403 | ||
2404 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2405 | { | |
2406 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
dda83cd7 | 2407 | read memory beyond PC to be sure we stay within text section |
bdb4c075 MG |
2408 | (this protection only works if a non-zero pc is supplied). */ |
2409 | ||
2410 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2411 | { |
bdb4c075 | 2412 | ba = ia; |
2ff5e605 | 2413 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
dbab50de MG |
2414 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) |
2415 | error (_("Unable to read target memory ...")); | |
bdb4c075 MG |
2416 | } |
2417 | ||
2418 | /* Decode format information. */ | |
2419 | ||
2420 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2421 | ifmt = xtensa_format_decode (isa, ins); | |
2422 | if (ifmt == XTENSA_UNDEFINED) | |
2423 | { | |
2424 | fail = 1; | |
2425 | goto done; | |
2426 | } | |
2427 | ilen = xtensa_format_length (isa, ifmt); | |
2428 | if (ilen == XTENSA_UNDEFINED) | |
2429 | { | |
2430 | fail = 1; | |
2431 | goto done; | |
2432 | } | |
2433 | islots = xtensa_format_num_slots (isa, ifmt); | |
2434 | if (islots == XTENSA_UNDEFINED) | |
2435 | { | |
2436 | fail = 1; | |
2437 | goto done; | |
2438 | } | |
2439 | ||
2440 | /* Analyze a bundle or a single instruction, using a snapshot of | |
dda83cd7 | 2441 | the register tracking info as input for the entire bundle so that |
bdb4c075 | 2442 | register changes do not take effect within this bundle. */ |
ca3bf3bd | 2443 | |
bdb4c075 | 2444 | for (j = 0; j < nregs; ++j) |
dbab50de | 2445 | rtmp[j] = cache->c0.c0_rt[j]; |
bdb4c075 MG |
2446 | |
2447 | for (is = 0; is < islots; ++is) | |
dda83cd7 | 2448 | { |
bdb4c075 MG |
2449 | /* Decode a slot and classify the opcode. */ |
2450 | ||
2451 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2452 | if (fail) | |
2453 | goto done; | |
2454 | ||
2455 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
dbab50de | 2456 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", |
bdb4c075 MG |
2457 | (unsigned)ia, opc); |
2458 | if (opc == XTENSA_UNDEFINED) | |
2459 | opclass = c0opc_illegal; | |
2460 | else | |
2461 | opclass = call0_classify_opcode (isa, opc); | |
2462 | ||
2463 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2464 | ||
2465 | switch (opclass) | |
2466 | { | |
2467 | case c0opc_illegal: | |
2468 | case c0opc_break: | |
2469 | fail = 1; | |
2470 | goto done; | |
2471 | ||
2472 | case c0opc_uninteresting: | |
2473 | continue; | |
2474 | ||
dbab50de MG |
2475 | case c0opc_flow: /* Flow control instructions stop analysis. */ |
2476 | case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */ | |
bdb4c075 MG |
2477 | goto done; |
2478 | ||
2479 | case c0opc_entry: | |
dbab50de | 2480 | cache->call0 = 0; |
bdb4c075 MG |
2481 | ia += ilen; /* Skip over 'entry' insn. */ |
2482 | goto done; | |
2483 | ||
2484 | default: | |
dbab50de | 2485 | cache->call0 = 1; |
bdb4c075 MG |
2486 | } |
2487 | ||
2488 | /* Only expected opcodes should get this far. */ | |
bdb4c075 MG |
2489 | |
2490 | /* Extract and decode the operands. */ | |
2491 | nods = xtensa_opcode_num_operands (isa, opc); | |
2492 | if (nods == XTENSA_UNDEFINED) | |
2493 | { | |
2494 | fail = 1; | |
2495 | goto done; | |
2496 | } | |
2497 | ||
2498 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2499 | { | |
2500 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2501 | is, slot, &odv[j]); | |
2502 | if (fail) | |
2503 | goto done; | |
2504 | ||
2505 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2506 | if (fail) | |
2507 | goto done; | |
2508 | } | |
2509 | ||
2510 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2511 | if (opclass == c0opc_mov && nods == 3) | |
2512 | { | |
2513 | if (odv[2] == odv[1]) | |
dbab50de MG |
2514 | { |
2515 | nods = 2; | |
2516 | if ((odv[0] == 1) && (odv[1] != 1)) | |
2517 | /* OR A1, An, An , where n != 1. | |
2518 | This means we are inside epilogue already. */ | |
2519 | goto done; | |
2520 | } | |
bdb4c075 MG |
2521 | else |
2522 | { | |
2523 | opclass = c0opc_uninteresting; | |
2524 | continue; | |
2525 | } | |
2526 | } | |
2527 | ||
2528 | /* Track register movement and modification for this operation. */ | |
dbab50de MG |
2529 | fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp, |
2530 | opclass, nods, odv, ia, 1, cache); | |
2531 | if (fail) | |
2532 | goto done; | |
bdb4c075 MG |
2533 | } |
2534 | } | |
2535 | done: | |
2536 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2537 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2538 | xtensa_insnbuf_free(isa, slot); | |
2539 | xtensa_insnbuf_free(isa, ins); | |
d4709618 | 2540 | return fail ? XTENSA_ISA_BADPC : ia; |
bdb4c075 MG |
2541 | } |
2542 | ||
5142f611 | 2543 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2544 | |
2545 | static void | |
bd2b40ac | 2546 | call0_frame_cache (frame_info_ptr this_frame, |
dbab50de | 2547 | xtensa_frame_cache_t *cache, CORE_ADDR pc) |
bdb4c075 | 2548 | { |
5142f611 | 2549 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2550 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 MG |
2551 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2552 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2553 | CORE_ADDR sp, fp, ra; | |
dbab50de | 2554 | int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk; |
08106042 | 2555 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
bdb4c075 | 2556 | |
dbab50de | 2557 | sp = get_frame_register_unsigned |
345bd07c | 2558 | (this_frame, tdep->a0_base + 1); |
dbab50de MG |
2559 | fp = sp; /* Assume FP == SP until proven otherwise. */ |
2560 | ||
bdb4c075 MG |
2561 | /* Find the beginning of the prologue of the function containing the PC |
2562 | and analyze it up to the PC or the end of the prologue. */ | |
2563 | ||
2564 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2565 | { | |
dbab50de | 2566 | body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache); |
d4709618 MG |
2567 | |
2568 | if (body_pc == XTENSA_ISA_BADPC) | |
dbab50de MG |
2569 | { |
2570 | warning_once (); | |
2571 | ra = 0; | |
2572 | goto finish_frame_analysis; | |
2573 | } | |
bdb4c075 MG |
2574 | } |
2575 | ||
bdb4c075 MG |
2576 | /* Get the frame information and FP (if used) at the current PC. |
2577 | If PC is in the prologue, the prologue analysis is more reliable | |
dbab50de MG |
2578 | than DWARF info. We don't not know for sure, if PC is in the prologue, |
2579 | but we do know no calls have yet taken place, so we can almost | |
bdb4c075 MG |
2580 | certainly rely on the prologue analysis. */ |
2581 | ||
2582 | if (body_pc <= pc) | |
2583 | { | |
2584 | /* Prologue analysis was successful up to the PC. | |
dda83cd7 | 2585 | It includes the cases when PC == START_PC. */ |
bdb4c075 MG |
2586 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; |
2587 | /* c0_hasfp == true means there is a frame pointer because | |
2588 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2589 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2590 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2591 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
345bd07c | 2592 | fp_regnum += tdep->a0_base; |
bdb4c075 MG |
2593 | } |
2594 | else /* No data from the prologue analysis. */ | |
2595 | { | |
2596 | c0_hasfp = 0; | |
345bd07c | 2597 | fp_regnum = tdep->a0_base + C0_SP; |
bdb4c075 MG |
2598 | c0_frmsz = 0; |
2599 | start_pc = pc; | |
2600 | } | |
2601 | ||
dbab50de MG |
2602 | if (cache->c0.c0_fpalign) |
2603 | { | |
2604 | /* This frame has a special prologue with a dynamic stack adjustment | |
2605 | to force an alignment, which is bigger than standard 16 bytes. */ | |
2606 | ||
2607 | CORE_ADDR unaligned_sp; | |
2608 | ||
2609 | if (cache->c0.c0_old_sp == C0_INEXP) | |
2610 | /* This can't be. Prologue code should be consistent. | |
2611 | Unaligned stack pointer should be saved in a spare register. */ | |
2612 | { | |
2613 | warning_once (); | |
2614 | ra = 0; | |
2615 | goto finish_frame_analysis; | |
2616 | } | |
2617 | ||
2618 | if (cache->c0.c0_sp_ofs == C0_NOSTK) | |
2619 | /* Saved unaligned value of SP is kept in a register. */ | |
2620 | unaligned_sp = get_frame_register_unsigned | |
345bd07c | 2621 | (this_frame, tdep->a0_base + cache->c0.c0_old_sp); |
dbab50de MG |
2622 | else |
2623 | /* Get the value from stack. */ | |
2624 | unaligned_sp = (CORE_ADDR) | |
2625 | read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order); | |
2626 | ||
2627 | prev_sp = unaligned_sp + c0_frmsz; | |
2628 | } | |
2629 | else | |
2630 | prev_sp = fp + c0_frmsz; | |
bdb4c075 MG |
2631 | |
2632 | /* Frame size from debug info or prologue tracking does not account for | |
2633 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2634 | if (c0_hasfp) | |
2635 | { | |
5142f611 | 2636 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 | 2637 | |
bdb4c075 MG |
2638 | /* Update the stack frame size. */ |
2639 | c0_frmsz += fp - sp; | |
2640 | } | |
2641 | ||
2642 | /* Get the return address (RA) from the stack if saved, | |
2643 | or try to get it from a register. */ | |
2644 | ||
2645 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2646 | if (to_stk != C0_NOSTK) | |
2647 | ra = (CORE_ADDR) | |
e17a4113 UW |
2648 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, |
2649 | 4, byte_order); | |
bdb4c075 MG |
2650 | |
2651 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2652 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2653 | { | |
dbab50de MG |
2654 | /* Special case for terminating backtrace at a function that wants to |
2655 | be seen as the outermost one. Such a function will clear it's RA (A0) | |
2656 | register to 0 in the prologue instead of saving its original value. */ | |
bdb4c075 MG |
2657 | ra = 0; |
2658 | } | |
2659 | else | |
2660 | { | |
dbab50de MG |
2661 | /* RA was copied to another register or (before any function call) may |
2662 | still be in the original RA register. This is not always reliable: | |
2663 | even in a leaf function, register tracking stops after prologue, and | |
2664 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2665 | RA or any register it was copied to. If likely in prologue or before | |
2666 | any call, use retracking info and hope for the best (compiler should | |
2667 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2668 | too bad. */ | |
bdb4c075 MG |
2669 | |
2670 | int i; | |
1448a0a2 PM |
2671 | for (i = 0; |
2672 | (i < C0_NREGS) | |
2673 | && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
bdb4c075 MG |
2674 | ++i); |
2675 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2676 | i = C0_RA; | |
5142f611 | 2677 | if (i < C0_NREGS) |
bdb4c075 | 2678 | { |
5142f611 MG |
2679 | ra = get_frame_register_unsigned |
2680 | (this_frame, | |
345bd07c | 2681 | tdep->a0_base + cache->c0.c0_rt[i].fr_reg); |
bdb4c075 MG |
2682 | } |
2683 | else ra = 0; | |
2684 | } | |
2685 | ||
dbab50de | 2686 | finish_frame_analysis: |
bdb4c075 MG |
2687 | cache->pc = start_pc; |
2688 | cache->ra = ra; | |
2689 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2690 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2691 | cache->c0.fp_regnum = fp_regnum; | |
2692 | cache->c0.c0_frmsz = c0_frmsz; | |
2693 | cache->c0.c0_hasfp = c0_hasfp; | |
2694 | cache->c0.c0_fp = fp; | |
2695 | } | |
2696 | ||
08b9c608 MG |
2697 | static CORE_ADDR a0_saved; |
2698 | static CORE_ADDR a7_saved; | |
2699 | static CORE_ADDR a11_saved; | |
2700 | static int a0_was_saved; | |
2701 | static int a7_was_saved; | |
2702 | static int a11_was_saved; | |
2703 | ||
68d6df83 | 2704 | /* Simulate L32E instruction: AT <-- ref (AS + offset). */ |
08b9c608 MG |
2705 | static void |
2706 | execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2707 | { | |
08106042 | 2708 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c SM |
2709 | int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb); |
2710 | int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb); | |
08b9c608 MG |
2711 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; |
2712 | unsigned int spilled_value | |
2713 | = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch)); | |
2714 | ||
2715 | if ((at == 0) && !a0_was_saved) | |
2716 | { | |
2717 | a0_saved = xtensa_read_register (atreg); | |
2718 | a0_was_saved = 1; | |
2719 | } | |
2720 | else if ((at == 7) && !a7_was_saved) | |
2721 | { | |
2722 | a7_saved = xtensa_read_register (atreg); | |
2723 | a7_was_saved = 1; | |
2724 | } | |
2725 | else if ((at == 11) && !a11_was_saved) | |
2726 | { | |
2727 | a11_saved = xtensa_read_register (atreg); | |
2728 | a11_was_saved = 1; | |
2729 | } | |
2730 | ||
2731 | xtensa_write_register (atreg, spilled_value); | |
2732 | } | |
2733 | ||
68d6df83 | 2734 | /* Simulate S32E instruction: AT --> ref (AS + offset). */ |
08b9c608 MG |
2735 | static void |
2736 | execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2737 | { | |
08106042 | 2738 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c SM |
2739 | int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb); |
2740 | int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb); | |
08b9c608 MG |
2741 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; |
2742 | ULONGEST spilled_value = xtensa_read_register (atreg); | |
2743 | ||
2744 | write_memory_unsigned_integer (addr, 4, | |
2745 | gdbarch_byte_order (gdbarch), | |
2746 | spilled_value); | |
2747 | } | |
2748 | ||
2749 | #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200 | |
2750 | ||
0d1703b8 | 2751 | enum xtensa_exception_handler_t |
68d6df83 | 2752 | { |
08b9c608 MG |
2753 | xtWindowOverflow, |
2754 | xtWindowUnderflow, | |
2755 | xtNoExceptionHandler | |
0d1703b8 | 2756 | }; |
08b9c608 | 2757 | |
68d6df83 | 2758 | /* Execute instruction stream from current PC until hitting RFWU or RFWO. |
08b9c608 MG |
2759 | Return type of Xtensa Window Interrupt Handler on success. */ |
2760 | static xtensa_exception_handler_t | |
2761 | execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb) | |
2762 | { | |
2763 | xtensa_isa isa; | |
2764 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2765 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
08b9c608 MG |
2766 | CORE_ADDR ia, bt, ba; |
2767 | xtensa_format ifmt; | |
2768 | int ilen, islots, is; | |
2769 | xtensa_opcode opc; | |
2770 | int insn_num = 0; | |
08b9c608 | 2771 | void (*func) (struct gdbarch *, int, int, int, CORE_ADDR); |
08106042 | 2772 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
08b9c608 | 2773 | |
19afdd07 | 2774 | uint32_t at, as, offset; |
08b9c608 MG |
2775 | |
2776 | /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ | |
2777 | int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; | |
2778 | ||
2779 | isa = xtensa_default_isa; | |
2780 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2781 | ins = xtensa_insnbuf_alloc (isa); | |
2782 | slot = xtensa_insnbuf_alloc (isa); | |
2783 | ba = 0; | |
2784 | ia = current_pc; | |
2785 | bt = ia; | |
2786 | ||
2787 | a0_was_saved = 0; | |
2788 | a7_was_saved = 0; | |
2789 | a11_was_saved = 0; | |
2790 | ||
2791 | while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN) | |
2792 | { | |
2793 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
dda83cd7 | 2794 | { |
08b9c608 MG |
2795 | ba = ia; |
2796 | bt = (ba + XTENSA_ISA_BSZ); | |
2797 | if (target_read_memory (ba, ibuf, bt - ba) != 0) | |
2798 | return xtNoExceptionHandler; | |
2799 | } | |
2800 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2801 | ifmt = xtensa_format_decode (isa, ins); | |
2802 | if (ifmt == XTENSA_UNDEFINED) | |
2803 | return xtNoExceptionHandler; | |
2804 | ilen = xtensa_format_length (isa, ifmt); | |
2805 | if (ilen == XTENSA_UNDEFINED) | |
2806 | return xtNoExceptionHandler; | |
2807 | islots = xtensa_format_num_slots (isa, ifmt); | |
2808 | if (islots == XTENSA_UNDEFINED) | |
2809 | return xtNoExceptionHandler; | |
2810 | for (is = 0; is < islots; ++is) | |
2811 | { | |
2812 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2813 | return xtNoExceptionHandler; | |
2814 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2815 | if (opc == XTENSA_UNDEFINED) | |
2816 | return xtNoExceptionHandler; | |
2817 | switch (call0_classify_opcode (isa, opc)) | |
2818 | { | |
2819 | case c0opc_illegal: | |
2820 | case c0opc_flow: | |
2821 | case c0opc_entry: | |
2822 | case c0opc_break: | |
2823 | /* We expect none of them here. */ | |
2824 | return xtNoExceptionHandler; | |
2825 | case c0opc_l32e: | |
2826 | func = execute_l32e; | |
2827 | break; | |
2828 | case c0opc_s32e: | |
2829 | func = execute_s32e; | |
2830 | break; | |
2831 | case c0opc_rfwo: /* RFWO. */ | |
2832 | /* Here, we return from WindowOverflow handler and, | |
2833 | if we stopped at the very beginning, which means | |
2834 | A0 was saved, we have to restore it now. */ | |
2835 | if (a0_was_saved) | |
2836 | { | |
2837 | int arreg = arreg_number (gdbarch, | |
345bd07c | 2838 | tdep->a0_base, |
08b9c608 MG |
2839 | wb); |
2840 | xtensa_write_register (arreg, a0_saved); | |
2841 | } | |
2842 | return xtWindowOverflow; | |
2843 | case c0opc_rfwu: /* RFWU. */ | |
2844 | /* Here, we return from WindowUnderflow handler. | |
2845 | Let's see if either A7 or A11 has to be restored. */ | |
2846 | if (WindowUnderflow12) | |
2847 | { | |
2848 | if (a11_was_saved) | |
2849 | { | |
2850 | int arreg = arreg_number (gdbarch, | |
345bd07c | 2851 | tdep->a0_base + 11, |
08b9c608 MG |
2852 | wb); |
2853 | xtensa_write_register (arreg, a11_saved); | |
2854 | } | |
2855 | } | |
2856 | else if (a7_was_saved) | |
2857 | { | |
2858 | int arreg = arreg_number (gdbarch, | |
345bd07c | 2859 | tdep->a0_base + 7, |
08b9c608 MG |
2860 | wb); |
2861 | xtensa_write_register (arreg, a7_saved); | |
2862 | } | |
2863 | return xtWindowUnderflow; | |
24b21115 | 2864 | default: /* Simply skip this insns. */ |
08b9c608 MG |
2865 | continue; |
2866 | } | |
2867 | ||
2868 | /* Decode arguments for L32E / S32E and simulate their execution. */ | |
2869 | if ( xtensa_opcode_num_operands (isa, opc) != 3 ) | |
2870 | return xtNoExceptionHandler; | |
2871 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at)) | |
2872 | return xtNoExceptionHandler; | |
2873 | if (xtensa_operand_decode (isa, opc, 0, &at)) | |
2874 | return xtNoExceptionHandler; | |
2875 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as)) | |
2876 | return xtNoExceptionHandler; | |
2877 | if (xtensa_operand_decode (isa, opc, 1, &as)) | |
2878 | return xtNoExceptionHandler; | |
2879 | if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset)) | |
2880 | return xtNoExceptionHandler; | |
2881 | if (xtensa_operand_decode (isa, opc, 2, &offset)) | |
2882 | return xtNoExceptionHandler; | |
2883 | ||
2884 | (*func) (gdbarch, at, as, offset, wb); | |
2885 | } | |
2886 | ||
2887 | ia += ilen; | |
2888 | } | |
2889 | return xtNoExceptionHandler; | |
2890 | } | |
2891 | ||
2892 | /* Handle Window Overflow / Underflow exception frames. */ | |
2893 | ||
2894 | static void | |
bd2b40ac | 2895 | xtensa_window_interrupt_frame_cache (frame_info_ptr this_frame, |
08b9c608 MG |
2896 | xtensa_frame_cache_t *cache, |
2897 | CORE_ADDR pc) | |
2898 | { | |
2899 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2900 | CORE_ADDR ps, wb, ws, ra; | |
2901 | int epc1_regnum, i, regnum; | |
2902 | xtensa_exception_handler_t eh_type; | |
08106042 | 2903 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
08b9c608 MG |
2904 | |
2905 | /* Read PS, WB, and WS from the hardware. Note that PS register | |
2906 | must be present, if Windowed ABI is supported. */ | |
2907 | ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch)); | |
345bd07c SM |
2908 | wb = xtensa_read_register (tdep->wb_regnum); |
2909 | ws = xtensa_read_register (tdep->ws_regnum); | |
08b9c608 MG |
2910 | |
2911 | /* Execute all the remaining instructions from Window Interrupt Handler | |
2912 | by simulating them on the remote protocol level. On return, set the | |
2913 | type of Xtensa Window Interrupt Handler, or report an error. */ | |
2914 | eh_type = execute_code (gdbarch, pc, wb); | |
2915 | if (eh_type == xtNoExceptionHandler) | |
2916 | error (_("\ | |
2917 | Unable to decode Xtensa Window Interrupt Handler's code.")); | |
2918 | ||
2919 | cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */ | |
2920 | cache->call0 = 0; /* It's Windowed ABI. */ | |
2921 | ||
2922 | /* All registers for the cached frame will be alive. */ | |
2923 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) | |
2924 | cache->wd.aregs[i] = -1; | |
2925 | ||
2926 | if (eh_type == xtWindowOverflow) | |
2927 | cache->wd.ws = ws ^ (1 << wb); | |
2928 | else /* eh_type == xtWindowUnderflow. */ | |
2929 | cache->wd.ws = ws | (1 << wb); | |
2930 | ||
2931 | cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */ | |
345bd07c | 2932 | regnum = arreg_number (gdbarch, tdep->a0_base, |
08b9c608 MG |
2933 | cache->wd.wb); |
2934 | ra = xtensa_read_register (regnum); | |
2935 | cache->wd.callsize = WINSIZE (ra); | |
2936 | cache->prev_sp = xtensa_read_register (regnum + 1); | |
2937 | /* Set regnum to a frame pointer of the frame being cached. */ | |
2938 | regnum = xtensa_scan_prologue (gdbarch, pc); | |
2939 | regnum = arreg_number (gdbarch, | |
345bd07c | 2940 | tdep->a0_base + regnum, |
08b9c608 MG |
2941 | cache->wd.wb); |
2942 | cache->base = get_frame_register_unsigned (this_frame, regnum); | |
2943 | ||
2944 | /* Read PC of interrupted function from EPC1 register. */ | |
2945 | epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1"); | |
2946 | if (epc1_regnum < 0) | |
2947 | error(_("Unable to read Xtensa register EPC1")); | |
2948 | cache->ra = xtensa_read_register (epc1_regnum); | |
2949 | cache->pc = get_frame_func (this_frame); | |
2950 | } | |
2951 | ||
bdb4c075 MG |
2952 | |
2953 | /* Skip function prologue. | |
2954 | ||
2955 | Return the pc of the first instruction after prologue. GDB calls this to | |
2956 | find the address of the first line of the function or (if there is no line | |
2957 | number information) to skip the prologue for planting breakpoints on | |
2958 | function entries. Use debug info (if present) or prologue analysis to skip | |
2959 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2960 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2961 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2962 | backtrace at any point in the prologue, however certain potential hazards | |
2963 | are avoided and a more "normal" debugging experience is ensured by | |
2964 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2965 | For example, if we don't skip the prologue: | |
2966 | - Some args may not yet have been saved to the stack where the debug | |
2967 | info expects to find them (true anyway when only 'entry' is skipped); | |
2968 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2969 | when the prologue analysis is done on initializing the frame cache, | |
2970 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2971 | |
2972 | If we have debug info ( line-number info, in particular ) we simply skip | |
2973 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2974 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2975 | |
2976 | int main() | |
2977 | { int local_var = 1; | |
24b21115 | 2978 | .... |
ca3bf3bd DJ |
2979 | } |
2980 | ||
2981 | because, for this source code, both Xtensa compilers will generate two | |
2982 | separate entries ( with the same line number ) in dwarf line-number | |
2983 | section to make sure there is a boundary between the prologue code and | |
2984 | the rest of the function. | |
2985 | ||
bdb4c075 MG |
2986 | If there is no debug info, we need to analyze the code. */ |
2987 | ||
2988 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 2989 | |
63807e1d | 2990 | static CORE_ADDR |
6093d2eb | 2991 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 2992 | { |
bdb4c075 MG |
2993 | struct symtab_and_line prologue_sal; |
2994 | CORE_ADDR body_pc; | |
2995 | ||
ca3bf3bd DJ |
2996 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2997 | ||
bdb4c075 MG |
2998 | #if DONT_SKIP_PROLOGUE |
2999 | return start_pc; | |
3000 | #endif | |
3001 | ||
3002 | /* Try to find first body line from debug info. */ | |
3003 | ||
3004 | prologue_sal = find_pc_line (start_pc, 0); | |
3005 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 3006 | { |
f976a05d MG |
3007 | /* In Call0, it is possible to have a function with only one instruction |
3008 | ('ret') resulting from a one-line optimized function that does nothing. | |
3009 | In that case, prologue_sal.end may actually point to the start of the | |
3010 | next function in the text section, causing a breakpoint to be set at | |
3011 | the wrong place. Check, if the end address is within a different | |
3012 | function, and if so return the start PC. We know we have symbol | |
3013 | information. */ | |
ca3bf3bd | 3014 | |
bdb4c075 MG |
3015 | CORE_ADDR end_func; |
3016 | ||
08106042 | 3017 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
345bd07c | 3018 | if ((tdep->call_abi == CallAbiCall0Only) |
f976a05d MG |
3019 | && call0_ret (start_pc, prologue_sal.end)) |
3020 | return start_pc; | |
3021 | ||
bdb4c075 MG |
3022 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); |
3023 | if (end_func != start_pc) | |
ca3bf3bd DJ |
3024 | return start_pc; |
3025 | ||
bdb4c075 | 3026 | return prologue_sal.end; |
ca3bf3bd | 3027 | } |
ca3bf3bd | 3028 | |
bdb4c075 | 3029 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
dbab50de MG |
3030 | body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, |
3031 | xtensa_alloc_frame_cache (0)); | |
bdb4c075 MG |
3032 | return body_pc != 0 ? body_pc : start_pc; |
3033 | } | |
ca3bf3bd DJ |
3034 | |
3035 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
3036 | static void |
3037 | xtensa_verify_config (struct gdbarch *gdbarch) | |
3038 | { | |
08106042 | 3039 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); |
d7e74731 | 3040 | string_file log; |
ca3bf3bd DJ |
3041 | |
3042 | /* Verify that we got a reasonable number of AREGS. */ | |
3043 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
d7e74731 | 3044 | log.printf (_("\ |
bdb4c075 | 3045 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), |
d7e74731 | 3046 | tdep->num_aregs); |
ca3bf3bd DJ |
3047 | |
3048 | /* Verify that certain registers exist. */ | |
bdb4c075 | 3049 | |
ca3bf3bd | 3050 | if (tdep->pc_regnum == -1) |
d7e74731 | 3051 | log.printf (_("\n\tpc_regnum: No PC register")); |
bdb4c075 | 3052 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) |
d7e74731 | 3053 | log.printf (_("\n\tps_regnum: No PS register")); |
bdb4c075 MG |
3054 | |
3055 | if (tdep->isa_use_windowed_registers) | |
3056 | { | |
3057 | if (tdep->wb_regnum == -1) | |
d7e74731 | 3058 | log.printf (_("\n\twb_regnum: No WB register")); |
bdb4c075 | 3059 | if (tdep->ws_regnum == -1) |
d7e74731 | 3060 | log.printf (_("\n\tws_regnum: No WS register")); |
bdb4c075 | 3061 | if (tdep->ar_base == -1) |
d7e74731 | 3062 | log.printf (_("\n\tar_base: No AR registers")); |
bdb4c075 MG |
3063 | } |
3064 | ||
ca3bf3bd | 3065 | if (tdep->a0_base == -1) |
d7e74731 | 3066 | log.printf (_("\n\ta0_base: No Ax registers")); |
ca3bf3bd | 3067 | |
d7e74731 | 3068 | if (!log.empty ()) |
f34652de | 3069 | internal_error (_("the following are invalid: %s"), log.c_str ()); |
ca3bf3bd DJ |
3070 | } |
3071 | ||
94a0e877 MG |
3072 | |
3073 | /* Derive specific register numbers from the array of registers. */ | |
3074 | ||
63807e1d | 3075 | static void |
345bd07c | 3076 | xtensa_derive_tdep (xtensa_gdbarch_tdep *tdep) |
94a0e877 MG |
3077 | { |
3078 | xtensa_register_t* rmap; | |
3079 | int n, max_size = 4; | |
3080 | ||
3081 | tdep->num_regs = 0; | |
3082 | tdep->num_nopriv_regs = 0; | |
3083 | ||
3084 | /* Special registers 0..255 (core). */ | |
3085 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
f74f865e MF |
3086 | /* User registers 0..255. */ |
3087 | #define XTENSA_DBREGN_UREG(n) (0x0300+(n)) | |
94a0e877 MG |
3088 | |
3089 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
3090 | { | |
3091 | if (rmap->target_number == 0x0020) | |
3092 | tdep->pc_regnum = n; | |
3093 | else if (rmap->target_number == 0x0100) | |
3094 | tdep->ar_base = n; | |
3095 | else if (rmap->target_number == 0x0000) | |
3096 | tdep->a0_base = n; | |
3097 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
3098 | tdep->wb_regnum = n; | |
3099 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
3100 | tdep->ws_regnum = n; | |
3101 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
3102 | tdep->debugcause_regnum = n; | |
3103 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
3104 | tdep->exccause_regnum = n; | |
3105 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
3106 | tdep->excvaddr_regnum = n; | |
3107 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
3108 | tdep->lbeg_regnum = n; | |
3109 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
3110 | tdep->lend_regnum = n; | |
3111 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
3112 | tdep->lcount_regnum = n; | |
3113 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
3114 | tdep->sar_regnum = n; | |
3115 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
3116 | tdep->litbase_regnum = n; | |
3117 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
3118 | tdep->ps_regnum = n; | |
f74f865e MF |
3119 | else if (rmap->target_number == XTENSA_DBREGN_UREG(231)) |
3120 | tdep->threadptr_regnum = n; | |
94a0e877 MG |
3121 | #if 0 |
3122 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
3123 | tdep->interrupt_regnum = n; | |
3124 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
3125 | tdep->interrupt2_regnum = n; | |
3126 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
3127 | tdep->cpenable_regnum = n; | |
3128 | #endif | |
3129 | ||
3130 | if (rmap->byte_size > max_size) | |
3131 | max_size = rmap->byte_size; | |
3132 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
3133 | tdep->num_regs = n; | |
94a0e877 | 3134 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 |
37d9e062 MF |
3135 | && tdep->num_nopriv_regs == 0) |
3136 | tdep->num_nopriv_regs = n; | |
94a0e877 | 3137 | } |
37d9e062 MF |
3138 | if (tdep->num_regs == 0) |
3139 | tdep->num_regs = tdep->num_nopriv_regs; | |
94a0e877 MG |
3140 | |
3141 | /* Number of pseudo registers. */ | |
3142 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
3143 | ||
3144 | /* Empirically determined maximum sizes. */ | |
3145 | tdep->max_register_raw_size = max_size; | |
3146 | tdep->max_register_virtual_size = max_size; | |
3147 | } | |
3148 | ||
ca3bf3bd DJ |
3149 | /* Module "constructor" function. */ |
3150 | ||
2b16913c | 3151 | extern xtensa_register_t xtensa_rmap[]; |
94a0e877 | 3152 | |
ca3bf3bd DJ |
3153 | static struct gdbarch * |
3154 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3155 | { | |
ca3bf3bd DJ |
3156 | DEBUGTRACE ("gdbarch_init()\n"); |
3157 | ||
a4398628 MF |
3158 | if (!xtensa_default_isa) |
3159 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
3160 | ||
ca3bf3bd | 3161 | /* We have to set the byte order before we call gdbarch_alloc. */ |
94a0e877 | 3162 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 3163 | |
2b16913c SM |
3164 | gdbarch *gdbarch |
3165 | = gdbarch_alloc (&info, | |
3166 | gdbarch_tdep_up (new xtensa_gdbarch_tdep (xtensa_rmap))); | |
3167 | xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch); | |
94a0e877 | 3168 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
3169 | |
3170 | /* Verify our configuration. */ | |
3171 | xtensa_verify_config (gdbarch); | |
dbab50de | 3172 | xtensa_session_once_reported = 0; |
ca3bf3bd | 3173 | |
53375380 PA |
3174 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
3175 | set_gdbarch_wchar_signed (gdbarch, 0); | |
3176 | ||
bdb4c075 | 3177 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
3178 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
3179 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
3180 | ||
3181 | /* Set target information. */ | |
3182 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
3183 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
3184 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
3185 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
3186 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
3187 | ||
ba2b1c56 | 3188 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 3189 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
3190 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
3191 | ||
3192 | /* We provide our own function to get register information. */ | |
3193 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
3194 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
3195 | ||
581e13c1 | 3196 | /* To call functions from GDB using dummy frame. */ |
ca3bf3bd DJ |
3197 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
3198 | ||
3199 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
3200 | ||
3201 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
3202 | ||
3203 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
3204 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
3205 | ||
3206 | /* Stack grows downward. */ | |
3207 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3208 | ||
3209 | /* Set breakpoints. */ | |
04180708 YQ |
3210 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3211 | xtensa_breakpoint_kind_from_pc); | |
3212 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3213 | xtensa_sw_breakpoint_from_kind); | |
ca3bf3bd DJ |
3214 | |
3215 | /* After breakpoint instruction or illegal instruction, pc still | |
3216 | points at break instruction, so don't decrement. */ | |
3217 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3218 | ||
3219 | /* We don't skip args. */ | |
3220 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3221 | ||
3222 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
3223 | ||
3224 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
3225 | ||
5142f611 | 3226 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
3227 | |
3228 | /* Frame handling. */ | |
3229 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
3230 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
3231 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd | 3232 | |
ca3bf3bd DJ |
3233 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3234 | ||
3235 | xtensa_add_reggroups (gdbarch); | |
3236 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
3237 | ||
97094034 AA |
3238 | set_gdbarch_iterate_over_regset_sections |
3239 | (gdbarch, xtensa_iterate_over_regset_sections); | |
ca3bf3bd | 3240 | |
ee967b5f MG |
3241 | set_solib_svr4_fetch_link_map_offsets |
3242 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
3243 | ||
40045d91 MF |
3244 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
3245 | gdbarch_init_osabi (info, gdbarch); | |
3246 | ||
ca3bf3bd DJ |
3247 | return gdbarch; |
3248 | } | |
3249 | ||
ca3bf3bd | 3250 | static void |
6b50c0b0 | 3251 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
3252 | { |
3253 | error (_("xtensa_dump_tdep(): not implemented")); | |
3254 | } | |
3255 | ||
6c265988 | 3256 | void _initialize_xtensa_tdep (); |
ca3bf3bd | 3257 | void |
6c265988 | 3258 | _initialize_xtensa_tdep () |
ca3bf3bd | 3259 | { |
ca3bf3bd DJ |
3260 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); |
3261 | xtensa_init_reggroups (); | |
3262 | ||
ccce17b0 YQ |
3263 | add_setshow_zuinteger_cmd ("xtensa", |
3264 | class_maintenance, | |
3265 | &xtensa_debug_level, | |
581e13c1 MS |
3266 | _("Set Xtensa debugging."), |
3267 | _("Show Xtensa debugging."), _("\ | |
ca3bf3bd DJ |
3268 | When non-zero, Xtensa-specific debugging is enabled. \ |
3269 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
ccce17b0 YQ |
3270 | NULL, |
3271 | NULL, | |
3272 | &setdebuglist, &showdebuglist); | |
ca3bf3bd | 3273 | } |