]>
Commit | Line | Data |
---|---|---|
0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
007c9b97 TBA |
38 | bool supports_z_point_type (char z_type) override; |
39 | ||
797bcff5 TBA |
40 | protected: |
41 | ||
42 | void low_arch_setup () override; | |
daca57a7 TBA |
43 | |
44 | bool low_cannot_fetch_register (int regno) override; | |
45 | ||
46 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
47 | |
48 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
49 | |
50 | bool low_supports_breakpoints () override; | |
51 | ||
52 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
53 | ||
54 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
55 | |
56 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
57 | |
58 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
59 | int size, raw_breakpoint *bp) override; | |
60 | ||
61 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
62 | int size, raw_breakpoint *bp) override; | |
ef0478f6 TBA |
63 | }; |
64 | ||
65 | /* The singleton target ops object. */ | |
66 | ||
67 | static mips_target the_mips_target; | |
68 | ||
d05b4ac3 UW |
69 | /* Defined in auto-generated file mips-linux.c. */ |
70 | void init_registers_mips_linux (void); | |
3aee8918 PA |
71 | extern const struct target_desc *tdesc_mips_linux; |
72 | ||
1faeff08 MR |
73 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
74 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
75 | extern const struct target_desc *tdesc_mips_dsp_linux; |
76 | ||
d05b4ac3 UW |
77 | /* Defined in auto-generated file mips64-linux.c. */ |
78 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
79 | extern const struct target_desc *tdesc_mips64_linux; |
80 | ||
1faeff08 MR |
81 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
82 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 83 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
84 | |
85 | #ifdef __mips64 | |
3aee8918 PA |
86 | #define tdesc_mips_linux tdesc_mips64_linux |
87 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 88 | #endif |
d05b4ac3 | 89 | |
21b0f40c DJ |
90 | #ifndef PTRACE_GET_THREAD_AREA |
91 | #define PTRACE_GET_THREAD_AREA 25 | |
92 | #endif | |
93 | ||
0a30fbc4 DJ |
94 | #ifdef HAVE_SYS_REG_H |
95 | #include <sys/reg.h> | |
96 | #endif | |
97 | ||
117ce543 | 98 | #define mips_num_regs 73 |
1faeff08 | 99 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
100 | |
101 | #include <asm/ptrace.h> | |
102 | ||
1faeff08 MR |
103 | #ifndef DSP_BASE |
104 | #define DSP_BASE 71 | |
105 | #define DSP_CONTROL 77 | |
106 | #endif | |
107 | ||
186947f7 DJ |
108 | union mips_register |
109 | { | |
110 | unsigned char buf[8]; | |
111 | ||
112 | /* Deliberately signed, for proper sign extension. */ | |
113 | int reg32; | |
114 | long long reg64; | |
115 | }; | |
116 | ||
0a30fbc4 DJ |
117 | /* Return the ptrace ``address'' of register REGNO. */ |
118 | ||
1faeff08 MR |
119 | #define mips_base_regs \ |
120 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
121 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
122 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
123 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
124 | \ | |
125 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
126 | \ | |
127 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
128 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
129 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
130 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
131 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
132 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
133 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
134 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
135 | FPC_CSR, FPC_EIR | |
136 | ||
137 | #define mips_dsp_regs \ | |
138 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
139 | DSP_BASE + 4, DSP_BASE + 5, \ | |
140 | DSP_CONTROL | |
141 | ||
142 | static int mips_regmap[mips_num_regs] = { | |
143 | mips_base_regs, | |
144 | 0 | |
145 | }; | |
0a30fbc4 | 146 | |
1faeff08 MR |
147 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
148 | mips_base_regs, | |
149 | mips_dsp_regs, | |
150 | 0 | |
151 | }; | |
0a30fbc4 | 152 | |
1faeff08 MR |
153 | /* DSP registers are not in any regset and can only be accessed |
154 | individually. */ | |
0a30fbc4 | 155 | |
1faeff08 MR |
156 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
157 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
158 | }; |
159 | ||
3aee8918 PA |
160 | static int have_dsp = -1; |
161 | ||
1faeff08 MR |
162 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
163 | user register set accordingly. */ | |
164 | ||
3aee8918 PA |
165 | static const struct target_desc * |
166 | mips_read_description (void) | |
1faeff08 | 167 | { |
3aee8918 | 168 | if (have_dsp < 0) |
1faeff08 | 169 | { |
0bfdf32f | 170 | int pid = lwpid_of (current_thread); |
1faeff08 | 171 | |
ac740bc7 | 172 | errno = 0; |
1faeff08 MR |
173 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
174 | switch (errno) | |
175 | { | |
176 | case 0: | |
3aee8918 | 177 | have_dsp = 1; |
1faeff08 MR |
178 | break; |
179 | case EIO: | |
3aee8918 | 180 | have_dsp = 0; |
1faeff08 MR |
181 | break; |
182 | default: | |
183 | perror_with_name ("ptrace"); | |
184 | break; | |
185 | } | |
186 | } | |
3aee8918 PA |
187 | |
188 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
189 | } | |
190 | ||
797bcff5 TBA |
191 | void |
192 | mips_target::low_arch_setup () | |
3aee8918 PA |
193 | { |
194 | current_process ()->tdesc = mips_read_description (); | |
195 | } | |
196 | ||
7a60ad40 YQ |
197 | /* Per-process arch-specific data we want to keep. */ |
198 | ||
199 | struct arch_process_info | |
200 | { | |
201 | /* -1 if the kernel and/or CPU do not support watch registers. | |
202 | 1 if watch_readback is valid and we can read style, num_valid | |
203 | and the masks. | |
204 | 0 if we need to read the watch_readback. */ | |
205 | ||
206 | int watch_readback_valid; | |
207 | ||
208 | /* Cached watch register read values. */ | |
209 | ||
210 | struct pt_watch_regs watch_readback; | |
211 | ||
212 | /* Current watchpoint requests for this process. */ | |
213 | ||
214 | struct mips_watchpoint *current_watches; | |
215 | ||
216 | /* The current set of watch register values for writing the | |
217 | registers. */ | |
218 | ||
219 | struct pt_watch_regs watch_mirror; | |
220 | }; | |
221 | ||
222 | /* Per-thread arch-specific data we want to keep. */ | |
223 | ||
224 | struct arch_lwp_info | |
225 | { | |
226 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
227 | int watch_registers_changed; | |
228 | }; | |
229 | ||
0a30fbc4 DJ |
230 | /* From mips-linux-nat.c. */ |
231 | ||
232 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
233 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
234 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
235 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 236 | |
daca57a7 TBA |
237 | bool |
238 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 239 | { |
3aee8918 PA |
240 | const struct target_desc *tdesc; |
241 | ||
daca57a7 TBA |
242 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
243 | return true; | |
0a30fbc4 | 244 | |
3aee8918 PA |
245 | tdesc = current_process ()->tdesc; |
246 | ||
75d74cca MR |
247 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
248 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 249 | return true; |
75d74cca | 250 | |
3aee8918 | 251 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 252 | return true; |
0a30fbc4 | 253 | |
daca57a7 | 254 | return false; |
0a30fbc4 DJ |
255 | } |
256 | ||
daca57a7 TBA |
257 | bool |
258 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 259 | { |
3aee8918 PA |
260 | const struct target_desc *tdesc; |
261 | ||
daca57a7 TBA |
262 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
263 | return true; | |
0a30fbc4 | 264 | |
3aee8918 PA |
265 | tdesc = current_process ()->tdesc; |
266 | ||
75d74cca MR |
267 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
268 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 269 | return true; |
75d74cca | 270 | |
3aee8918 | 271 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 272 | return true; |
0a30fbc4 | 273 | |
3aee8918 | 274 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 275 | return true; |
0a30fbc4 | 276 | |
3aee8918 | 277 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 278 | return true; |
0a30fbc4 | 279 | |
3aee8918 | 280 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 281 | return true; |
0a30fbc4 | 282 | |
daca57a7 | 283 | return false; |
0a30fbc4 | 284 | } |
2ec06d2e | 285 | |
bd70b1f2 TBA |
286 | bool |
287 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
288 | { |
289 | const struct target_desc *tdesc = current_process ()->tdesc; | |
290 | ||
291 | if (find_regno (tdesc, "r0") == regno) | |
292 | { | |
293 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 294 | return true; |
e4439e43 MR |
295 | } |
296 | ||
bd70b1f2 | 297 | return false; |
e4439e43 MR |
298 | } |
299 | ||
bf9ae9d8 TBA |
300 | bool |
301 | mips_target::low_supports_breakpoints () | |
302 | { | |
303 | return true; | |
304 | } | |
305 | ||
306 | CORE_ADDR | |
307 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 308 | { |
186947f7 | 309 | union mips_register pc; |
442ea881 | 310 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 311 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
312 | } |
313 | ||
bf9ae9d8 TBA |
314 | void |
315 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 316 | { |
186947f7 | 317 | union mips_register newpc; |
3aee8918 | 318 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
319 | newpc.reg32 = pc; |
320 | else | |
321 | newpc.reg64 = pc; | |
322 | ||
442ea881 | 323 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
324 | } |
325 | ||
326 | /* Correct in either endianness. */ | |
186947f7 | 327 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
328 | #define mips_breakpoint_len 4 |
329 | ||
3ca4edb6 | 330 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 331 | |
3ca4edb6 TBA |
332 | const gdb_byte * |
333 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
334 | { |
335 | *size = mips_breakpoint_len; | |
336 | return (const gdb_byte *) &mips_breakpoint; | |
337 | } | |
338 | ||
d7146cda TBA |
339 | bool |
340 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 341 | { |
186947f7 | 342 | unsigned int insn; |
0d62e5e8 | 343 | |
d7146cda | 344 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 345 | if (insn == mips_breakpoint) |
d7146cda | 346 | return true; |
0d62e5e8 DJ |
347 | |
348 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
349 | one. */ | |
d7146cda | 350 | return false; |
0d62e5e8 DJ |
351 | } |
352 | ||
da25033c | 353 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 354 | |
da25033c SM |
355 | static void |
356 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 357 | { |
d86d4aaf | 358 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 359 | |
da25033c SM |
360 | /* The actual update is done later just before resuming the lwp, |
361 | we just mark that the registers need updating. */ | |
362 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 363 | |
da25033c SM |
364 | /* If the lwp isn't stopped, force it to momentarily pause, so |
365 | we can update its watch registers. */ | |
366 | if (!lwp->stopped) | |
367 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
368 | } |
369 | ||
370 | /* This is the implementation of linux_target_ops method | |
371 | new_process. */ | |
372 | ||
373 | static struct arch_process_info * | |
374 | mips_linux_new_process (void) | |
375 | { | |
8d749320 | 376 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
377 | |
378 | return info; | |
379 | } | |
380 | ||
04ec7890 SM |
381 | /* This is the implementation of linux_target_ops method |
382 | delete_process. */ | |
383 | ||
384 | static void | |
385 | mips_linux_delete_process (struct arch_process_info *info) | |
386 | { | |
387 | xfree (info); | |
388 | } | |
389 | ||
7a60ad40 YQ |
390 | /* This is the implementation of linux_target_ops method new_thread. |
391 | Mark the watch registers as changed, so the threads' copies will | |
392 | be updated. */ | |
393 | ||
34c703da GB |
394 | static void |
395 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 396 | { |
8d749320 | 397 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
398 | |
399 | info->watch_registers_changed = 1; | |
400 | ||
34c703da | 401 | lwp->arch_private = info; |
7a60ad40 YQ |
402 | } |
403 | ||
466eecee SM |
404 | /* Function to call when a thread is being deleted. */ |
405 | ||
406 | static void | |
407 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
408 | { | |
409 | xfree (arch_lwp); | |
410 | } | |
411 | ||
3a8a0396 DB |
412 | /* Create a new mips_watchpoint and add it to the list. */ |
413 | ||
414 | static void | |
cbec665b | 415 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 416 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
417 | { |
418 | struct mips_watchpoint *new_watch; | |
419 | struct mips_watchpoint **pw; | |
420 | ||
8d749320 | 421 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
422 | new_watch->addr = addr; |
423 | new_watch->len = len; | |
424 | new_watch->type = watch_type; | |
425 | new_watch->next = NULL; | |
426 | ||
cbec665b | 427 | pw = &priv->current_watches; |
3a8a0396 DB |
428 | while (*pw != NULL) |
429 | pw = &(*pw)->next; | |
430 | *pw = new_watch; | |
431 | } | |
432 | ||
433 | /* Hook to call when a new fork is attached. */ | |
434 | ||
435 | static void | |
436 | mips_linux_new_fork (struct process_info *parent, | |
437 | struct process_info *child) | |
438 | { | |
439 | struct arch_process_info *parent_private; | |
440 | struct arch_process_info *child_private; | |
441 | struct mips_watchpoint *wp; | |
442 | ||
443 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
444 | gdb_assert (parent->priv != NULL |
445 | && parent->priv->arch_private != NULL); | |
446 | gdb_assert (child->priv != NULL | |
447 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
448 | |
449 | /* Linux kernel before 2.6.33 commit | |
450 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
451 | will inherit hardware debug registers from parent | |
452 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
453 | zeroed debug registers. | |
454 | ||
455 | GDB core assumes the child inherits the watchpoints/hw | |
456 | breakpoints of the parent, and will remove them all from the | |
457 | forked off process. Copy the debug registers mirrors into the | |
458 | new process so that all breakpoints and watchpoints can be | |
459 | removed together. The debug registers mirror will become zeroed | |
460 | in the end before detaching the forked off process, thus making | |
461 | this compatible with older Linux kernels too. */ | |
462 | ||
61a7418c DB |
463 | parent_private = parent->priv->arch_private; |
464 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
465 | |
466 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
467 | child_private->watch_readback = parent_private->watch_readback; | |
468 | ||
469 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
470 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
471 | ||
472 | child_private->watch_mirror = parent_private->watch_mirror; | |
473 | } | |
7a60ad40 YQ |
474 | /* This is the implementation of linux_target_ops method |
475 | prepare_to_resume. If the watch regs have changed, update the | |
476 | thread's copies. */ | |
477 | ||
478 | static void | |
479 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
480 | { | |
d86d4aaf | 481 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 482 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 483 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
484 | |
485 | if (lwp->arch_private->watch_registers_changed) | |
486 | { | |
487 | /* Only update the watch registers if we have set or unset a | |
488 | watchpoint already. */ | |
fe978cb0 | 489 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
490 | { |
491 | /* Write the mirrored watch register values. */ | |
e38504b3 | 492 | int tid = ptid.lwp (); |
7a60ad40 YQ |
493 | |
494 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 495 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
496 | perror_with_name ("Couldn't write watch register"); |
497 | } | |
498 | ||
499 | lwp->arch_private->watch_registers_changed = 0; | |
500 | } | |
501 | } | |
502 | ||
007c9b97 TBA |
503 | bool |
504 | mips_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
505 | { |
506 | switch (z_type) | |
507 | { | |
508 | case Z_PACKET_WRITE_WP: | |
509 | case Z_PACKET_READ_WP: | |
510 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 511 | return true; |
802e8e6d | 512 | default: |
007c9b97 | 513 | return false; |
802e8e6d PA |
514 | } |
515 | } | |
516 | ||
9db9aa23 TBA |
517 | /* This is the implementation of linux target ops method |
518 | low_insert_point. */ | |
7a60ad40 | 519 | |
9db9aa23 TBA |
520 | int |
521 | mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
522 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
523 | { |
524 | struct process_info *proc = current_process (); | |
fe978cb0 | 525 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 526 | struct pt_watch_regs regs; |
7a60ad40 YQ |
527 | long lwpid; |
528 | enum target_hw_bp_type watch_type; | |
529 | uint32_t irw; | |
530 | ||
0bfdf32f | 531 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 532 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
533 | &priv->watch_readback, |
534 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
535 | 0)) |
536 | return -1; | |
537 | ||
538 | if (len <= 0) | |
539 | return -1; | |
540 | ||
fe978cb0 | 541 | regs = priv->watch_readback; |
7a60ad40 | 542 | /* Add the current watches. */ |
fe978cb0 | 543 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
544 | |
545 | /* Now try to add the new watch. */ | |
802e8e6d | 546 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
547 | irw = mips_linux_watch_type_to_irw (watch_type); |
548 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
549 | return -1; | |
550 | ||
551 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 552 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 553 | |
fe978cb0 | 554 | priv->watch_mirror = regs; |
7a60ad40 YQ |
555 | |
556 | /* Only update the threads of this process. */ | |
da25033c | 557 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
558 | |
559 | return 0; | |
560 | } | |
561 | ||
9db9aa23 TBA |
562 | /* This is the implementation of linux target ops method |
563 | low_remove_point. */ | |
7a60ad40 | 564 | |
9db9aa23 TBA |
565 | int |
566 | mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
567 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
568 | { |
569 | struct process_info *proc = current_process (); | |
fe978cb0 | 570 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
571 | |
572 | int deleted_one; | |
7a60ad40 YQ |
573 | enum target_hw_bp_type watch_type; |
574 | ||
575 | struct mips_watchpoint **pw; | |
576 | struct mips_watchpoint *w; | |
577 | ||
7a60ad40 | 578 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 579 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 580 | deleted_one = 0; |
fe978cb0 | 581 | pw = &priv->current_watches; |
7a60ad40 YQ |
582 | while ((w = *pw)) |
583 | { | |
584 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
585 | { | |
586 | *pw = w->next; | |
587 | free (w); | |
588 | deleted_one = 1; | |
589 | break; | |
590 | } | |
591 | pw = &(w->next); | |
592 | } | |
593 | ||
594 | if (!deleted_one) | |
595 | return -1; /* We don't know about it, fail doing nothing. */ | |
596 | ||
597 | /* At this point watch_readback is known to be valid because we | |
598 | could not have added the watch without reading it. */ | |
fe978cb0 | 599 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 600 | |
fe978cb0 PA |
601 | priv->watch_mirror = priv->watch_readback; |
602 | mips_linux_watch_populate_regs (priv->current_watches, | |
603 | &priv->watch_mirror); | |
7a60ad40 YQ |
604 | |
605 | /* Only update the threads of this process. */ | |
da25033c SM |
606 | for_each_thread (proc->pid, update_watch_registers_callback); |
607 | ||
7a60ad40 YQ |
608 | return 0; |
609 | } | |
610 | ||
611 | /* This is the implementation of linux_target_ops method | |
612 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
613 | the watch register triggered. */ | |
614 | ||
615 | static int | |
616 | mips_stopped_by_watchpoint (void) | |
617 | { | |
618 | struct process_info *proc = current_process (); | |
fe978cb0 | 619 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
620 | int n; |
621 | int num_valid; | |
0bfdf32f | 622 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
623 | |
624 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
625 | &priv->watch_readback, |
626 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
627 | 1)) |
628 | return 0; | |
629 | ||
fe978cb0 | 630 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
631 | |
632 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 633 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
634 | & (R_MASK | W_MASK)) |
635 | return 1; | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | /* This is the implementation of linux_target_ops method | |
641 | stopped_data_address. */ | |
642 | ||
643 | static CORE_ADDR | |
644 | mips_stopped_data_address (void) | |
645 | { | |
646 | struct process_info *proc = current_process (); | |
fe978cb0 | 647 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
648 | int n; |
649 | int num_valid; | |
0bfdf32f | 650 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
651 | |
652 | /* On MIPS we don't know the low order 3 bits of the data address. | |
653 | GDB does not support remote targets that can't report the | |
654 | watchpoint address. So, make our best guess; return the starting | |
655 | address of a watchpoint request which overlaps the one that | |
656 | triggered. */ | |
657 | ||
658 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
659 | &priv->watch_readback, |
660 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
661 | 0)) |
662 | return 0; | |
663 | ||
fe978cb0 | 664 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
665 | |
666 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 667 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
668 | & (R_MASK | W_MASK)) |
669 | { | |
670 | CORE_ADDR t_low, t_hi; | |
671 | int t_irw; | |
672 | struct mips_watchpoint *watch; | |
673 | ||
fe978cb0 | 674 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 675 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 676 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
677 | | IRW_MASK); |
678 | t_low &= ~(CORE_ADDR)t_hi; | |
679 | ||
fe978cb0 | 680 | for (watch = priv->current_watches; |
7a60ad40 YQ |
681 | watch != NULL; |
682 | watch = watch->next) | |
683 | { | |
684 | CORE_ADDR addr = watch->addr; | |
685 | CORE_ADDR last_byte = addr + watch->len - 1; | |
686 | ||
687 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
688 | { | |
689 | /* Different type. */ | |
690 | continue; | |
691 | } | |
692 | /* Check for overlap of even a single byte. */ | |
693 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
694 | return addr; | |
695 | } | |
696 | } | |
697 | ||
698 | /* Shouldn't happen. */ | |
699 | return 0; | |
700 | } | |
701 | ||
21b0f40c DJ |
702 | /* Fetch the thread-local storage pointer for libthread_db. */ |
703 | ||
704 | ps_err_e | |
754653a7 | 705 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 706 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
707 | { |
708 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
709 | return PS_ERR; | |
710 | ||
711 | /* IDX is the bias from the thread pointer to the beginning of the | |
712 | thread descriptor. It has to be subtracted due to implementation | |
713 | quirks in libthread_db. */ | |
714 | *base = (void *) ((char *)*base - idx); | |
715 | ||
716 | return PS_OK; | |
717 | } | |
718 | ||
186947f7 | 719 | static void |
442ea881 PA |
720 | mips_collect_register (struct regcache *regcache, |
721 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
722 | { |
723 | union mips_register tmp_reg; | |
724 | ||
725 | if (use_64bit) | |
726 | { | |
442ea881 | 727 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
728 | *reg = tmp_reg; |
729 | } | |
730 | else | |
731 | { | |
442ea881 | 732 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
733 | reg->reg64 = tmp_reg.reg32; |
734 | } | |
735 | } | |
736 | ||
737 | static void | |
442ea881 PA |
738 | mips_supply_register (struct regcache *regcache, |
739 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
740 | { |
741 | int offset = 0; | |
742 | ||
743 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
744 | eight-byte slot. */ | |
745 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
746 | offset = 4; | |
747 | ||
442ea881 | 748 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
749 | } |
750 | ||
7e947ad3 MR |
751 | #ifdef HAVE_PTRACE_GETREGS |
752 | ||
186947f7 | 753 | static void |
442ea881 PA |
754 | mips_collect_register_32bit (struct regcache *regcache, |
755 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
756 | { |
757 | union mips_register tmp_reg; | |
758 | int reg32; | |
759 | ||
442ea881 | 760 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
761 | reg32 = tmp_reg.reg64; |
762 | memcpy (buf, ®32, 4); | |
763 | } | |
764 | ||
765 | static void | |
442ea881 PA |
766 | mips_supply_register_32bit (struct regcache *regcache, |
767 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
768 | { |
769 | union mips_register tmp_reg; | |
770 | int reg32; | |
771 | ||
772 | memcpy (®32, buf, 4); | |
773 | tmp_reg.reg64 = reg32; | |
442ea881 | 774 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
775 | } |
776 | ||
777 | static void | |
442ea881 | 778 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 779 | { |
1996e237 | 780 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 781 | int i, use_64bit; |
3aee8918 | 782 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 783 | |
3aee8918 | 784 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 785 | |
117ce543 | 786 | for (i = 1; i < 32; i++) |
442ea881 PA |
787 | mips_collect_register (regcache, use_64bit, i, regset + i); |
788 | ||
789 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 790 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 791 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 792 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 793 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 794 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 795 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 796 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 797 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 798 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 799 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 800 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
801 | |
802 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 803 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
804 | } |
805 | ||
806 | static void | |
442ea881 | 807 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 808 | { |
1996e237 | 809 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
810 | int i, use_64bit; |
811 | ||
3aee8918 | 812 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 813 | |
e4439e43 MR |
814 | supply_register_by_name_zeroed (regcache, "r0"); |
815 | ||
816 | for (i = 1; i < 32; i++) | |
442ea881 PA |
817 | mips_supply_register (regcache, use_64bit, i, regset + i); |
818 | ||
442ea881 | 819 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
820 | find_regno (regcache->tdesc, "lo"), regset + 32); |
821 | mips_supply_register (regcache, use_64bit, | |
822 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 823 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 824 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 825 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
826 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
827 | mips_supply_register (regcache, use_64bit, | |
828 | find_regno (regcache->tdesc, "status"), regset + 36); | |
829 | mips_supply_register (regcache, use_64bit, | |
830 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
831 | |
832 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 833 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
834 | } |
835 | ||
836 | static void | |
442ea881 | 837 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 838 | { |
1996e237 | 839 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
840 | int i, use_64bit, first_fp, big_endian; |
841 | ||
3aee8918 PA |
842 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
843 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
844 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
845 | ||
846 | /* See GDB for a discussion of this peculiar layout. */ | |
847 | for (i = 0; i < 32; i++) | |
848 | if (use_64bit) | |
442ea881 | 849 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 850 | else |
442ea881 | 851 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
852 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
853 | ||
442ea881 | 854 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
855 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
856 | mips_collect_register_32bit (regcache, use_64bit, | |
857 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
858 | regset[32].buf + 4); |
859 | } | |
860 | ||
861 | static void | |
442ea881 | 862 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 863 | { |
1996e237 | 864 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
865 | int i, use_64bit, first_fp, big_endian; |
866 | ||
3aee8918 PA |
867 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
868 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
869 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
870 | ||
871 | /* See GDB for a discussion of this peculiar layout. */ | |
872 | for (i = 0; i < 32; i++) | |
873 | if (use_64bit) | |
442ea881 | 874 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 875 | else |
442ea881 | 876 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
877 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
878 | ||
442ea881 | 879 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
880 | find_regno (regcache->tdesc, "fcsr"), |
881 | regset[32].buf); | |
882 | mips_supply_register_32bit (regcache, use_64bit, | |
883 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
884 | regset[32].buf + 4); |
885 | } | |
886 | #endif /* HAVE_PTRACE_GETREGS */ | |
887 | ||
7e947ad3 MR |
888 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
889 | ||
890 | static void | |
891 | mips_collect_ptrace_register (struct regcache *regcache, | |
892 | int regno, char *buf) | |
893 | { | |
7e947ad3 MR |
894 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
895 | ||
896 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
897 | { | |
898 | union mips_register reg; | |
899 | ||
900 | mips_collect_register (regcache, 0, regno, ®); | |
901 | memcpy (buf, ®, sizeof (reg)); | |
902 | } | |
903 | else | |
904 | collect_register (regcache, regno, buf); | |
905 | } | |
906 | ||
907 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
908 | ||
909 | static void | |
910 | mips_supply_ptrace_register (struct regcache *regcache, | |
911 | int regno, const char *buf) | |
912 | { | |
7e947ad3 MR |
913 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
914 | ||
915 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
916 | { | |
917 | union mips_register reg; | |
918 | ||
919 | memcpy (®, buf, sizeof (reg)); | |
920 | mips_supply_register (regcache, 0, regno, ®); | |
921 | } | |
922 | else | |
923 | supply_register (regcache, regno, buf); | |
924 | } | |
925 | ||
3aee8918 | 926 | static struct regset_info mips_regsets[] = { |
186947f7 | 927 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 928 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 929 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 930 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
931 | mips_fill_fpregset, mips_store_fpregset }, |
932 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 933 | NULL_REGSET |
186947f7 DJ |
934 | }; |
935 | ||
3aee8918 PA |
936 | static struct regsets_info mips_regsets_info = |
937 | { | |
938 | mips_regsets, /* regsets */ | |
939 | 0, /* num_regsets */ | |
940 | NULL, /* disabled_regsets */ | |
941 | }; | |
942 | ||
943 | static struct usrregs_info mips_dsp_usrregs_info = | |
944 | { | |
945 | mips_dsp_num_regs, | |
946 | mips_dsp_regmap, | |
947 | }; | |
948 | ||
949 | static struct usrregs_info mips_usrregs_info = | |
950 | { | |
951 | mips_num_regs, | |
952 | mips_regmap, | |
953 | }; | |
954 | ||
955 | static struct regs_info dsp_regs_info = | |
956 | { | |
957 | mips_dsp_regset_bitmap, | |
958 | &mips_dsp_usrregs_info, | |
959 | &mips_regsets_info | |
960 | }; | |
961 | ||
aa8d21c9 | 962 | static struct regs_info myregs_info = |
3aee8918 PA |
963 | { |
964 | NULL, /* regset_bitmap */ | |
965 | &mips_usrregs_info, | |
966 | &mips_regsets_info | |
967 | }; | |
968 | ||
aa8d21c9 TBA |
969 | const regs_info * |
970 | mips_target::get_regs_info () | |
3aee8918 PA |
971 | { |
972 | if (have_dsp) | |
973 | return &dsp_regs_info; | |
974 | else | |
aa8d21c9 | 975 | return &myregs_info; |
3aee8918 PA |
976 | } |
977 | ||
2ec06d2e | 978 | struct linux_target_ops the_low_target = { |
7a60ad40 YQ |
979 | mips_stopped_by_watchpoint, |
980 | mips_stopped_data_address, | |
7e947ad3 MR |
981 | mips_collect_ptrace_register, |
982 | mips_supply_ptrace_register, | |
7a60ad40 YQ |
983 | NULL, /* siginfo_fixup */ |
984 | mips_linux_new_process, | |
04ec7890 | 985 | mips_linux_delete_process, |
7a60ad40 | 986 | mips_linux_new_thread, |
466eecee | 987 | mips_linux_delete_thread, |
3a8a0396 | 988 | mips_linux_new_fork, |
7a60ad40 | 989 | mips_linux_prepare_to_resume |
2ec06d2e | 990 | }; |
3aee8918 | 991 | |
ef0478f6 TBA |
992 | /* The linux target ops object. */ |
993 | ||
994 | linux_process_target *the_linux_target = &the_mips_target; | |
995 | ||
3aee8918 PA |
996 | void |
997 | initialize_low_arch (void) | |
998 | { | |
999 | /* Initialize the Linux target descriptions. */ | |
1000 | init_registers_mips_linux (); | |
1001 | init_registers_mips_dsp_linux (); | |
1002 | init_registers_mips64_linux (); | |
1003 | init_registers_mips64_dsp_linux (); | |
1004 | ||
1005 | initialize_regsets_info (&mips_regsets_info); | |
1006 | } |