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Commit | Line | Data |
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93d89f63 IY |
1 | /* |
2 | * ACPI implementation | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This library is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * Lesser General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU Lesser General Public | |
16 | * License along with this library; if not, see <http://www.gnu.org/licenses/> | |
6b620ca3 PB |
17 | * |
18 | * Contributions after 2012-01-13 are licensed under the terms of the | |
19 | * GNU GPL, version 2 or (at your option) any later version. | |
93d89f63 | 20 | */ |
71e8a915 | 21 | |
b6a0aa05 | 22 | #include "qemu/osdep.h" |
0d09e41a | 23 | #include "hw/i386/pc.h" |
64552b6b | 24 | #include "hw/irq.h" |
0d09e41a PB |
25 | #include "hw/isa/apm.h" |
26 | #include "hw/i2c/pm_smbus.h" | |
83c9f4ca | 27 | #include "hw/pci/pci.h" |
0d09e41a | 28 | #include "hw/acpi/acpi.h" |
71e8a915 | 29 | #include "sysemu/reset.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
da34e65c | 31 | #include "qapi/error.h" |
1de7afc9 | 32 | #include "qemu/range.h" |
022c62cb | 33 | #include "exec/address-spaces.h" |
277e9340 | 34 | #include "hw/acpi/piix4.h" |
9e047b98 | 35 | #include "hw/acpi/pcihp.h" |
81cea5e7 | 36 | #include "hw/acpi/cpu_hotplug.h" |
5e1b5d93 | 37 | #include "hw/acpi/cpu.h" |
c24d5e0b | 38 | #include "hw/hotplug.h" |
34774320 IM |
39 | #include "hw/mem/pc-dimm.h" |
40 | #include "hw/acpi/memory_hotplug.h" | |
43f50410 | 41 | #include "hw/acpi/acpi_dev_interface.h" |
91ab2ed7 | 42 | #include "hw/xen/xen.h" |
ca77ee28 | 43 | #include "migration/qemu-file-types.h" |
d6454270 | 44 | #include "migration/vmstate.h" |
7d0c99a9 | 45 | #include "qom/cpu.h" |
b37d56ec | 46 | #include "trace.h" |
50d8ff8b | 47 | |
ac404095 | 48 | #define GPE_BASE 0xafe0 |
23910d3f | 49 | #define GPE_LEN 4 |
c177684c | 50 | |
ac404095 | 51 | struct pci_status { |
7faa8075 | 52 | uint32_t up; /* deprecated, maintained for migration compatibility */ |
ac404095 IY |
53 | uint32_t down; |
54 | }; | |
55 | ||
93d89f63 | 56 | typedef struct PIIX4PMState { |
6a6b5580 AF |
57 | /*< private >*/ |
58 | PCIDevice parent_obj; | |
59 | /*< public >*/ | |
56e5b2a1 | 60 | |
af11110b | 61 | MemoryRegion io; |
277e9340 MT |
62 | uint32_t io_base; |
63 | ||
b65b93f2 | 64 | MemoryRegion io_gpe; |
355bf2e5 | 65 | ACPIREGS ar; |
93d89f63 IY |
66 | |
67 | APMState apm; | |
68 | ||
93d89f63 | 69 | PMSMBus smb; |
e8ec0571 | 70 | uint32_t smb_io_base; |
93d89f63 IY |
71 | |
72 | qemu_irq irq; | |
93d89f63 | 73 | qemu_irq smi_irq; |
61e66c62 | 74 | int smm_enabled; |
6141dbfe | 75 | Notifier machine_ready; |
d010f91c | 76 | Notifier powerdown_notifier; |
ac404095 | 77 | |
9e047b98 MT |
78 | AcpiPciHpState acpi_pci_hotplug; |
79 | bool use_acpi_pci_hotplug; | |
80 | ||
459ae5ea GN |
81 | uint8_t disable_s3; |
82 | uint8_t disable_s4; | |
83 | uint8_t s4_val; | |
b8622725 | 84 | |
16bcab97 | 85 | bool cpu_hotplug_legacy; |
81cea5e7 | 86 | AcpiCpuHotplug gpe_cpu; |
5e1b5d93 | 87 | CPUHotplugState cpuhp_state; |
34774320 IM |
88 | |
89 | MemHotplugState acpi_memory_hotplug; | |
93d89f63 IY |
90 | } PIIX4PMState; |
91 | ||
74e445f6 PC |
92 | #define PIIX4_PM(obj) \ |
93 | OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM) | |
94 | ||
56e5b2a1 GH |
95 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
96 | PCIBus *bus, PIIX4PMState *s); | |
ac404095 | 97 | |
93d89f63 IY |
98 | #define ACPI_ENABLE 0xf1 |
99 | #define ACPI_DISABLE 0xf0 | |
100 | ||
355bf2e5 | 101 | static void pm_tmr_timer(ACPIREGS *ar) |
93d89f63 | 102 | { |
355bf2e5 | 103 | PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); |
06313503 | 104 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
105 | } |
106 | ||
93d89f63 IY |
107 | static void apm_ctrl_changed(uint32_t val, void *arg) |
108 | { | |
109 | PIIX4PMState *s = arg; | |
6a6b5580 | 110 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 IY |
111 | |
112 | /* ACPI specs 3.0, 4.7.2.5 */ | |
355bf2e5 | 113 | acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); |
afd6895b PB |
114 | if (val == ACPI_ENABLE || val == ACPI_DISABLE) { |
115 | return; | |
116 | } | |
93d89f63 | 117 | |
6a6b5580 | 118 | if (d->config[0x5b] & (1 << 1)) { |
93d89f63 IY |
119 | if (s->smi_irq) { |
120 | qemu_irq_raise(s->smi_irq); | |
121 | } | |
122 | } | |
123 | } | |
124 | ||
93d89f63 IY |
125 | static void pm_io_space_update(PIIX4PMState *s) |
126 | { | |
6a6b5580 | 127 | PCIDevice *d = PCI_DEVICE(s); |
93d89f63 | 128 | |
277e9340 MT |
129 | s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); |
130 | s->io_base &= 0xffc0; | |
93d89f63 | 131 | |
af11110b | 132 | memory_region_transaction_begin(); |
6a6b5580 | 133 | memory_region_set_enabled(&s->io, d->config[0x80] & 1); |
277e9340 | 134 | memory_region_set_address(&s->io, s->io_base); |
af11110b | 135 | memory_region_transaction_commit(); |
93d89f63 IY |
136 | } |
137 | ||
24fe083d GH |
138 | static void smbus_io_space_update(PIIX4PMState *s) |
139 | { | |
6a6b5580 AF |
140 | PCIDevice *d = PCI_DEVICE(s); |
141 | ||
142 | s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); | |
24fe083d GH |
143 | s->smb_io_base &= 0xffc0; |
144 | ||
145 | memory_region_transaction_begin(); | |
6a6b5580 | 146 | memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); |
24fe083d GH |
147 | memory_region_set_address(&s->smb.io, s->smb_io_base); |
148 | memory_region_transaction_commit(); | |
93d89f63 IY |
149 | } |
150 | ||
151 | static void pm_write_config(PCIDevice *d, | |
152 | uint32_t address, uint32_t val, int len) | |
153 | { | |
154 | pci_default_write_config(d, address, val, len); | |
24fe083d GH |
155 | if (range_covers_byte(address, len, 0x80) || |
156 | ranges_overlap(address, len, 0x40, 4)) { | |
93d89f63 | 157 | pm_io_space_update((PIIX4PMState *)d); |
24fe083d GH |
158 | } |
159 | if (range_covers_byte(address, len, 0xd2) || | |
160 | ranges_overlap(address, len, 0x90, 4)) { | |
161 | smbus_io_space_update((PIIX4PMState *)d); | |
162 | } | |
93d89f63 IY |
163 | } |
164 | ||
165 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
166 | { | |
167 | PIIX4PMState *s = opaque; | |
168 | ||
169 | pm_io_space_update(s); | |
2b4e573c | 170 | smbus_io_space_update(s); |
93d89f63 IY |
171 | return 0; |
172 | } | |
173 | ||
23910d3f IY |
174 | #define VMSTATE_GPE_ARRAY(_field, _state) \ |
175 | { \ | |
176 | .name = (stringify(_field)), \ | |
177 | .version_id = 0, \ | |
23910d3f IY |
178 | .info = &vmstate_info_uint16, \ |
179 | .size = sizeof(uint16_t), \ | |
b0b873a0 | 180 | .flags = VMS_SINGLE | VMS_POINTER, \ |
23910d3f IY |
181 | .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ |
182 | } | |
183 | ||
4cf3e6f3 AW |
184 | static const VMStateDescription vmstate_gpe = { |
185 | .name = "gpe", | |
186 | .version_id = 1, | |
187 | .minimum_version_id = 1, | |
d49805ae | 188 | .fields = (VMStateField[]) { |
23910d3f IY |
189 | VMSTATE_GPE_ARRAY(sts, ACPIGPE), |
190 | VMSTATE_GPE_ARRAY(en, ACPIGPE), | |
4cf3e6f3 AW |
191 | VMSTATE_END_OF_LIST() |
192 | } | |
193 | }; | |
194 | ||
195 | static const VMStateDescription vmstate_pci_status = { | |
196 | .name = "pci_status", | |
197 | .version_id = 1, | |
198 | .minimum_version_id = 1, | |
d49805ae | 199 | .fields = (VMStateField[]) { |
e358edc8 IM |
200 | VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), |
201 | VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), | |
4cf3e6f3 AW |
202 | VMSTATE_END_OF_LIST() |
203 | } | |
204 | }; | |
205 | ||
b0b873a0 MT |
206 | static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) |
207 | { | |
208 | PIIX4PMState *s = opaque; | |
209 | int ret, i; | |
210 | uint16_t temp; | |
211 | ||
6a6b5580 | 212 | ret = pci_device_load(PCI_DEVICE(s), f); |
b0b873a0 MT |
213 | if (ret < 0) { |
214 | return ret; | |
215 | } | |
216 | qemu_get_be16s(f, &s->ar.pm1.evt.sts); | |
217 | qemu_get_be16s(f, &s->ar.pm1.evt.en); | |
218 | qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); | |
219 | ||
ded67782 | 220 | ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); |
b0b873a0 MT |
221 | if (ret) { |
222 | return ret; | |
223 | } | |
224 | ||
40daca54 | 225 | timer_get(f, s->ar.tmr.timer); |
b0b873a0 MT |
226 | qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); |
227 | ||
228 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); | |
229 | for (i = 0; i < 3; i++) { | |
230 | qemu_get_be16s(f, &temp); | |
231 | } | |
232 | ||
233 | qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); | |
234 | for (i = 0; i < 3; i++) { | |
235 | qemu_get_be16s(f, &temp); | |
236 | } | |
237 | ||
e358edc8 IM |
238 | ret = vmstate_load_state(f, &vmstate_pci_status, |
239 | &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); | |
b0b873a0 MT |
240 | return ret; |
241 | } | |
242 | ||
9e047b98 MT |
243 | static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) |
244 | { | |
245 | PIIX4PMState *s = opaque; | |
246 | return s->use_acpi_pci_hotplug; | |
247 | } | |
248 | ||
249 | static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id) | |
250 | { | |
251 | PIIX4PMState *s = opaque; | |
252 | return !s->use_acpi_pci_hotplug; | |
253 | } | |
254 | ||
f816a62d IM |
255 | static bool vmstate_test_use_memhp(void *opaque) |
256 | { | |
257 | PIIX4PMState *s = opaque; | |
258 | return s->acpi_memory_hotplug.is_enabled; | |
259 | } | |
260 | ||
261 | static const VMStateDescription vmstate_memhp_state = { | |
262 | .name = "piix4_pm/memhp", | |
263 | .version_id = 1, | |
264 | .minimum_version_id = 1, | |
265 | .minimum_version_id_old = 1, | |
5cd8cada | 266 | .needed = vmstate_test_use_memhp, |
f816a62d IM |
267 | .fields = (VMStateField[]) { |
268 | VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), | |
269 | VMSTATE_END_OF_LIST() | |
270 | } | |
271 | }; | |
272 | ||
679dd1a9 IM |
273 | static bool vmstate_test_use_cpuhp(void *opaque) |
274 | { | |
275 | PIIX4PMState *s = opaque; | |
276 | return !s->cpu_hotplug_legacy; | |
277 | } | |
278 | ||
279 | static int vmstate_cpuhp_pre_load(void *opaque) | |
280 | { | |
281 | Object *obj = OBJECT(opaque); | |
282 | object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); | |
283 | return 0; | |
284 | } | |
285 | ||
286 | static const VMStateDescription vmstate_cpuhp_state = { | |
287 | .name = "piix4_pm/cpuhp", | |
288 | .version_id = 1, | |
289 | .minimum_version_id = 1, | |
290 | .minimum_version_id_old = 1, | |
291 | .needed = vmstate_test_use_cpuhp, | |
292 | .pre_load = vmstate_cpuhp_pre_load, | |
293 | .fields = (VMStateField[]) { | |
294 | VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), | |
295 | VMSTATE_END_OF_LIST() | |
296 | } | |
297 | }; | |
298 | ||
4ab2f2a8 CM |
299 | static bool piix4_vmstate_need_smbus(void *opaque, int version_id) |
300 | { | |
301 | return pm_smbus_vmstate_needed(); | |
302 | } | |
303 | ||
b0b873a0 MT |
304 | /* qemu-kvm 1.2 uses version 3 but advertised as 2 |
305 | * To support incoming qemu-kvm 1.2 migration, change version_id | |
306 | * and minimum_version_id to 2 below (which breaks migration from | |
307 | * qemu 1.2). | |
308 | * | |
309 | */ | |
93d89f63 IY |
310 | static const VMStateDescription vmstate_acpi = { |
311 | .name = "piix4_pm", | |
b0b873a0 MT |
312 | .version_id = 3, |
313 | .minimum_version_id = 3, | |
93d89f63 | 314 | .minimum_version_id_old = 1, |
b0b873a0 | 315 | .load_state_old = acpi_load_old, |
93d89f63 | 316 | .post_load = vmstate_acpi_post_load, |
d49805ae | 317 | .fields = (VMStateField[]) { |
6a6b5580 | 318 | VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), |
355bf2e5 GH |
319 | VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), |
320 | VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), | |
321 | VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), | |
93d89f63 | 322 | VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
4ab2f2a8 CM |
323 | VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, |
324 | pmsmb_vmstate, PMSMBus), | |
e720677e | 325 | VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), |
355bf2e5 GH |
326 | VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), |
327 | VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), | |
e358edc8 IM |
328 | VMSTATE_STRUCT_TEST( |
329 | acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], | |
330 | PIIX4PMState, | |
331 | vmstate_test_no_use_acpi_pci_hotplug, | |
332 | 2, vmstate_pci_status, | |
333 | struct AcpiPciHpPciStatus), | |
9e047b98 MT |
334 | VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, |
335 | vmstate_test_use_acpi_pci_hotplug), | |
93d89f63 | 336 | VMSTATE_END_OF_LIST() |
f816a62d | 337 | }, |
5cd8cada JQ |
338 | .subsections = (const VMStateDescription*[]) { |
339 | &vmstate_memhp_state, | |
679dd1a9 | 340 | &vmstate_cpuhp_state, |
5cd8cada | 341 | NULL |
93d89f63 IY |
342 | } |
343 | }; | |
344 | ||
345 | static void piix4_reset(void *opaque) | |
346 | { | |
347 | PIIX4PMState *s = opaque; | |
6a6b5580 AF |
348 | PCIDevice *d = PCI_DEVICE(s); |
349 | uint8_t *pci_conf = d->config; | |
93d89f63 IY |
350 | |
351 | pci_conf[0x58] = 0; | |
352 | pci_conf[0x59] = 0; | |
353 | pci_conf[0x5a] = 0; | |
354 | pci_conf[0x5b] = 0; | |
355 | ||
4d09d37c GN |
356 | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
357 | pci_conf[0x80] = 0; | |
358 | ||
61e66c62 | 359 | if (!s->smm_enabled) { |
93d89f63 IY |
360 | /* Mark SMM as already inited (until KVM supports SMM). */ |
361 | pci_conf[0x5B] = 0x02; | |
362 | } | |
c046e8c4 | 363 | pm_io_space_update(s); |
e358edc8 | 364 | acpi_pcihp_reset(&s->acpi_pci_hotplug); |
93d89f63 IY |
365 | } |
366 | ||
d010f91c | 367 | static void piix4_pm_powerdown_req(Notifier *n, void *opaque) |
93d89f63 | 368 | { |
d010f91c | 369 | PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); |
93d89f63 | 370 | |
355bf2e5 GH |
371 | assert(s != NULL); |
372 | acpi_pm1_evt_power_down(&s->ar); | |
93d89f63 IY |
373 | } |
374 | ||
ec266f40 DH |
375 | static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
376 | DeviceState *dev, Error **errp) | |
377 | { | |
9040e6df WY |
378 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
379 | ||
ec266f40 DH |
380 | if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
381 | acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); | |
9040e6df WY |
382 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
383 | if (!s->acpi_memory_hotplug.is_enabled) { | |
384 | error_setg(errp, | |
385 | "memory hotplug is not enabled: %s.memory-hotplug-support " | |
386 | "is not set", object_get_typename(OBJECT(s))); | |
387 | } | |
388 | } else if ( | |
ec266f40 DH |
389 | !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
390 | error_setg(errp, "acpi: device pre plug request for not supported" | |
391 | " device type: %s", object_get_typename(OBJECT(dev))); | |
392 | } | |
393 | } | |
394 | ||
f1adc360 IM |
395 | static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, |
396 | DeviceState *dev, Error **errp) | |
9e047b98 | 397 | { |
c24d5e0b | 398 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
f1adc360 | 399 | |
9040e6df | 400 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
75f27498 XG |
401 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { |
402 | nvdimm_acpi_plug_cb(hotplug_dev, dev); | |
403 | } else { | |
404 | acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, | |
405 | dev, errp); | |
406 | } | |
34774320 | 407 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
2bed1ba7 | 408 | acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); |
5e1b5d93 IM |
409 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { |
410 | if (s->cpu_hotplug_legacy) { | |
411 | legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); | |
412 | } else { | |
413 | acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
414 | } | |
f1adc360 | 415 | } else { |
ec266f40 | 416 | g_assert_not_reached(); |
f1adc360 | 417 | } |
c24d5e0b | 418 | } |
9e047b98 | 419 | |
14d5a28f IM |
420 | static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
421 | DeviceState *dev, Error **errp) | |
c24d5e0b IM |
422 | { |
423 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); | |
f1adc360 | 424 | |
64fec58e TC |
425 | if (s->acpi_memory_hotplug.is_enabled && |
426 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
0058c082 | 427 | acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, |
64fec58e TC |
428 | dev, errp); |
429 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { | |
c97adf3c DH |
430 | acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, |
431 | dev, errp); | |
8872c25a IM |
432 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
433 | !s->cpu_hotplug_legacy) { | |
434 | acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); | |
f1adc360 IM |
435 | } else { |
436 | error_setg(errp, "acpi: device unplug request for not supported device" | |
437 | " type: %s", object_get_typename(OBJECT(dev))); | |
438 | } | |
9e047b98 MT |
439 | } |
440 | ||
c0e57a60 TC |
441 | static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, |
442 | DeviceState *dev, Error **errp) | |
443 | { | |
f7d3e29d TC |
444 | PIIX4PMState *s = PIIX4_PM(hotplug_dev); |
445 | ||
446 | if (s->acpi_memory_hotplug.is_enabled && | |
447 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
448 | acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); | |
c97adf3c DH |
449 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { |
450 | acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, | |
451 | errp); | |
8872c25a IM |
452 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && |
453 | !s->cpu_hotplug_legacy) { | |
454 | acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); | |
f7d3e29d TC |
455 | } else { |
456 | error_setg(errp, "acpi: device unplug for not supported device" | |
457 | " type: %s", object_get_typename(OBJECT(dev))); | |
458 | } | |
c0e57a60 TC |
459 | } |
460 | ||
9e8dd451 | 461 | static void piix4_pm_machine_ready(Notifier *n, void *opaque) |
6141dbfe PB |
462 | { |
463 | PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); | |
6a6b5580 AF |
464 | PCIDevice *d = PCI_DEVICE(s); |
465 | MemoryRegion *io_as = pci_address_space_io(d); | |
6141dbfe PB |
466 | uint8_t *pci_conf; |
467 | ||
6a6b5580 | 468 | pci_conf = d->config; |
b6f32962 | 469 | pci_conf[0x5f] = 0x10 | |
3ce10901 | 470 | (memory_region_present(io_as, 0x378) ? 0x80 : 0); |
6141dbfe | 471 | pci_conf[0x63] = 0x60; |
3ce10901 PB |
472 | pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | |
473 | (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); | |
6141dbfe PB |
474 | } |
475 | ||
277e9340 MT |
476 | static void piix4_pm_add_propeties(PIIX4PMState *s) |
477 | { | |
478 | static const uint8_t acpi_enable_cmd = ACPI_ENABLE; | |
479 | static const uint8_t acpi_disable_cmd = ACPI_DISABLE; | |
480 | static const uint32_t gpe0_blk = GPE_BASE; | |
481 | static const uint32_t gpe0_blk_len = GPE_LEN; | |
482 | static const uint16_t sci_int = 9; | |
483 | ||
484 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, | |
485 | &acpi_enable_cmd, NULL); | |
486 | object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, | |
487 | &acpi_disable_cmd, NULL); | |
488 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, | |
489 | &gpe0_blk, NULL); | |
490 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, | |
491 | &gpe0_blk_len, NULL); | |
492 | object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, | |
493 | &sci_int, NULL); | |
494 | object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, | |
495 | &s->io_base, NULL); | |
496 | } | |
497 | ||
9af21dbe | 498 | static void piix4_pm_realize(PCIDevice *dev, Error **errp) |
93d89f63 | 499 | { |
74e445f6 | 500 | PIIX4PMState *s = PIIX4_PM(dev); |
93d89f63 IY |
501 | uint8_t *pci_conf; |
502 | ||
6a6b5580 | 503 | pci_conf = dev->config; |
93d89f63 IY |
504 | pci_conf[0x06] = 0x80; |
505 | pci_conf[0x07] = 0x02; | |
93d89f63 | 506 | pci_conf[0x09] = 0x00; |
93d89f63 IY |
507 | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
508 | ||
93d89f63 | 509 | /* APM */ |
42d8a3cf | 510 | apm_init(dev, &s->apm, apm_ctrl_changed, s); |
93d89f63 | 511 | |
61e66c62 | 512 | if (!s->smm_enabled) { |
93d89f63 IY |
513 | /* Mark SMM as already inited to prevent SMM from running. KVM does not |
514 | * support SMM mode. */ | |
515 | pci_conf[0x5B] = 0x02; | |
516 | } | |
517 | ||
518 | /* XXX: which specification is used ? The i82731AB has different | |
519 | mappings */ | |
e8ec0571 IY |
520 | pci_conf[0x90] = s->smb_io_base | 1; |
521 | pci_conf[0x91] = s->smb_io_base >> 8; | |
93d89f63 | 522 | pci_conf[0xd2] = 0x09; |
45726b6e | 523 | pm_smbus_init(DEVICE(dev), &s->smb, true); |
24fe083d | 524 | memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); |
56e5b2a1 GH |
525 | memory_region_add_subregion(pci_address_space_io(dev), |
526 | s->smb_io_base, &s->smb.io); | |
93d89f63 | 527 | |
64bde0f3 | 528 | memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); |
af11110b | 529 | memory_region_set_enabled(&s->io, false); |
56e5b2a1 GH |
530 | memory_region_add_subregion(pci_address_space_io(dev), |
531 | 0, &s->io); | |
93d89f63 | 532 | |
77d58b1e | 533 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 534 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
9a10bbb4 | 535 | acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); |
355bf2e5 | 536 | acpi_gpe_init(&s->ar, GPE_LEN); |
93d89f63 | 537 | |
d010f91c IM |
538 | s->powerdown_notifier.notify = piix4_pm_powerdown_req; |
539 | qemu_register_powerdown_notifier(&s->powerdown_notifier); | |
93d89f63 | 540 | |
6141dbfe PB |
541 | s->machine_ready.notify = piix4_pm_machine_ready; |
542 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
e8ec0571 | 543 | qemu_register_reset(piix4_reset, s); |
56e5b2a1 | 544 | |
fd56e061 DG |
545 | piix4_acpi_system_hot_add_init(pci_address_space_io(dev), |
546 | pci_get_bus(dev), s); | |
94d1cc5f | 547 | qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort); |
e8ec0571 | 548 | |
277e9340 | 549 | piix4_pm_add_propeties(s); |
e8ec0571 IY |
550 | } |
551 | ||
a5c82852 AF |
552 | I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
553 | qemu_irq sci_irq, qemu_irq smi_irq, | |
61e66c62 | 554 | int smm_enabled, DeviceState **piix4_pm) |
e8ec0571 | 555 | { |
74e445f6 | 556 | DeviceState *dev; |
e8ec0571 IY |
557 | PIIX4PMState *s; |
558 | ||
74e445f6 PC |
559 | dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM)); |
560 | qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); | |
781bbd6b IM |
561 | if (piix4_pm) { |
562 | *piix4_pm = dev; | |
563 | } | |
93d89f63 | 564 | |
74e445f6 | 565 | s = PIIX4_PM(dev); |
93d89f63 | 566 | s->irq = sci_irq; |
93d89f63 | 567 | s->smi_irq = smi_irq; |
61e66c62 | 568 | s->smm_enabled = smm_enabled; |
91ab2ed7 IM |
569 | if (xen_enabled()) { |
570 | s->use_acpi_pci_hotplug = false; | |
571 | } | |
e8ec0571 | 572 | |
74e445f6 | 573 | qdev_init_nofail(dev); |
93d89f63 IY |
574 | |
575 | return s->smb.smbus; | |
576 | } | |
577 | ||
b65b93f2 | 578 | static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) |
93d89f63 | 579 | { |
633aa0ac | 580 | PIIX4PMState *s = opaque; |
355bf2e5 | 581 | uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); |
93d89f63 | 582 | |
b37d56ec | 583 | trace_piix4_gpe_readb(addr, width, val); |
93d89f63 IY |
584 | return val; |
585 | } | |
586 | ||
b65b93f2 GH |
587 | static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, |
588 | unsigned width) | |
93d89f63 | 589 | { |
633aa0ac | 590 | PIIX4PMState *s = opaque; |
633aa0ac | 591 | |
b37d56ec | 592 | trace_piix4_gpe_writeb(addr, width, val); |
355bf2e5 | 593 | acpi_gpe_ioport_writeb(&s->ar, addr, val); |
06313503 | 594 | acpi_update_sci(&s->ar, s->irq); |
93d89f63 IY |
595 | } |
596 | ||
b65b93f2 GH |
597 | static const MemoryRegionOps piix4_gpe_ops = { |
598 | .read = gpe_readb, | |
599 | .write = gpe_writeb, | |
600 | .valid.min_access_size = 1, | |
601 | .valid.max_access_size = 4, | |
602 | .impl.min_access_size = 1, | |
603 | .impl.max_access_size = 1, | |
604 | .endianness = DEVICE_LITTLE_ENDIAN, | |
605 | }; | |
606 | ||
16bcab97 IM |
607 | |
608 | static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) | |
609 | { | |
610 | PIIX4PMState *s = PIIX4_PM(obj); | |
611 | ||
612 | return s->cpu_hotplug_legacy; | |
613 | } | |
614 | ||
615 | static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) | |
616 | { | |
617 | PIIX4PMState *s = PIIX4_PM(obj); | |
618 | ||
679dd1a9 IM |
619 | assert(!value); |
620 | if (s->cpu_hotplug_legacy && value == false) { | |
621 | acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, | |
622 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
623 | } | |
16bcab97 IM |
624 | s->cpu_hotplug_legacy = value; |
625 | } | |
626 | ||
56e5b2a1 GH |
627 | static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, |
628 | PCIBus *bus, PIIX4PMState *s) | |
93d89f63 | 629 | { |
64bde0f3 PB |
630 | memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, |
631 | "acpi-gpe0", GPE_LEN); | |
56e5b2a1 | 632 | memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); |
ac404095 | 633 | |
78c2d872 | 634 | acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, |
e358edc8 | 635 | s->use_acpi_pci_hotplug); |
b8622725 | 636 | |
16bcab97 IM |
637 | s->cpu_hotplug_legacy = true; |
638 | object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", | |
639 | piix4_get_cpu_hotplug_legacy, | |
640 | piix4_set_cpu_hotplug_legacy, | |
641 | NULL); | |
96e3e12b IM |
642 | legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, |
643 | PIIX4_CPU_HOTPLUG_IO_BASE); | |
34774320 IM |
644 | |
645 | if (s->acpi_memory_hotplug.is_enabled) { | |
80db0e78 IM |
646 | acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, |
647 | ACPI_MEMORY_HOTPLUG_BASE); | |
34774320 | 648 | } |
93d89f63 | 649 | } |
5fdae20c | 650 | |
43f50410 IM |
651 | static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) |
652 | { | |
653 | PIIX4PMState *s = PIIX4_PM(adev); | |
654 | ||
655 | acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); | |
76623d00 IM |
656 | if (!s->cpu_hotplug_legacy) { |
657 | acpi_cpu_ospm_status(&s->cpuhp_state, list); | |
658 | } | |
43f50410 IM |
659 | } |
660 | ||
eaf23bf7 IM |
661 | static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) |
662 | { | |
663 | PIIX4PMState *s = PIIX4_PM(adev); | |
664 | ||
665 | acpi_send_gpe_event(&s->ar, s->irq, ev); | |
666 | } | |
667 | ||
5fdae20c IM |
668 | static Property piix4_pm_properties[] = { |
669 | DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), | |
670 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), | |
671 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), | |
672 | DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), | |
673 | DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, | |
674 | use_acpi_pci_hotplug, true), | |
34774320 IM |
675 | DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, |
676 | acpi_memory_hotplug.is_enabled, true), | |
5fdae20c IM |
677 | DEFINE_PROP_END_OF_LIST(), |
678 | }; | |
679 | ||
680 | static void piix4_pm_class_init(ObjectClass *klass, void *data) | |
681 | { | |
682 | DeviceClass *dc = DEVICE_CLASS(klass); | |
683 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
c24d5e0b | 684 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
43f50410 | 685 | AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); |
5fdae20c | 686 | |
9af21dbe | 687 | k->realize = piix4_pm_realize; |
5fdae20c IM |
688 | k->config_write = pm_write_config; |
689 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
690 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; | |
691 | k->revision = 0x03; | |
692 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
693 | dc->desc = "PM"; | |
694 | dc->vmsd = &vmstate_acpi; | |
695 | dc->props = piix4_pm_properties; | |
696 | /* | |
697 | * Reason: part of PIIX4 southbridge, needs to be wired up, | |
698 | * e.g. by mips_malta_init() | |
699 | */ | |
e90f2a8c | 700 | dc->user_creatable = false; |
2897ae02 | 701 | dc->hotpluggable = false; |
ec266f40 | 702 | hc->pre_plug = piix4_device_pre_plug_cb; |
f1adc360 | 703 | hc->plug = piix4_device_plug_cb; |
14d5a28f | 704 | hc->unplug_request = piix4_device_unplug_request_cb; |
c0e57a60 | 705 | hc->unplug = piix4_device_unplug_cb; |
43f50410 | 706 | adevc->ospm_status = piix4_ospm_status; |
eaf23bf7 | 707 | adevc->send_event = piix4_send_gpe; |
ac35f13b | 708 | adevc->madt_cpu = pc_madt_cpu_entry; |
5fdae20c IM |
709 | } |
710 | ||
711 | static const TypeInfo piix4_pm_info = { | |
712 | .name = TYPE_PIIX4_PM, | |
713 | .parent = TYPE_PCI_DEVICE, | |
714 | .instance_size = sizeof(PIIX4PMState), | |
715 | .class_init = piix4_pm_class_init, | |
c24d5e0b IM |
716 | .interfaces = (InterfaceInfo[]) { |
717 | { TYPE_HOTPLUG_HANDLER }, | |
43f50410 | 718 | { TYPE_ACPI_DEVICE_IF }, |
fd3b02c8 | 719 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
c24d5e0b IM |
720 | { } |
721 | } | |
5fdae20c IM |
722 | }; |
723 | ||
724 | static void piix4_pm_register_types(void) | |
725 | { | |
726 | type_register_static(&piix4_pm_info); | |
727 | } | |
728 | ||
729 | type_init(piix4_pm_register_types) |