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[thirdparty/qemu.git] / hw / arm / exynos4_boards.c
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1/*
2 * Samsung exynos4 SoC based boards emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
5 * Maksim Kozlov <m.kozlov@samsung.com>
6 * Evgeny Voevodin <e.voevodin@samsung.com>
7 * Igor Mitsyanko <i.mitsyanko@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
12b16722 24#include "qemu/osdep.h"
e12a0dd2 25#include "qemu/units.h"
a2f2f624 26#include "qapi/error.h"
f2ad5140 27#include "qemu/error-report.h"
4771d756 28#include "cpu.h"
9c17d615 29#include "sysemu/sysemu.h"
83c9f4ca 30#include "hw/sysbus.h"
1422e32d 31#include "net/net.h"
12ec8bd5 32#include "hw/arm/boot.h"
022c62cb 33#include "exec/address-spaces.h"
0d09e41a 34#include "hw/arm/exynos4210.h"
94630665 35#include "hw/net/lan9118.h"
a27bd6c7 36#include "hw/qdev-properties.h"
83c9f4ca 37#include "hw/boards.h"
64552b6b 38#include "hw/irq.h"
0caa7113 39
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40#define SMDK_LAN9118_BASE_ADDR 0x05000000
41
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42typedef enum Exynos4BoardType {
43 EXYNOS4_BOARD_NURI,
44 EXYNOS4_BOARD_SMDKC210,
45 EXYNOS4_NUM_OF_BOARDS
46} Exynos4BoardType;
47
a2f2f624 48typedef struct Exynos4BoardState {
98e4f4fd 49 Exynos4210State soc;
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50 MemoryRegion dram0_mem;
51 MemoryRegion dram1_mem;
52} Exynos4BoardState;
53
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54static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
55 [EXYNOS4_BOARD_NURI] = 0xD33,
56 [EXYNOS4_BOARD_SMDKC210] = 0xB16,
57};
58
59static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
60 [EXYNOS4_BOARD_NURI] = EXYNOS4210_SECOND_CPU_BOOTREG,
61 [EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
62};
63
64static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
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65 [EXYNOS4_BOARD_NURI] = 1 * GiB,
66 [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
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67};
68
69static struct arm_boot_info exynos4_board_binfo = {
70 .loader_start = EXYNOS4210_BASE_BOOT_ADDR,
71 .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
72 .nb_cpus = EXYNOS4210_NCPUS,
3f088e36 73 .write_secondary_boot = exynos4210_write_secondary,
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74};
75
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76static void lan9215_init(uint32_t base, qemu_irq irq)
77{
78 DeviceState *dev;
79 SysBusDevice *s;
80
81 /* This should be a 9215 but the 9118 is close enough */
a005d073 82 if (nd_table[0].used) {
2c2c6496 83 qemu_check_nic_model(&nd_table[0], "lan9118");
3e80f690 84 dev = qdev_new(TYPE_LAN9118);
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85 qdev_set_nic_properties(dev, &nd_table[0]);
86 qdev_prop_set_uint32(dev, "mode_16bit", 1);
1356b98d 87 s = SYS_BUS_DEVICE(dev);
3c6ef471 88 sysbus_realize_and_unref(s, &error_fatal);
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89 sysbus_mmio_map(s, 0, base);
90 sysbus_connect_irq(s, 0, irq);
91 }
92}
93
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94static void exynos4_boards_init_ram(Exynos4BoardState *s,
95 MemoryRegion *system_mem,
96 unsigned long ram_size)
97{
98 unsigned long mem_size = ram_size;
99
100 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
98a99ce0 101 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
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102 mem_size - EXYNOS4210_DRAM_MAX_SIZE,
103 &error_fatal);
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104 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
105 &s->dram1_mem);
106 mem_size = EXYNOS4210_DRAM_MAX_SIZE;
107 }
108
98a99ce0 109 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
a2f2f624 110 &error_fatal);
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111 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
112 &s->dram0_mem);
113}
114
115static Exynos4BoardState *
116exynos4_boards_init_common(MachineState *machine,
117 Exynos4BoardType board_type)
0caa7113 118{
a2f2f624 119 Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
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120
121 exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
122 exynos4_board_binfo.board_id = exynos4_board_id[board_type];
123 exynos4_board_binfo.smp_bootreg_addr =
124 exynos4_board_smp_bootreg_addr[board_type];
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125 exynos4_board_binfo.gic_cpu_if_addr =
126 EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
0caa7113 127
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128 exynos4_boards_init_ram(s, get_system_memory(),
129 exynos4_board_ram_size[board_type]);
130
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131 sysbus_init_child_obj(OBJECT(machine), "soc",
132 &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
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133 object_property_set_bool(OBJECT(&s->soc), true, "realized",
134 &error_fatal);
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135
136 return s;
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137}
138
3ef96221 139static void nuri_init(MachineState *machine)
0caa7113 140{
3ef96221 141 exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
0caa7113 142
2744ece8 143 arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
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144}
145
3ef96221 146static void smdkc210_init(MachineState *machine)
0caa7113 147{
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148 Exynos4BoardState *s = exynos4_boards_init_common(machine,
149 EXYNOS4_BOARD_SMDKC210);
0caa7113 150
2c2c6496 151 lan9215_init(SMDK_LAN9118_BASE_ADDR,
98e4f4fd 152 qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
2744ece8 153 arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
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154}
155
8a661aea 156static void nuri_class_init(ObjectClass *oc, void *data)
e264d29d 157{
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158 MachineClass *mc = MACHINE_CLASS(oc);
159
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160 mc->desc = "Samsung NURI board (Exynos4210)";
161 mc->init = nuri_init;
162 mc->max_cpus = EXYNOS4210_NCPUS;
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163 mc->min_cpus = EXYNOS4210_NCPUS;
164 mc->default_cpus = EXYNOS4210_NCPUS;
4672cbd7 165 mc->ignore_memory_transaction_failures = true;
e264d29d 166}
97c6671c 167
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168static const TypeInfo nuri_type = {
169 .name = MACHINE_TYPE_NAME("nuri"),
170 .parent = TYPE_MACHINE,
171 .class_init = nuri_class_init,
172};
0caa7113 173
8a661aea 174static void smdkc210_class_init(ObjectClass *oc, void *data)
0caa7113 175{
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176 MachineClass *mc = MACHINE_CLASS(oc);
177
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178 mc->desc = "Samsung SMDKC210 board (Exynos4210)";
179 mc->init = smdkc210_init;
180 mc->max_cpus = EXYNOS4210_NCPUS;
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181 mc->min_cpus = EXYNOS4210_NCPUS;
182 mc->default_cpus = EXYNOS4210_NCPUS;
4672cbd7 183 mc->ignore_memory_transaction_failures = true;
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184}
185
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186static const TypeInfo smdkc210_type = {
187 .name = MACHINE_TYPE_NAME("smdkc210"),
188 .parent = TYPE_MACHINE,
189 .class_init = smdkc210_class_init,
190};
191
192static void exynos4_machines_init(void)
193{
194 type_register_static(&nuri_type);
195 type_register_static(&smdkc210_type);
196}
197
0e6aac87 198type_init(exynos4_machines_init)