[thirdparty/qemu.git] / hw / arm / exynos4_boards.c

/*
 *  Samsung exynos4 SoC based boards emulation
 *
 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
 *    Maksim Kozlov <m.kozlov@samsung.com>
 *    Evgeny Voevodin <e.voevodin@samsung.com>
 *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "cpu.h"
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/arm/boot.h"
#include "exec/address-spaces.h"
#include "hw/arm/exynos4210.h"
#include "hw/net/lan9118.h"
#include "hw/boards.h"
#include "hw/irq.h"

#define SMDK_LAN9118_BASE_ADDR      0x05000000

typedef enum Exynos4BoardType {
    EXYNOS4_BOARD_NURI,
    EXYNOS4_BOARD_SMDKC210,
    EXYNOS4_NUM_OF_BOARDS
} Exynos4BoardType;

typedef struct Exynos4BoardState {
    Exynos4210State soc;
    MemoryRegion dram0_mem;
    MemoryRegion dram1_mem;
} Exynos4BoardState;

static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
    [EXYNOS4_BOARD_NURI]     = 0xD33,
    [EXYNOS4_BOARD_SMDKC210] = 0xB16,
};

static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
    [EXYNOS4_BOARD_NURI]     = EXYNOS4210_SECOND_CPU_BOOTREG,
    [EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
};

static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
};

static struct arm_boot_info exynos4_board_binfo = {
    .loader_start     = EXYNOS4210_BASE_BOOT_ADDR,
    .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
    .nb_cpus          = EXYNOS4210_NCPUS,
    .write_secondary_boot = exynos4210_write_secondary,
};

static void lan9215_init(uint32_t base, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *s;

    /* This should be a 9215 but the 9118 is close enough */
    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], "lan9118");
        dev = qdev_create(NULL, TYPE_LAN9118);
        qdev_set_nic_properties(dev, &nd_table[0]);
        qdev_prop_set_uint32(dev, "mode_16bit", 1);
        qdev_init_nofail(dev);
        s = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(s, 0, base);
        sysbus_connect_irq(s, 0, irq);
    }
}

static void exynos4_boards_init_ram(Exynos4BoardState *s,
                                    MemoryRegion *system_mem,
                                    unsigned long ram_size)
{
    unsigned long mem_size = ram_size;

    if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
        memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
                               mem_size - EXYNOS4210_DRAM_MAX_SIZE,
                               &error_fatal);
        memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
                                    &s->dram1_mem);
        mem_size = EXYNOS4210_DRAM_MAX_SIZE;
    }

    memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
                           &error_fatal);
    memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
                                &s->dram0_mem);
}

static Exynos4BoardState *
exynos4_boards_init_common(MachineState *machine,
                           Exynos4BoardType board_type)
{
    Exynos4BoardState *s = g_new(Exynos4BoardState, 1);

    exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
    exynos4_board_binfo.board_id = exynos4_board_id[board_type];
    exynos4_board_binfo.smp_bootreg_addr =
            exynos4_board_smp_bootreg_addr[board_type];
    exynos4_board_binfo.kernel_filename = machine->kernel_filename;
    exynos4_board_binfo.initrd_filename = machine->initrd_filename;
    exynos4_board_binfo.kernel_cmdline = machine->kernel_cmdline;
    exynos4_board_binfo.gic_cpu_if_addr =
            EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;

    exynos4_boards_init_ram(s, get_system_memory(),
                            exynos4_board_ram_size[board_type]);

    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                             &error_fatal);

    return s;
}

static void nuri_init(MachineState *machine)
{
    exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);

    arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
}

static void smdkc210_init(MachineState *machine)
{
    Exynos4BoardState *s = exynos4_boards_init_common(machine,
                                                      EXYNOS4_BOARD_SMDKC210);

    lan9215_init(SMDK_LAN9118_BASE_ADDR,
            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
    arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
}

static void nuri_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Samsung NURI board (Exynos4210)";
    mc->init = nuri_init;
    mc->max_cpus = EXYNOS4210_NCPUS;
    mc->min_cpus = EXYNOS4210_NCPUS;
    mc->default_cpus = EXYNOS4210_NCPUS;
    mc->ignore_memory_transaction_failures = true;
}

static const TypeInfo nuri_type = {
    .name = MACHINE_TYPE_NAME("nuri"),
    .parent = TYPE_MACHINE,
    .class_init = nuri_class_init,
};

static void smdkc210_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Samsung SMDKC210 board (Exynos4210)";
    mc->init = smdkc210_init;
    mc->max_cpus = EXYNOS4210_NCPUS;
    mc->min_cpus = EXYNOS4210_NCPUS;
    mc->default_cpus = EXYNOS4210_NCPUS;
    mc->ignore_memory_transaction_failures = true;
}

static const TypeInfo smdkc210_type = {
    .name = MACHINE_TYPE_NAME("smdkc210"),
    .parent = TYPE_MACHINE,
    .class_init = smdkc210_class_init,
};

static void exynos4_machines_init(void)
{
    type_register_static(&nuri_type);
    type_register_static(&smdkc210_type);
}

type_init(exynos4_machines_init)
Commit	Line	Data
0caa7113 EV	1	/*
	2	* Samsung exynos4 SoC based boards emulation
	3	*
	4	* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
	5	* Maksim Kozlov <m.kozlov@samsung.com>
	6	* Evgeny Voevodin <e.voevodin@samsung.com>
	7	* Igor Mitsyanko <i.mitsyanko@samsung.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	17	* for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*
	22	*/
	23
12b16722	24	#include "qemu/osdep.h"
e12a0dd2	25	#include "qemu/units.h"
a2f2f624	26	#include "qapi/error.h"
f2ad5140	27	#include "qemu/error-report.h"
4771d756	28	#include "cpu.h"
9c17d615	29	#include "sysemu/sysemu.h"
83c9f4ca	30	#include "hw/sysbus.h"
1422e32d	31	#include "net/net.h"
12ec8bd5	32	#include "hw/arm/boot.h"
022c62cb	33	#include "exec/address-spaces.h"
0d09e41a	34	#include "hw/arm/exynos4210.h"
94630665	35	#include "hw/net/lan9118.h"
83c9f4ca	36	#include "hw/boards.h"
64552b6b	37	#include "hw/irq.h"
0caa7113	38
2c2c6496 EV	39	#define SMDK_LAN9118_BASE_ADDR 0x05000000
2c2c6496 EV	40
0caa7113 EV	41	typedef enum Exynos4BoardType {
	42	EXYNOS4_BOARD_NURI,
	43	EXYNOS4_BOARD_SMDKC210,
	44	EXYNOS4_NUM_OF_BOARDS
	45	} Exynos4BoardType;
	46
a2f2f624	47	typedef struct Exynos4BoardState {
98e4f4fd	48	Exynos4210State soc;
a2f2f624 KK	49	MemoryRegion dram0_mem;
	50	MemoryRegion dram1_mem;
	51	} Exynos4BoardState;
	52
0caa7113 EV	53	static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
	54	[EXYNOS4_BOARD_NURI] = 0xD33,
	55	[EXYNOS4_BOARD_SMDKC210] = 0xB16,
	56	};
	57
	58	static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
	59	[EXYNOS4_BOARD_NURI] = EXYNOS4210_SECOND_CPU_BOOTREG,
	60	[EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
	61	};
	62
	63	static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
e12a0dd2 PMD	64	[EXYNOS4_BOARD_NURI] = 1 * GiB,
e12a0dd2 PMD	65	[EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
0caa7113 EV	66	};
	67
	68	static struct arm_boot_info exynos4_board_binfo = {
	69	.loader_start = EXYNOS4210_BASE_BOOT_ADDR,
	70	.smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
	71	.nb_cpus = EXYNOS4210_NCPUS,
3f088e36	72	.write_secondary_boot = exynos4210_write_secondary,
0caa7113 EV	73	};
0caa7113 EV	74
2c2c6496 EV	75	static void lan9215_init(uint32_t base, qemu_irq irq)
	76	{
	77	DeviceState *dev;
	78	SysBusDevice *s;
	79
	80	/* This should be a 9215 but the 9118 is close enough */
a005d073	81	if (nd_table[0].used) {
2c2c6496	82	qemu_check_nic_model(&nd_table[0], "lan9118");
94630665	83	dev = qdev_create(NULL, TYPE_LAN9118);
2c2c6496 EV	84	qdev_set_nic_properties(dev, &nd_table[0]);
	85	qdev_prop_set_uint32(dev, "mode_16bit", 1);
	86	qdev_init_nofail(dev);
1356b98d	87	s = SYS_BUS_DEVICE(dev);
2c2c6496 EV	88	sysbus_mmio_map(s, 0, base);
	89	sysbus_connect_irq(s, 0, irq);
	90	}
	91	}
	92
a2f2f624 KK	93	static void exynos4_boards_init_ram(Exynos4BoardState *s,
	94	MemoryRegion *system_mem,
	95	unsigned long ram_size)
	96	{
	97	unsigned long mem_size = ram_size;
	98
	99	if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
98a99ce0	100	memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
a2f2f624 KK	101	mem_size - EXYNOS4210_DRAM_MAX_SIZE,
a2f2f624 KK	102	&error_fatal);
a2f2f624 KK	103	memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
	104	&s->dram1_mem);
	105	mem_size = EXYNOS4210_DRAM_MAX_SIZE;
	106	}
	107
98a99ce0	108	memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
a2f2f624	109	&error_fatal);
a2f2f624 KK	110	memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
	111	&s->dram0_mem);
	112	}
	113
	114	static Exynos4BoardState *
	115	exynos4_boards_init_common(MachineState *machine,
	116	Exynos4BoardType board_type)
0caa7113	117	{
a2f2f624	118	Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
0caa7113 EV	119
	120	exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
	121	exynos4_board_binfo.board_id = exynos4_board_id[board_type];
	122	exynos4_board_binfo.smp_bootreg_addr =
	123	exynos4_board_smp_bootreg_addr[board_type];
3ef96221 MA	124	exynos4_board_binfo.kernel_filename = machine->kernel_filename;
	125	exynos4_board_binfo.initrd_filename = machine->initrd_filename;
	126	exynos4_board_binfo.kernel_cmdline = machine->kernel_cmdline;
96eacf64 PM	127	exynos4_board_binfo.gic_cpu_if_addr =
96eacf64 PM	128	EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
0caa7113	129
a2f2f624 KK	130	exynos4_boards_init_ram(s, get_system_memory(),
	131	exynos4_board_ram_size[board_type]);
	132
98e4f4fd PMD	133	object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
	134	qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
	135	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	136	&error_fatal);
a2f2f624 KK	137
a2f2f624 KK	138	return s;
0caa7113 EV	139	}
0caa7113 EV	140
3ef96221	141	static void nuri_init(MachineState *machine)
0caa7113	142	{
3ef96221	143	exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
0caa7113	144
182735ef	145	arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
0caa7113 EV	146	}
0caa7113 EV	147
3ef96221	148	static void smdkc210_init(MachineState *machine)
0caa7113	149	{
a2f2f624 KK	150	Exynos4BoardState *s = exynos4_boards_init_common(machine,
a2f2f624 KK	151	EXYNOS4_BOARD_SMDKC210);
0caa7113	152
2c2c6496	153	lan9215_init(SMDK_LAN9118_BASE_ADDR,
98e4f4fd	154	qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
182735ef	155	arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
0caa7113 EV	156	}
0caa7113 EV	157
8a661aea	158	static void nuri_class_init(ObjectClass oc, void data)
e264d29d	159	{
8a661aea AF	160	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	161
e264d29d EH	162	mc->desc = "Samsung NURI board (Exynos4210)";
	163	mc->init = nuri_init;
	164	mc->max_cpus = EXYNOS4210_NCPUS;
72649619 EC	165	mc->min_cpus = EXYNOS4210_NCPUS;
72649619 EC	166	mc->default_cpus = EXYNOS4210_NCPUS;
4672cbd7	167	mc->ignore_memory_transaction_failures = true;
e264d29d	168	}
97c6671c	169
8a661aea AF	170	static const TypeInfo nuri_type = {
	171	.name = MACHINE_TYPE_NAME("nuri"),
	172	.parent = TYPE_MACHINE,
	173	.class_init = nuri_class_init,
	174	};
0caa7113	175
8a661aea	176	static void smdkc210_class_init(ObjectClass oc, void data)
0caa7113	177	{
8a661aea AF	178	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	179
e264d29d EH	180	mc->desc = "Samsung SMDKC210 board (Exynos4210)";
	181	mc->init = smdkc210_init;
	182	mc->max_cpus = EXYNOS4210_NCPUS;
72649619 EC	183	mc->min_cpus = EXYNOS4210_NCPUS;
72649619 EC	184	mc->default_cpus = EXYNOS4210_NCPUS;
4672cbd7	185	mc->ignore_memory_transaction_failures = true;
0caa7113 EV	186	}
0caa7113 EV	187
8a661aea AF	188	static const TypeInfo smdkc210_type = {
	189	.name = MACHINE_TYPE_NAME("smdkc210"),
	190	.parent = TYPE_MACHINE,
	191	.class_init = smdkc210_class_init,
	192	};
	193
	194	static void exynos4_machines_init(void)
	195	{
	196	type_register_static(&nuri_type);
	197	type_register_static(&smdkc210_type);
	198	}
	199
0e6aac87	200	type_init(exynos4_machines_init)