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Commit | Line | Data |
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24859b68 AZ |
1 | /* |
2 | * Marvell MV88W8618 / Freecom MusicPal emulation. | |
3 | * | |
4 | * Copyright (c) 2008 Jan Kiszka | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU GPL v2. |
6b620ca3 PB |
7 | * |
8 | * Contributions after 2012-01-13 are licensed under the terms of the | |
9 | * GNU GPL, version 2 or (at your option) any later version. | |
24859b68 AZ |
10 | */ |
11 | ||
12b16722 | 12 | #include "qemu/osdep.h" |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 | 14 | #include "cpu.h" |
83c9f4ca | 15 | #include "hw/sysbus.h" |
d6454270 | 16 | #include "migration/vmstate.h" |
12ec8bd5 | 17 | #include "hw/arm/boot.h" |
1422e32d | 18 | #include "net/net.h" |
9c17d615 | 19 | #include "sysemu/sysemu.h" |
83c9f4ca | 20 | #include "hw/boards.h" |
0d09e41a | 21 | #include "hw/char/serial.h" |
650d103d | 22 | #include "hw/hw.h" |
1de7afc9 | 23 | #include "qemu/timer.h" |
83c9f4ca | 24 | #include "hw/ptimer.h" |
0d09e41a | 25 | #include "hw/block/flash.h" |
28ecbaee | 26 | #include "ui/console.h" |
0d09e41a | 27 | #include "hw/i2c/i2c.h" |
64552b6b | 28 | #include "hw/irq.h" |
7ab14c5a | 29 | #include "hw/audio/wm8750.h" |
fa1d36df | 30 | #include "sysemu/block-backend.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
28ecbaee | 32 | #include "ui/pixel_ops.h" |
24859b68 | 33 | |
718ec0be | 34 | #define MP_MISC_BASE 0x80002000 |
35 | #define MP_MISC_SIZE 0x00001000 | |
36 | ||
24859b68 AZ |
37 | #define MP_ETH_BASE 0x80008000 |
38 | #define MP_ETH_SIZE 0x00001000 | |
39 | ||
718ec0be | 40 | #define MP_WLAN_BASE 0x8000C000 |
41 | #define MP_WLAN_SIZE 0x00000800 | |
42 | ||
24859b68 AZ |
43 | #define MP_UART1_BASE 0x8000C840 |
44 | #define MP_UART2_BASE 0x8000C940 | |
45 | ||
718ec0be | 46 | #define MP_GPIO_BASE 0x8000D000 |
47 | #define MP_GPIO_SIZE 0x00001000 | |
48 | ||
24859b68 AZ |
49 | #define MP_FLASHCFG_BASE 0x90006000 |
50 | #define MP_FLASHCFG_SIZE 0x00001000 | |
51 | ||
52 | #define MP_AUDIO_BASE 0x90007000 | |
24859b68 AZ |
53 | |
54 | #define MP_PIC_BASE 0x90008000 | |
55 | #define MP_PIC_SIZE 0x00001000 | |
56 | ||
57 | #define MP_PIT_BASE 0x90009000 | |
58 | #define MP_PIT_SIZE 0x00001000 | |
59 | ||
60 | #define MP_LCD_BASE 0x9000c000 | |
61 | #define MP_LCD_SIZE 0x00001000 | |
62 | ||
63 | #define MP_SRAM_BASE 0xC0000000 | |
64 | #define MP_SRAM_SIZE 0x00020000 | |
65 | ||
66 | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 | |
67 | #define MP_FLASH_SIZE_MAX 32*1024*1024 | |
68 | ||
69 | #define MP_TIMER1_IRQ 4 | |
b47b50fa PB |
70 | #define MP_TIMER2_IRQ 5 |
71 | #define MP_TIMER3_IRQ 6 | |
24859b68 AZ |
72 | #define MP_TIMER4_IRQ 7 |
73 | #define MP_EHCI_IRQ 8 | |
74 | #define MP_ETH_IRQ 9 | |
75 | #define MP_UART1_IRQ 11 | |
76 | #define MP_UART2_IRQ 11 | |
77 | #define MP_GPIO_IRQ 12 | |
78 | #define MP_RTC_IRQ 28 | |
79 | #define MP_AUDIO_IRQ 30 | |
80 | ||
24859b68 | 81 | /* Wolfson 8750 I2C address */ |
64258229 | 82 | #define MP_WM_ADDR 0x1A |
24859b68 | 83 | |
24859b68 AZ |
84 | /* Ethernet register offsets */ |
85 | #define MP_ETH_SMIR 0x010 | |
86 | #define MP_ETH_PCXR 0x408 | |
87 | #define MP_ETH_SDCMR 0x448 | |
88 | #define MP_ETH_ICR 0x450 | |
89 | #define MP_ETH_IMR 0x458 | |
90 | #define MP_ETH_FRDP0 0x480 | |
91 | #define MP_ETH_FRDP1 0x484 | |
92 | #define MP_ETH_FRDP2 0x488 | |
93 | #define MP_ETH_FRDP3 0x48C | |
94 | #define MP_ETH_CRDP0 0x4A0 | |
95 | #define MP_ETH_CRDP1 0x4A4 | |
96 | #define MP_ETH_CRDP2 0x4A8 | |
97 | #define MP_ETH_CRDP3 0x4AC | |
98 | #define MP_ETH_CTDP0 0x4E0 | |
99 | #define MP_ETH_CTDP1 0x4E4 | |
24859b68 AZ |
100 | |
101 | /* MII PHY access */ | |
102 | #define MP_ETH_SMIR_DATA 0x0000FFFF | |
103 | #define MP_ETH_SMIR_ADDR 0x03FF0000 | |
104 | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ | |
105 | #define MP_ETH_SMIR_RDVALID (1 << 27) | |
106 | ||
107 | /* PHY registers */ | |
108 | #define MP_ETH_PHY1_BMSR 0x00210000 | |
109 | #define MP_ETH_PHY1_PHYSID1 0x00410000 | |
110 | #define MP_ETH_PHY1_PHYSID2 0x00610000 | |
111 | ||
112 | #define MP_PHY_BMSR_LINK 0x0004 | |
113 | #define MP_PHY_BMSR_AUTONEG 0x0008 | |
114 | ||
115 | #define MP_PHY_88E3015 0x01410E20 | |
116 | ||
117 | /* TX descriptor status */ | |
2b194951 | 118 | #define MP_ETH_TX_OWN (1U << 31) |
24859b68 AZ |
119 | |
120 | /* RX descriptor status */ | |
2b194951 | 121 | #define MP_ETH_RX_OWN (1U << 31) |
24859b68 AZ |
122 | |
123 | /* Interrupt cause/mask bits */ | |
124 | #define MP_ETH_IRQ_RX_BIT 0 | |
125 | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) | |
126 | #define MP_ETH_IRQ_TXHI_BIT 2 | |
127 | #define MP_ETH_IRQ_TXLO_BIT 3 | |
128 | ||
129 | /* Port config bits */ | |
130 | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ | |
131 | ||
132 | /* SDMA command bits */ | |
133 | #define MP_ETH_CMD_TXHI (1 << 23) | |
134 | #define MP_ETH_CMD_TXLO (1 << 22) | |
135 | ||
136 | typedef struct mv88w8618_tx_desc { | |
137 | uint32_t cmdstat; | |
138 | uint16_t res; | |
139 | uint16_t bytes; | |
140 | uint32_t buffer; | |
141 | uint32_t next; | |
142 | } mv88w8618_tx_desc; | |
143 | ||
144 | typedef struct mv88w8618_rx_desc { | |
145 | uint32_t cmdstat; | |
146 | uint16_t bytes; | |
147 | uint16_t buffer_size; | |
148 | uint32_t buffer; | |
149 | uint32_t next; | |
150 | } mv88w8618_rx_desc; | |
151 | ||
a77d90e6 AF |
152 | #define TYPE_MV88W8618_ETH "mv88w8618_eth" |
153 | #define MV88W8618_ETH(obj) \ | |
154 | OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH) | |
155 | ||
24859b68 | 156 | typedef struct mv88w8618_eth_state { |
a77d90e6 AF |
157 | /*< private >*/ |
158 | SysBusDevice parent_obj; | |
159 | /*< public >*/ | |
160 | ||
19b4a424 | 161 | MemoryRegion iomem; |
24859b68 AZ |
162 | qemu_irq irq; |
163 | uint32_t smir; | |
164 | uint32_t icr; | |
165 | uint32_t imr; | |
b946a153 | 166 | int mmio_index; |
d5b61ddd | 167 | uint32_t vlan_header; |
930c8682 PB |
168 | uint32_t tx_queue[2]; |
169 | uint32_t rx_queue[4]; | |
170 | uint32_t frx_queue[4]; | |
171 | uint32_t cur_rx[4]; | |
3a94dd18 | 172 | NICState *nic; |
4c91cd28 | 173 | NICConf conf; |
24859b68 AZ |
174 | } mv88w8618_eth_state; |
175 | ||
930c8682 PB |
176 | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
177 | { | |
178 | cpu_to_le32s(&desc->cmdstat); | |
179 | cpu_to_le16s(&desc->bytes); | |
180 | cpu_to_le16s(&desc->buffer_size); | |
181 | cpu_to_le32s(&desc->buffer); | |
182 | cpu_to_le32s(&desc->next); | |
e1fe50dc | 183 | cpu_physical_memory_write(addr, desc, sizeof(*desc)); |
930c8682 PB |
184 | } |
185 | ||
186 | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) | |
187 | { | |
e1fe50dc | 188 | cpu_physical_memory_read(addr, desc, sizeof(*desc)); |
930c8682 PB |
189 | le32_to_cpus(&desc->cmdstat); |
190 | le16_to_cpus(&desc->bytes); | |
191 | le16_to_cpus(&desc->buffer_size); | |
192 | le32_to_cpus(&desc->buffer); | |
193 | le32_to_cpus(&desc->next); | |
194 | } | |
195 | ||
4e68f7a0 | 196 | static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
24859b68 | 197 | { |
cc1f0f45 | 198 | mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); |
930c8682 PB |
199 | uint32_t desc_addr; |
200 | mv88w8618_rx_desc desc; | |
24859b68 AZ |
201 | int i; |
202 | ||
203 | for (i = 0; i < 4; i++) { | |
930c8682 | 204 | desc_addr = s->cur_rx[i]; |
49fedd0d | 205 | if (!desc_addr) { |
24859b68 | 206 | continue; |
49fedd0d | 207 | } |
24859b68 | 208 | do { |
930c8682 PB |
209 | eth_rx_desc_get(desc_addr, &desc); |
210 | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { | |
211 | cpu_physical_memory_write(desc.buffer + s->vlan_header, | |
212 | buf, size); | |
213 | desc.bytes = size + s->vlan_header; | |
214 | desc.cmdstat &= ~MP_ETH_RX_OWN; | |
215 | s->cur_rx[i] = desc.next; | |
24859b68 AZ |
216 | |
217 | s->icr |= MP_ETH_IRQ_RX; | |
49fedd0d | 218 | if (s->icr & s->imr) { |
24859b68 | 219 | qemu_irq_raise(s->irq); |
49fedd0d | 220 | } |
930c8682 | 221 | eth_rx_desc_put(desc_addr, &desc); |
4f1c942b | 222 | return size; |
24859b68 | 223 | } |
930c8682 PB |
224 | desc_addr = desc.next; |
225 | } while (desc_addr != s->rx_queue[i]); | |
24859b68 | 226 | } |
4f1c942b | 227 | return size; |
24859b68 AZ |
228 | } |
229 | ||
930c8682 PB |
230 | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
231 | { | |
232 | cpu_to_le32s(&desc->cmdstat); | |
233 | cpu_to_le16s(&desc->res); | |
234 | cpu_to_le16s(&desc->bytes); | |
235 | cpu_to_le32s(&desc->buffer); | |
236 | cpu_to_le32s(&desc->next); | |
e1fe50dc | 237 | cpu_physical_memory_write(addr, desc, sizeof(*desc)); |
930c8682 PB |
238 | } |
239 | ||
240 | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) | |
241 | { | |
e1fe50dc | 242 | cpu_physical_memory_read(addr, desc, sizeof(*desc)); |
930c8682 PB |
243 | le32_to_cpus(&desc->cmdstat); |
244 | le16_to_cpus(&desc->res); | |
245 | le16_to_cpus(&desc->bytes); | |
246 | le32_to_cpus(&desc->buffer); | |
247 | le32_to_cpus(&desc->next); | |
248 | } | |
249 | ||
24859b68 AZ |
250 | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
251 | { | |
930c8682 PB |
252 | uint32_t desc_addr = s->tx_queue[queue_index]; |
253 | mv88w8618_tx_desc desc; | |
07b064e9 | 254 | uint32_t next_desc; |
930c8682 PB |
255 | uint8_t buf[2048]; |
256 | int len; | |
257 | ||
24859b68 | 258 | do { |
930c8682 | 259 | eth_tx_desc_get(desc_addr, &desc); |
07b064e9 | 260 | next_desc = desc.next; |
930c8682 PB |
261 | if (desc.cmdstat & MP_ETH_TX_OWN) { |
262 | len = desc.bytes; | |
263 | if (len < 2048) { | |
264 | cpu_physical_memory_read(desc.buffer, buf, len); | |
b356f76d | 265 | qemu_send_packet(qemu_get_queue(s->nic), buf, len); |
930c8682 PB |
266 | } |
267 | desc.cmdstat &= ~MP_ETH_TX_OWN; | |
24859b68 | 268 | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); |
930c8682 | 269 | eth_tx_desc_put(desc_addr, &desc); |
24859b68 | 270 | } |
07b064e9 | 271 | desc_addr = next_desc; |
930c8682 | 272 | } while (desc_addr != s->tx_queue[queue_index]); |
24859b68 AZ |
273 | } |
274 | ||
a8170e5e | 275 | static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset, |
19b4a424 | 276 | unsigned size) |
24859b68 AZ |
277 | { |
278 | mv88w8618_eth_state *s = opaque; | |
279 | ||
24859b68 AZ |
280 | switch (offset) { |
281 | case MP_ETH_SMIR: | |
282 | if (s->smir & MP_ETH_SMIR_OPCODE) { | |
283 | switch (s->smir & MP_ETH_SMIR_ADDR) { | |
284 | case MP_ETH_PHY1_BMSR: | |
285 | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | | |
286 | MP_ETH_SMIR_RDVALID; | |
287 | case MP_ETH_PHY1_PHYSID1: | |
288 | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; | |
289 | case MP_ETH_PHY1_PHYSID2: | |
290 | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; | |
291 | default: | |
292 | return MP_ETH_SMIR_RDVALID; | |
293 | } | |
294 | } | |
295 | return 0; | |
296 | ||
297 | case MP_ETH_ICR: | |
298 | return s->icr; | |
299 | ||
300 | case MP_ETH_IMR: | |
301 | return s->imr; | |
302 | ||
303 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 304 | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
24859b68 AZ |
305 | |
306 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
930c8682 | 307 | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
24859b68 | 308 | |
cf143ad3 | 309 | case MP_ETH_CTDP0 ... MP_ETH_CTDP1: |
930c8682 | 310 | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
24859b68 AZ |
311 | |
312 | default: | |
313 | return 0; | |
314 | } | |
315 | } | |
316 | ||
a8170e5e | 317 | static void mv88w8618_eth_write(void *opaque, hwaddr offset, |
19b4a424 | 318 | uint64_t value, unsigned size) |
24859b68 AZ |
319 | { |
320 | mv88w8618_eth_state *s = opaque; | |
321 | ||
24859b68 AZ |
322 | switch (offset) { |
323 | case MP_ETH_SMIR: | |
324 | s->smir = value; | |
325 | break; | |
326 | ||
327 | case MP_ETH_PCXR: | |
328 | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; | |
329 | break; | |
330 | ||
331 | case MP_ETH_SDCMR: | |
49fedd0d | 332 | if (value & MP_ETH_CMD_TXHI) { |
24859b68 | 333 | eth_send(s, 1); |
49fedd0d JK |
334 | } |
335 | if (value & MP_ETH_CMD_TXLO) { | |
24859b68 | 336 | eth_send(s, 0); |
49fedd0d JK |
337 | } |
338 | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) { | |
24859b68 | 339 | qemu_irq_raise(s->irq); |
49fedd0d | 340 | } |
24859b68 AZ |
341 | break; |
342 | ||
343 | case MP_ETH_ICR: | |
344 | s->icr &= value; | |
345 | break; | |
346 | ||
347 | case MP_ETH_IMR: | |
348 | s->imr = value; | |
49fedd0d | 349 | if (s->icr & s->imr) { |
24859b68 | 350 | qemu_irq_raise(s->irq); |
49fedd0d | 351 | } |
24859b68 AZ |
352 | break; |
353 | ||
354 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 355 | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; |
24859b68 AZ |
356 | break; |
357 | ||
358 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
359 | s->rx_queue[(offset - MP_ETH_CRDP0)/4] = | |
930c8682 | 360 | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; |
24859b68 AZ |
361 | break; |
362 | ||
cf143ad3 | 363 | case MP_ETH_CTDP0 ... MP_ETH_CTDP1: |
930c8682 | 364 | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; |
24859b68 AZ |
365 | break; |
366 | } | |
367 | } | |
368 | ||
19b4a424 AK |
369 | static const MemoryRegionOps mv88w8618_eth_ops = { |
370 | .read = mv88w8618_eth_read, | |
371 | .write = mv88w8618_eth_write, | |
372 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
373 | }; |
374 | ||
4e68f7a0 | 375 | static void eth_cleanup(NetClientState *nc) |
b946a153 | 376 | { |
cc1f0f45 | 377 | mv88w8618_eth_state *s = qemu_get_nic_opaque(nc); |
b946a153 | 378 | |
3a94dd18 | 379 | s->nic = NULL; |
b946a153 AL |
380 | } |
381 | ||
3a94dd18 | 382 | static NetClientInfo net_mv88w8618_info = { |
f394b2e2 | 383 | .type = NET_CLIENT_DRIVER_NIC, |
3a94dd18 | 384 | .size = sizeof(NICState), |
3a94dd18 MM |
385 | .receive = eth_receive, |
386 | .cleanup = eth_cleanup, | |
387 | }; | |
388 | ||
ece71994 | 389 | static void mv88w8618_eth_init(Object *obj) |
24859b68 | 390 | { |
ece71994 | 391 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
a77d90e6 AF |
392 | DeviceState *dev = DEVICE(sbd); |
393 | mv88w8618_eth_state *s = MV88W8618_ETH(dev); | |
0ae18cee | 394 | |
a77d90e6 | 395 | sysbus_init_irq(sbd, &s->irq); |
ece71994 | 396 | memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s, |
64bde0f3 | 397 | "mv88w8618-eth", MP_ETH_SIZE); |
a77d90e6 | 398 | sysbus_init_mmio(sbd, &s->iomem); |
ece71994 XZ |
399 | } |
400 | ||
401 | static void mv88w8618_eth_realize(DeviceState *dev, Error **errp) | |
402 | { | |
403 | mv88w8618_eth_state *s = MV88W8618_ETH(dev); | |
404 | ||
405 | s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, | |
406 | object_get_typename(OBJECT(dev)), dev->id, s); | |
24859b68 AZ |
407 | } |
408 | ||
d5b61ddd JK |
409 | static const VMStateDescription mv88w8618_eth_vmsd = { |
410 | .name = "mv88w8618_eth", | |
411 | .version_id = 1, | |
412 | .minimum_version_id = 1, | |
d5b61ddd JK |
413 | .fields = (VMStateField[]) { |
414 | VMSTATE_UINT32(smir, mv88w8618_eth_state), | |
415 | VMSTATE_UINT32(icr, mv88w8618_eth_state), | |
416 | VMSTATE_UINT32(imr, mv88w8618_eth_state), | |
417 | VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), | |
418 | VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2), | |
419 | VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4), | |
420 | VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4), | |
421 | VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4), | |
422 | VMSTATE_END_OF_LIST() | |
423 | } | |
424 | }; | |
425 | ||
999e12bb AL |
426 | static Property mv88w8618_eth_properties[] = { |
427 | DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), | |
428 | DEFINE_PROP_END_OF_LIST(), | |
429 | }; | |
430 | ||
431 | static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) | |
432 | { | |
39bffca2 | 433 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 434 | |
39bffca2 AL |
435 | dc->vmsd = &mv88w8618_eth_vmsd; |
436 | dc->props = mv88w8618_eth_properties; | |
ece71994 | 437 | dc->realize = mv88w8618_eth_realize; |
999e12bb AL |
438 | } |
439 | ||
8c43a6f0 | 440 | static const TypeInfo mv88w8618_eth_info = { |
a77d90e6 | 441 | .name = TYPE_MV88W8618_ETH, |
39bffca2 AL |
442 | .parent = TYPE_SYS_BUS_DEVICE, |
443 | .instance_size = sizeof(mv88w8618_eth_state), | |
ece71994 | 444 | .instance_init = mv88w8618_eth_init, |
39bffca2 | 445 | .class_init = mv88w8618_eth_class_init, |
d5b61ddd JK |
446 | }; |
447 | ||
24859b68 AZ |
448 | /* LCD register offsets */ |
449 | #define MP_LCD_IRQCTRL 0x180 | |
450 | #define MP_LCD_IRQSTAT 0x184 | |
451 | #define MP_LCD_SPICTRL 0x1ac | |
452 | #define MP_LCD_INST 0x1bc | |
453 | #define MP_LCD_DATA 0x1c0 | |
454 | ||
455 | /* Mode magics */ | |
456 | #define MP_LCD_SPI_DATA 0x00100011 | |
457 | #define MP_LCD_SPI_CMD 0x00104011 | |
458 | #define MP_LCD_SPI_INVALID 0x00000000 | |
459 | ||
460 | /* Commmands */ | |
461 | #define MP_LCD_INST_SETPAGE0 0xB0 | |
462 | /* ... */ | |
463 | #define MP_LCD_INST_SETPAGE7 0xB7 | |
464 | ||
465 | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ | |
466 | ||
2cca58fd AF |
467 | #define TYPE_MUSICPAL_LCD "musicpal_lcd" |
468 | #define MUSICPAL_LCD(obj) \ | |
469 | OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD) | |
470 | ||
24859b68 | 471 | typedef struct musicpal_lcd_state { |
2cca58fd AF |
472 | /*< private >*/ |
473 | SysBusDevice parent_obj; | |
474 | /*< public >*/ | |
475 | ||
19b4a424 | 476 | MemoryRegion iomem; |
343ec8e4 | 477 | uint32_t brightness; |
24859b68 AZ |
478 | uint32_t mode; |
479 | uint32_t irqctrl; | |
d5b61ddd JK |
480 | uint32_t page; |
481 | uint32_t page_off; | |
c78f7137 | 482 | QemuConsole *con; |
24859b68 AZ |
483 | uint8_t video_ram[128*64/8]; |
484 | } musicpal_lcd_state; | |
485 | ||
343ec8e4 | 486 | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) |
24859b68 | 487 | { |
343ec8e4 BC |
488 | switch (s->brightness) { |
489 | case 7: | |
490 | return col; | |
491 | case 0: | |
24859b68 | 492 | return 0; |
24859b68 | 493 | default: |
343ec8e4 | 494 | return (col * s->brightness) / 7; |
24859b68 AZ |
495 | } |
496 | } | |
497 | ||
0266f2c7 AZ |
498 | #define SET_LCD_PIXEL(depth, type) \ |
499 | static inline void glue(set_lcd_pixel, depth) \ | |
500 | (musicpal_lcd_state *s, int x, int y, type col) \ | |
501 | { \ | |
502 | int dx, dy; \ | |
c78f7137 GH |
503 | DisplaySurface *surface = qemu_console_surface(s->con); \ |
504 | type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \ | |
0266f2c7 AZ |
505 | \ |
506 | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ | |
507 | for (dx = 0; dx < 3; dx++, pixel++) \ | |
508 | *pixel = col; \ | |
24859b68 | 509 | } |
0266f2c7 AZ |
510 | SET_LCD_PIXEL(8, uint8_t) |
511 | SET_LCD_PIXEL(16, uint16_t) | |
512 | SET_LCD_PIXEL(32, uint32_t) | |
513 | ||
24859b68 AZ |
514 | static void lcd_refresh(void *opaque) |
515 | { | |
516 | musicpal_lcd_state *s = opaque; | |
c78f7137 | 517 | DisplaySurface *surface = qemu_console_surface(s->con); |
0266f2c7 | 518 | int x, y, col; |
24859b68 | 519 | |
c78f7137 | 520 | switch (surface_bits_per_pixel(surface)) { |
0266f2c7 AZ |
521 | case 0: |
522 | return; | |
523 | #define LCD_REFRESH(depth, func) \ | |
524 | case depth: \ | |
343ec8e4 BC |
525 | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
526 | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ | |
527 | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ | |
49fedd0d JK |
528 | for (x = 0; x < 128; x++) { \ |
529 | for (y = 0; y < 64; y++) { \ | |
530 | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ | |
0266f2c7 | 531 | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
49fedd0d | 532 | } else { \ |
0266f2c7 | 533 | glue(set_lcd_pixel, depth)(s, x, y, 0); \ |
49fedd0d JK |
534 | } \ |
535 | } \ | |
536 | } \ | |
0266f2c7 AZ |
537 | break; |
538 | LCD_REFRESH(8, rgb_to_pixel8) | |
539 | LCD_REFRESH(16, rgb_to_pixel16) | |
c78f7137 | 540 | LCD_REFRESH(32, (is_surface_bgr(surface) ? |
bf9b48af | 541 | rgb_to_pixel32bgr : rgb_to_pixel32)) |
0266f2c7 | 542 | default: |
2ac71179 | 543 | hw_error("unsupported colour depth %i\n", |
c78f7137 | 544 | surface_bits_per_pixel(surface)); |
0266f2c7 | 545 | } |
24859b68 | 546 | |
c78f7137 | 547 | dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); |
24859b68 AZ |
548 | } |
549 | ||
167bc3d2 AZ |
550 | static void lcd_invalidate(void *opaque) |
551 | { | |
167bc3d2 AZ |
552 | } |
553 | ||
2c79fed3 | 554 | static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level) |
343ec8e4 | 555 | { |
243cd13c | 556 | musicpal_lcd_state *s = opaque; |
343ec8e4 BC |
557 | s->brightness &= ~(1 << irq); |
558 | s->brightness |= level << irq; | |
559 | } | |
560 | ||
a8170e5e | 561 | static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset, |
19b4a424 | 562 | unsigned size) |
24859b68 AZ |
563 | { |
564 | musicpal_lcd_state *s = opaque; | |
565 | ||
24859b68 AZ |
566 | switch (offset) { |
567 | case MP_LCD_IRQCTRL: | |
568 | return s->irqctrl; | |
569 | ||
570 | default: | |
571 | return 0; | |
572 | } | |
573 | } | |
574 | ||
a8170e5e | 575 | static void musicpal_lcd_write(void *opaque, hwaddr offset, |
19b4a424 | 576 | uint64_t value, unsigned size) |
24859b68 AZ |
577 | { |
578 | musicpal_lcd_state *s = opaque; | |
579 | ||
24859b68 AZ |
580 | switch (offset) { |
581 | case MP_LCD_IRQCTRL: | |
582 | s->irqctrl = value; | |
583 | break; | |
584 | ||
585 | case MP_LCD_SPICTRL: | |
49fedd0d | 586 | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) { |
24859b68 | 587 | s->mode = value; |
49fedd0d | 588 | } else { |
24859b68 | 589 | s->mode = MP_LCD_SPI_INVALID; |
49fedd0d | 590 | } |
24859b68 AZ |
591 | break; |
592 | ||
593 | case MP_LCD_INST: | |
594 | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { | |
595 | s->page = value - MP_LCD_INST_SETPAGE0; | |
596 | s->page_off = 0; | |
597 | } | |
598 | break; | |
599 | ||
600 | case MP_LCD_DATA: | |
601 | if (s->mode == MP_LCD_SPI_CMD) { | |
602 | if (value >= MP_LCD_INST_SETPAGE0 && | |
603 | value <= MP_LCD_INST_SETPAGE7) { | |
604 | s->page = value - MP_LCD_INST_SETPAGE0; | |
605 | s->page_off = 0; | |
606 | } | |
607 | } else if (s->mode == MP_LCD_SPI_DATA) { | |
608 | s->video_ram[s->page*128 + s->page_off] = value; | |
609 | s->page_off = (s->page_off + 1) & 127; | |
610 | } | |
611 | break; | |
612 | } | |
613 | } | |
614 | ||
19b4a424 AK |
615 | static const MemoryRegionOps musicpal_lcd_ops = { |
616 | .read = musicpal_lcd_read, | |
617 | .write = musicpal_lcd_write, | |
618 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
619 | }; |
620 | ||
380cd056 GH |
621 | static const GraphicHwOps musicpal_gfx_ops = { |
622 | .invalidate = lcd_invalidate, | |
623 | .gfx_update = lcd_refresh, | |
624 | }; | |
625 | ||
ece71994 XZ |
626 | static void musicpal_lcd_realize(DeviceState *dev, Error **errp) |
627 | { | |
628 | musicpal_lcd_state *s = MUSICPAL_LCD(dev); | |
629 | s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s); | |
630 | qemu_console_resize(s->con, 128 * 3, 64 * 3); | |
631 | } | |
632 | ||
633 | static void musicpal_lcd_init(Object *obj) | |
24859b68 | 634 | { |
ece71994 | 635 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
2cca58fd AF |
636 | DeviceState *dev = DEVICE(sbd); |
637 | musicpal_lcd_state *s = MUSICPAL_LCD(dev); | |
24859b68 | 638 | |
343ec8e4 BC |
639 | s->brightness = 7; |
640 | ||
ece71994 | 641 | memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s, |
19b4a424 | 642 | "musicpal-lcd", MP_LCD_SIZE); |
2cca58fd | 643 | sysbus_init_mmio(sbd, &s->iomem); |
24859b68 | 644 | |
2cca58fd | 645 | qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3); |
24859b68 AZ |
646 | } |
647 | ||
d5b61ddd JK |
648 | static const VMStateDescription musicpal_lcd_vmsd = { |
649 | .name = "musicpal_lcd", | |
650 | .version_id = 1, | |
651 | .minimum_version_id = 1, | |
d5b61ddd JK |
652 | .fields = (VMStateField[]) { |
653 | VMSTATE_UINT32(brightness, musicpal_lcd_state), | |
654 | VMSTATE_UINT32(mode, musicpal_lcd_state), | |
655 | VMSTATE_UINT32(irqctrl, musicpal_lcd_state), | |
656 | VMSTATE_UINT32(page, musicpal_lcd_state), | |
657 | VMSTATE_UINT32(page_off, musicpal_lcd_state), | |
658 | VMSTATE_BUFFER(video_ram, musicpal_lcd_state), | |
659 | VMSTATE_END_OF_LIST() | |
660 | } | |
661 | }; | |
662 | ||
999e12bb AL |
663 | static void musicpal_lcd_class_init(ObjectClass *klass, void *data) |
664 | { | |
39bffca2 | 665 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 666 | |
39bffca2 | 667 | dc->vmsd = &musicpal_lcd_vmsd; |
ece71994 | 668 | dc->realize = musicpal_lcd_realize; |
999e12bb AL |
669 | } |
670 | ||
8c43a6f0 | 671 | static const TypeInfo musicpal_lcd_info = { |
2cca58fd | 672 | .name = TYPE_MUSICPAL_LCD, |
39bffca2 AL |
673 | .parent = TYPE_SYS_BUS_DEVICE, |
674 | .instance_size = sizeof(musicpal_lcd_state), | |
ece71994 | 675 | .instance_init = musicpal_lcd_init, |
39bffca2 | 676 | .class_init = musicpal_lcd_class_init, |
d5b61ddd JK |
677 | }; |
678 | ||
24859b68 AZ |
679 | /* PIC register offsets */ |
680 | #define MP_PIC_STATUS 0x00 | |
681 | #define MP_PIC_ENABLE_SET 0x08 | |
682 | #define MP_PIC_ENABLE_CLR 0x0C | |
683 | ||
c7bd0fd9 AF |
684 | #define TYPE_MV88W8618_PIC "mv88w8618_pic" |
685 | #define MV88W8618_PIC(obj) \ | |
686 | OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC) | |
687 | ||
688 | typedef struct mv88w8618_pic_state { | |
689 | /*< private >*/ | |
690 | SysBusDevice parent_obj; | |
691 | /*< public >*/ | |
692 | ||
19b4a424 | 693 | MemoryRegion iomem; |
24859b68 AZ |
694 | uint32_t level; |
695 | uint32_t enabled; | |
696 | qemu_irq parent_irq; | |
697 | } mv88w8618_pic_state; | |
698 | ||
699 | static void mv88w8618_pic_update(mv88w8618_pic_state *s) | |
700 | { | |
701 | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); | |
702 | } | |
703 | ||
704 | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) | |
705 | { | |
706 | mv88w8618_pic_state *s = opaque; | |
707 | ||
49fedd0d | 708 | if (level) { |
24859b68 | 709 | s->level |= 1 << irq; |
49fedd0d | 710 | } else { |
24859b68 | 711 | s->level &= ~(1 << irq); |
49fedd0d | 712 | } |
24859b68 AZ |
713 | mv88w8618_pic_update(s); |
714 | } | |
715 | ||
a8170e5e | 716 | static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset, |
19b4a424 | 717 | unsigned size) |
24859b68 AZ |
718 | { |
719 | mv88w8618_pic_state *s = opaque; | |
720 | ||
24859b68 AZ |
721 | switch (offset) { |
722 | case MP_PIC_STATUS: | |
723 | return s->level & s->enabled; | |
724 | ||
725 | default: | |
726 | return 0; | |
727 | } | |
728 | } | |
729 | ||
a8170e5e | 730 | static void mv88w8618_pic_write(void *opaque, hwaddr offset, |
19b4a424 | 731 | uint64_t value, unsigned size) |
24859b68 AZ |
732 | { |
733 | mv88w8618_pic_state *s = opaque; | |
734 | ||
24859b68 AZ |
735 | switch (offset) { |
736 | case MP_PIC_ENABLE_SET: | |
737 | s->enabled |= value; | |
738 | break; | |
739 | ||
740 | case MP_PIC_ENABLE_CLR: | |
741 | s->enabled &= ~value; | |
742 | s->level &= ~value; | |
743 | break; | |
744 | } | |
745 | mv88w8618_pic_update(s); | |
746 | } | |
747 | ||
d5b61ddd | 748 | static void mv88w8618_pic_reset(DeviceState *d) |
24859b68 | 749 | { |
c7bd0fd9 | 750 | mv88w8618_pic_state *s = MV88W8618_PIC(d); |
24859b68 AZ |
751 | |
752 | s->level = 0; | |
753 | s->enabled = 0; | |
754 | } | |
755 | ||
19b4a424 AK |
756 | static const MemoryRegionOps mv88w8618_pic_ops = { |
757 | .read = mv88w8618_pic_read, | |
758 | .write = mv88w8618_pic_write, | |
759 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
760 | }; |
761 | ||
ece71994 | 762 | static void mv88w8618_pic_init(Object *obj) |
24859b68 | 763 | { |
ece71994 | 764 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
c7bd0fd9 | 765 | mv88w8618_pic_state *s = MV88W8618_PIC(dev); |
24859b68 | 766 | |
c7bd0fd9 | 767 | qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32); |
b47b50fa | 768 | sysbus_init_irq(dev, &s->parent_irq); |
ece71994 | 769 | memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s, |
19b4a424 | 770 | "musicpal-pic", MP_PIC_SIZE); |
750ecd44 | 771 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
772 | } |
773 | ||
d5b61ddd JK |
774 | static const VMStateDescription mv88w8618_pic_vmsd = { |
775 | .name = "mv88w8618_pic", | |
776 | .version_id = 1, | |
777 | .minimum_version_id = 1, | |
d5b61ddd JK |
778 | .fields = (VMStateField[]) { |
779 | VMSTATE_UINT32(level, mv88w8618_pic_state), | |
780 | VMSTATE_UINT32(enabled, mv88w8618_pic_state), | |
781 | VMSTATE_END_OF_LIST() | |
782 | } | |
783 | }; | |
784 | ||
999e12bb AL |
785 | static void mv88w8618_pic_class_init(ObjectClass *klass, void *data) |
786 | { | |
39bffca2 | 787 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 788 | |
39bffca2 AL |
789 | dc->reset = mv88w8618_pic_reset; |
790 | dc->vmsd = &mv88w8618_pic_vmsd; | |
999e12bb AL |
791 | } |
792 | ||
8c43a6f0 | 793 | static const TypeInfo mv88w8618_pic_info = { |
c7bd0fd9 | 794 | .name = TYPE_MV88W8618_PIC, |
39bffca2 AL |
795 | .parent = TYPE_SYS_BUS_DEVICE, |
796 | .instance_size = sizeof(mv88w8618_pic_state), | |
ece71994 | 797 | .instance_init = mv88w8618_pic_init, |
39bffca2 | 798 | .class_init = mv88w8618_pic_class_init, |
d5b61ddd JK |
799 | }; |
800 | ||
24859b68 AZ |
801 | /* PIT register offsets */ |
802 | #define MP_PIT_TIMER1_LENGTH 0x00 | |
803 | /* ... */ | |
804 | #define MP_PIT_TIMER4_LENGTH 0x0C | |
805 | #define MP_PIT_CONTROL 0x10 | |
806 | #define MP_PIT_TIMER1_VALUE 0x14 | |
807 | /* ... */ | |
808 | #define MP_PIT_TIMER4_VALUE 0x20 | |
809 | #define MP_BOARD_RESET 0x34 | |
810 | ||
811 | /* Magic board reset value (probably some watchdog behind it) */ | |
812 | #define MP_BOARD_RESET_MAGIC 0x10000 | |
813 | ||
814 | typedef struct mv88w8618_timer_state { | |
b47b50fa | 815 | ptimer_state *ptimer; |
24859b68 AZ |
816 | uint32_t limit; |
817 | int freq; | |
818 | qemu_irq irq; | |
819 | } mv88w8618_timer_state; | |
820 | ||
4adc8541 AF |
821 | #define TYPE_MV88W8618_PIT "mv88w8618_pit" |
822 | #define MV88W8618_PIT(obj) \ | |
823 | OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT) | |
824 | ||
24859b68 | 825 | typedef struct mv88w8618_pit_state { |
4adc8541 AF |
826 | /*< private >*/ |
827 | SysBusDevice parent_obj; | |
828 | /*< public >*/ | |
829 | ||
19b4a424 | 830 | MemoryRegion iomem; |
b47b50fa | 831 | mv88w8618_timer_state timer[4]; |
24859b68 AZ |
832 | } mv88w8618_pit_state; |
833 | ||
834 | static void mv88w8618_timer_tick(void *opaque) | |
835 | { | |
836 | mv88w8618_timer_state *s = opaque; | |
837 | ||
838 | qemu_irq_raise(s->irq); | |
839 | } | |
840 | ||
b47b50fa PB |
841 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
842 | uint32_t freq) | |
24859b68 | 843 | { |
24859b68 AZ |
844 | QEMUBH *bh; |
845 | ||
b47b50fa | 846 | sysbus_init_irq(dev, &s->irq); |
24859b68 AZ |
847 | s->freq = freq; |
848 | ||
849 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | |
e7ea81c3 | 850 | s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
24859b68 AZ |
851 | } |
852 | ||
a8170e5e | 853 | static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset, |
19b4a424 | 854 | unsigned size) |
24859b68 AZ |
855 | { |
856 | mv88w8618_pit_state *s = opaque; | |
857 | mv88w8618_timer_state *t; | |
858 | ||
24859b68 AZ |
859 | switch (offset) { |
860 | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: | |
b47b50fa PB |
861 | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; |
862 | return ptimer_get_count(t->ptimer); | |
24859b68 AZ |
863 | |
864 | default: | |
865 | return 0; | |
866 | } | |
867 | } | |
868 | ||
a8170e5e | 869 | static void mv88w8618_pit_write(void *opaque, hwaddr offset, |
19b4a424 | 870 | uint64_t value, unsigned size) |
24859b68 AZ |
871 | { |
872 | mv88w8618_pit_state *s = opaque; | |
873 | mv88w8618_timer_state *t; | |
874 | int i; | |
875 | ||
24859b68 AZ |
876 | switch (offset) { |
877 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | |
b47b50fa | 878 | t = &s->timer[offset >> 2]; |
24859b68 | 879 | t->limit = value; |
c88d6bde JK |
880 | if (t->limit > 0) { |
881 | ptimer_set_limit(t->ptimer, t->limit, 1); | |
882 | } else { | |
883 | ptimer_stop(t->ptimer); | |
884 | } | |
24859b68 AZ |
885 | break; |
886 | ||
887 | case MP_PIT_CONTROL: | |
888 | for (i = 0; i < 4; i++) { | |
c88d6bde JK |
889 | t = &s->timer[i]; |
890 | if (value & 0xf && t->limit > 0) { | |
b47b50fa PB |
891 | ptimer_set_limit(t->ptimer, t->limit, 0); |
892 | ptimer_set_freq(t->ptimer, t->freq); | |
893 | ptimer_run(t->ptimer, 0); | |
c88d6bde JK |
894 | } else { |
895 | ptimer_stop(t->ptimer); | |
24859b68 AZ |
896 | } |
897 | value >>= 4; | |
898 | } | |
899 | break; | |
900 | ||
901 | case MP_BOARD_RESET: | |
49fedd0d | 902 | if (value == MP_BOARD_RESET_MAGIC) { |
cf83f140 | 903 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
49fedd0d | 904 | } |
24859b68 AZ |
905 | break; |
906 | } | |
907 | } | |
908 | ||
d5b61ddd | 909 | static void mv88w8618_pit_reset(DeviceState *d) |
c88d6bde | 910 | { |
4adc8541 | 911 | mv88w8618_pit_state *s = MV88W8618_PIT(d); |
c88d6bde JK |
912 | int i; |
913 | ||
914 | for (i = 0; i < 4; i++) { | |
915 | ptimer_stop(s->timer[i].ptimer); | |
916 | s->timer[i].limit = 0; | |
917 | } | |
918 | } | |
919 | ||
19b4a424 AK |
920 | static const MemoryRegionOps mv88w8618_pit_ops = { |
921 | .read = mv88w8618_pit_read, | |
922 | .write = mv88w8618_pit_write, | |
923 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
924 | }; |
925 | ||
ece71994 | 926 | static void mv88w8618_pit_init(Object *obj) |
24859b68 | 927 | { |
ece71994 | 928 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
4adc8541 | 929 | mv88w8618_pit_state *s = MV88W8618_PIT(dev); |
b47b50fa | 930 | int i; |
24859b68 | 931 | |
24859b68 AZ |
932 | /* Letting them all run at 1 MHz is likely just a pragmatic |
933 | * simplification. */ | |
b47b50fa PB |
934 | for (i = 0; i < 4; i++) { |
935 | mv88w8618_timer_init(dev, &s->timer[i], 1000000); | |
936 | } | |
24859b68 | 937 | |
ece71994 | 938 | memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s, |
19b4a424 | 939 | "musicpal-pit", MP_PIT_SIZE); |
750ecd44 | 940 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
941 | } |
942 | ||
d5b61ddd JK |
943 | static const VMStateDescription mv88w8618_timer_vmsd = { |
944 | .name = "timer", | |
945 | .version_id = 1, | |
946 | .minimum_version_id = 1, | |
d5b61ddd JK |
947 | .fields = (VMStateField[]) { |
948 | VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), | |
949 | VMSTATE_UINT32(limit, mv88w8618_timer_state), | |
950 | VMSTATE_END_OF_LIST() | |
951 | } | |
952 | }; | |
953 | ||
954 | static const VMStateDescription mv88w8618_pit_vmsd = { | |
955 | .name = "mv88w8618_pit", | |
956 | .version_id = 1, | |
957 | .minimum_version_id = 1, | |
d5b61ddd JK |
958 | .fields = (VMStateField[]) { |
959 | VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, | |
960 | mv88w8618_timer_vmsd, mv88w8618_timer_state), | |
961 | VMSTATE_END_OF_LIST() | |
962 | } | |
963 | }; | |
964 | ||
999e12bb AL |
965 | static void mv88w8618_pit_class_init(ObjectClass *klass, void *data) |
966 | { | |
39bffca2 | 967 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 968 | |
39bffca2 AL |
969 | dc->reset = mv88w8618_pit_reset; |
970 | dc->vmsd = &mv88w8618_pit_vmsd; | |
999e12bb AL |
971 | } |
972 | ||
8c43a6f0 | 973 | static const TypeInfo mv88w8618_pit_info = { |
4adc8541 | 974 | .name = TYPE_MV88W8618_PIT, |
39bffca2 AL |
975 | .parent = TYPE_SYS_BUS_DEVICE, |
976 | .instance_size = sizeof(mv88w8618_pit_state), | |
ece71994 | 977 | .instance_init = mv88w8618_pit_init, |
39bffca2 | 978 | .class_init = mv88w8618_pit_class_init, |
c88d6bde JK |
979 | }; |
980 | ||
24859b68 AZ |
981 | /* Flash config register offsets */ |
982 | #define MP_FLASHCFG_CFGR0 0x04 | |
983 | ||
5952b01c AF |
984 | #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg" |
985 | #define MV88W8618_FLASHCFG(obj) \ | |
986 | OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG) | |
987 | ||
24859b68 | 988 | typedef struct mv88w8618_flashcfg_state { |
5952b01c AF |
989 | /*< private >*/ |
990 | SysBusDevice parent_obj; | |
991 | /*< public >*/ | |
992 | ||
19b4a424 | 993 | MemoryRegion iomem; |
24859b68 AZ |
994 | uint32_t cfgr0; |
995 | } mv88w8618_flashcfg_state; | |
996 | ||
19b4a424 | 997 | static uint64_t mv88w8618_flashcfg_read(void *opaque, |
a8170e5e | 998 | hwaddr offset, |
19b4a424 | 999 | unsigned size) |
24859b68 AZ |
1000 | { |
1001 | mv88w8618_flashcfg_state *s = opaque; | |
1002 | ||
24859b68 AZ |
1003 | switch (offset) { |
1004 | case MP_FLASHCFG_CFGR0: | |
1005 | return s->cfgr0; | |
1006 | ||
1007 | default: | |
1008 | return 0; | |
1009 | } | |
1010 | } | |
1011 | ||
a8170e5e | 1012 | static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset, |
19b4a424 | 1013 | uint64_t value, unsigned size) |
24859b68 AZ |
1014 | { |
1015 | mv88w8618_flashcfg_state *s = opaque; | |
1016 | ||
24859b68 AZ |
1017 | switch (offset) { |
1018 | case MP_FLASHCFG_CFGR0: | |
1019 | s->cfgr0 = value; | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | ||
19b4a424 AK |
1024 | static const MemoryRegionOps mv88w8618_flashcfg_ops = { |
1025 | .read = mv88w8618_flashcfg_read, | |
1026 | .write = mv88w8618_flashcfg_write, | |
1027 | .endianness = DEVICE_NATIVE_ENDIAN, | |
24859b68 AZ |
1028 | }; |
1029 | ||
ece71994 | 1030 | static void mv88w8618_flashcfg_init(Object *obj) |
24859b68 | 1031 | { |
ece71994 | 1032 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
5952b01c | 1033 | mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev); |
24859b68 | 1034 | |
24859b68 | 1035 | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
ece71994 | 1036 | memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s, |
19b4a424 | 1037 | "musicpal-flashcfg", MP_FLASHCFG_SIZE); |
750ecd44 | 1038 | sysbus_init_mmio(dev, &s->iomem); |
24859b68 AZ |
1039 | } |
1040 | ||
d5b61ddd JK |
1041 | static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
1042 | .name = "mv88w8618_flashcfg", | |
1043 | .version_id = 1, | |
1044 | .minimum_version_id = 1, | |
d5b61ddd JK |
1045 | .fields = (VMStateField[]) { |
1046 | VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), | |
1047 | VMSTATE_END_OF_LIST() | |
1048 | } | |
1049 | }; | |
1050 | ||
999e12bb AL |
1051 | static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data) |
1052 | { | |
39bffca2 | 1053 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1054 | |
39bffca2 | 1055 | dc->vmsd = &mv88w8618_flashcfg_vmsd; |
999e12bb AL |
1056 | } |
1057 | ||
8c43a6f0 | 1058 | static const TypeInfo mv88w8618_flashcfg_info = { |
5952b01c | 1059 | .name = TYPE_MV88W8618_FLASHCFG, |
39bffca2 AL |
1060 | .parent = TYPE_SYS_BUS_DEVICE, |
1061 | .instance_size = sizeof(mv88w8618_flashcfg_state), | |
ece71994 | 1062 | .instance_init = mv88w8618_flashcfg_init, |
39bffca2 | 1063 | .class_init = mv88w8618_flashcfg_class_init, |
d5b61ddd JK |
1064 | }; |
1065 | ||
718ec0be | 1066 | /* Misc register offsets */ |
1067 | #define MP_MISC_BOARD_REVISION 0x18 | |
1068 | ||
1069 | #define MP_BOARD_REVISION 0x31 | |
1070 | ||
a86f200a PM |
1071 | typedef struct { |
1072 | SysBusDevice parent_obj; | |
1073 | MemoryRegion iomem; | |
1074 | } MusicPalMiscState; | |
1075 | ||
1076 | #define TYPE_MUSICPAL_MISC "musicpal-misc" | |
1077 | #define MUSICPAL_MISC(obj) \ | |
1078 | OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC) | |
1079 | ||
a8170e5e | 1080 | static uint64_t musicpal_misc_read(void *opaque, hwaddr offset, |
19b4a424 | 1081 | unsigned size) |
718ec0be | 1082 | { |
1083 | switch (offset) { | |
1084 | case MP_MISC_BOARD_REVISION: | |
1085 | return MP_BOARD_REVISION; | |
1086 | ||
1087 | default: | |
1088 | return 0; | |
1089 | } | |
1090 | } | |
1091 | ||
a8170e5e | 1092 | static void musicpal_misc_write(void *opaque, hwaddr offset, |
19b4a424 | 1093 | uint64_t value, unsigned size) |
718ec0be | 1094 | { |
1095 | } | |
1096 | ||
19b4a424 AK |
1097 | static const MemoryRegionOps musicpal_misc_ops = { |
1098 | .read = musicpal_misc_read, | |
1099 | .write = musicpal_misc_write, | |
1100 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1101 | }; |
1102 | ||
a86f200a | 1103 | static void musicpal_misc_init(Object *obj) |
718ec0be | 1104 | { |
a86f200a PM |
1105 | SysBusDevice *sd = SYS_BUS_DEVICE(obj); |
1106 | MusicPalMiscState *s = MUSICPAL_MISC(obj); | |
718ec0be | 1107 | |
64bde0f3 | 1108 | memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL, |
19b4a424 | 1109 | "musicpal-misc", MP_MISC_SIZE); |
a86f200a | 1110 | sysbus_init_mmio(sd, &s->iomem); |
718ec0be | 1111 | } |
1112 | ||
a86f200a PM |
1113 | static const TypeInfo musicpal_misc_info = { |
1114 | .name = TYPE_MUSICPAL_MISC, | |
1115 | .parent = TYPE_SYS_BUS_DEVICE, | |
1116 | .instance_init = musicpal_misc_init, | |
1117 | .instance_size = sizeof(MusicPalMiscState), | |
1118 | }; | |
1119 | ||
718ec0be | 1120 | /* WLAN register offsets */ |
1121 | #define MP_WLAN_MAGIC1 0x11c | |
1122 | #define MP_WLAN_MAGIC2 0x124 | |
1123 | ||
a8170e5e | 1124 | static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset, |
19b4a424 | 1125 | unsigned size) |
718ec0be | 1126 | { |
1127 | switch (offset) { | |
1128 | /* Workaround to allow loading the binary-only wlandrv.ko crap | |
1129 | * from the original Freecom firmware. */ | |
1130 | case MP_WLAN_MAGIC1: | |
1131 | return ~3; | |
1132 | case MP_WLAN_MAGIC2: | |
1133 | return -1; | |
1134 | ||
1135 | default: | |
1136 | return 0; | |
1137 | } | |
1138 | } | |
1139 | ||
a8170e5e | 1140 | static void mv88w8618_wlan_write(void *opaque, hwaddr offset, |
19b4a424 | 1141 | uint64_t value, unsigned size) |
718ec0be | 1142 | { |
1143 | } | |
1144 | ||
19b4a424 AK |
1145 | static const MemoryRegionOps mv88w8618_wlan_ops = { |
1146 | .read = mv88w8618_wlan_read, | |
1147 | .write =mv88w8618_wlan_write, | |
1148 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1149 | }; |
1150 | ||
7f7420a0 | 1151 | static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) |
718ec0be | 1152 | { |
19b4a424 | 1153 | MemoryRegion *iomem = g_new(MemoryRegion, 1); |
24859b68 | 1154 | |
64bde0f3 | 1155 | memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL, |
19b4a424 | 1156 | "musicpal-wlan", MP_WLAN_SIZE); |
7f7420a0 | 1157 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem); |
718ec0be | 1158 | } |
24859b68 | 1159 | |
718ec0be | 1160 | /* GPIO register offsets */ |
1161 | #define MP_GPIO_OE_LO 0x008 | |
1162 | #define MP_GPIO_OUT_LO 0x00c | |
1163 | #define MP_GPIO_IN_LO 0x010 | |
708afdf3 JK |
1164 | #define MP_GPIO_IER_LO 0x014 |
1165 | #define MP_GPIO_IMR_LO 0x018 | |
718ec0be | 1166 | #define MP_GPIO_ISR_LO 0x020 |
1167 | #define MP_GPIO_OE_HI 0x508 | |
1168 | #define MP_GPIO_OUT_HI 0x50c | |
1169 | #define MP_GPIO_IN_HI 0x510 | |
708afdf3 JK |
1170 | #define MP_GPIO_IER_HI 0x514 |
1171 | #define MP_GPIO_IMR_HI 0x518 | |
718ec0be | 1172 | #define MP_GPIO_ISR_HI 0x520 |
24859b68 AZ |
1173 | |
1174 | /* GPIO bits & masks */ | |
24859b68 | 1175 | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
24859b68 | 1176 | #define MP_GPIO_I2C_DATA_BIT 29 |
24859b68 AZ |
1177 | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1178 | ||
1179 | /* LCD brightness bits in GPIO_OE_HI */ | |
1180 | #define MP_OE_LCD_BRIGHTNESS 0x0007 | |
1181 | ||
7012d4b4 AF |
1182 | #define TYPE_MUSICPAL_GPIO "musicpal_gpio" |
1183 | #define MUSICPAL_GPIO(obj) \ | |
1184 | OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO) | |
1185 | ||
343ec8e4 | 1186 | typedef struct musicpal_gpio_state { |
7012d4b4 AF |
1187 | /*< private >*/ |
1188 | SysBusDevice parent_obj; | |
1189 | /*< public >*/ | |
1190 | ||
19b4a424 | 1191 | MemoryRegion iomem; |
343ec8e4 BC |
1192 | uint32_t lcd_brightness; |
1193 | uint32_t out_state; | |
1194 | uint32_t in_state; | |
708afdf3 JK |
1195 | uint32_t ier; |
1196 | uint32_t imr; | |
343ec8e4 | 1197 | uint32_t isr; |
343ec8e4 | 1198 | qemu_irq irq; |
708afdf3 | 1199 | qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
343ec8e4 BC |
1200 | } musicpal_gpio_state; |
1201 | ||
1202 | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { | |
1203 | int i; | |
1204 | uint32_t brightness; | |
1205 | ||
1206 | /* compute brightness ratio */ | |
1207 | switch (s->lcd_brightness) { | |
1208 | case 0x00000007: | |
1209 | brightness = 0; | |
1210 | break; | |
1211 | ||
1212 | case 0x00020000: | |
1213 | brightness = 1; | |
1214 | break; | |
1215 | ||
1216 | case 0x00020001: | |
1217 | brightness = 2; | |
1218 | break; | |
1219 | ||
1220 | case 0x00040000: | |
1221 | brightness = 3; | |
1222 | break; | |
1223 | ||
1224 | case 0x00010006: | |
1225 | brightness = 4; | |
1226 | break; | |
1227 | ||
1228 | case 0x00020005: | |
1229 | brightness = 5; | |
1230 | break; | |
1231 | ||
1232 | case 0x00040003: | |
1233 | brightness = 6; | |
1234 | break; | |
1235 | ||
1236 | case 0x00030004: | |
1237 | default: | |
1238 | brightness = 7; | |
1239 | } | |
1240 | ||
1241 | /* set lcd brightness GPIOs */ | |
49fedd0d | 1242 | for (i = 0; i <= 2; i++) { |
343ec8e4 | 1243 | qemu_set_irq(s->out[i], (brightness >> i) & 1); |
49fedd0d | 1244 | } |
343ec8e4 BC |
1245 | } |
1246 | ||
708afdf3 | 1247 | static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
343ec8e4 | 1248 | { |
243cd13c | 1249 | musicpal_gpio_state *s = opaque; |
708afdf3 JK |
1250 | uint32_t mask = 1 << pin; |
1251 | uint32_t delta = level << pin; | |
1252 | uint32_t old = s->in_state & mask; | |
343ec8e4 | 1253 | |
708afdf3 JK |
1254 | s->in_state &= ~mask; |
1255 | s->in_state |= delta; | |
343ec8e4 | 1256 | |
708afdf3 JK |
1257 | if ((old ^ delta) && |
1258 | ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { | |
1259 | s->isr = mask; | |
1260 | qemu_irq_raise(s->irq); | |
343ec8e4 | 1261 | } |
343ec8e4 BC |
1262 | } |
1263 | ||
a8170e5e | 1264 | static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset, |
19b4a424 | 1265 | unsigned size) |
24859b68 | 1266 | { |
243cd13c | 1267 | musicpal_gpio_state *s = opaque; |
343ec8e4 | 1268 | |
24859b68 | 1269 | switch (offset) { |
24859b68 | 1270 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
343ec8e4 | 1271 | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; |
24859b68 AZ |
1272 | |
1273 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1274 | return s->out_state & 0xFFFF; |
24859b68 | 1275 | case MP_GPIO_OUT_HI: |
343ec8e4 | 1276 | return s->out_state >> 16; |
24859b68 AZ |
1277 | |
1278 | case MP_GPIO_IN_LO: | |
343ec8e4 | 1279 | return s->in_state & 0xFFFF; |
24859b68 | 1280 | case MP_GPIO_IN_HI: |
343ec8e4 | 1281 | return s->in_state >> 16; |
24859b68 | 1282 | |
708afdf3 JK |
1283 | case MP_GPIO_IER_LO: |
1284 | return s->ier & 0xFFFF; | |
1285 | case MP_GPIO_IER_HI: | |
1286 | return s->ier >> 16; | |
1287 | ||
1288 | case MP_GPIO_IMR_LO: | |
1289 | return s->imr & 0xFFFF; | |
1290 | case MP_GPIO_IMR_HI: | |
1291 | return s->imr >> 16; | |
1292 | ||
24859b68 | 1293 | case MP_GPIO_ISR_LO: |
343ec8e4 | 1294 | return s->isr & 0xFFFF; |
24859b68 | 1295 | case MP_GPIO_ISR_HI: |
343ec8e4 | 1296 | return s->isr >> 16; |
24859b68 | 1297 | |
24859b68 AZ |
1298 | default: |
1299 | return 0; | |
1300 | } | |
1301 | } | |
1302 | ||
a8170e5e | 1303 | static void musicpal_gpio_write(void *opaque, hwaddr offset, |
19b4a424 | 1304 | uint64_t value, unsigned size) |
24859b68 | 1305 | { |
243cd13c | 1306 | musicpal_gpio_state *s = opaque; |
24859b68 AZ |
1307 | switch (offset) { |
1308 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ | |
343ec8e4 | 1309 | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
24859b68 | 1310 | (value & MP_OE_LCD_BRIGHTNESS); |
343ec8e4 | 1311 | musicpal_gpio_brightness_update(s); |
24859b68 AZ |
1312 | break; |
1313 | ||
1314 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1315 | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
24859b68 AZ |
1316 | break; |
1317 | case MP_GPIO_OUT_HI: | |
343ec8e4 BC |
1318 | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1319 | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | | |
1320 | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); | |
1321 | musicpal_gpio_brightness_update(s); | |
d074769c AZ |
1322 | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1323 | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); | |
24859b68 AZ |
1324 | break; |
1325 | ||
708afdf3 JK |
1326 | case MP_GPIO_IER_LO: |
1327 | s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); | |
1328 | break; | |
1329 | case MP_GPIO_IER_HI: | |
1330 | s->ier = (s->ier & 0xFFFF) | (value << 16); | |
1331 | break; | |
1332 | ||
1333 | case MP_GPIO_IMR_LO: | |
1334 | s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); | |
1335 | break; | |
1336 | case MP_GPIO_IMR_HI: | |
1337 | s->imr = (s->imr & 0xFFFF) | (value << 16); | |
1338 | break; | |
24859b68 AZ |
1339 | } |
1340 | } | |
1341 | ||
19b4a424 AK |
1342 | static const MemoryRegionOps musicpal_gpio_ops = { |
1343 | .read = musicpal_gpio_read, | |
1344 | .write = musicpal_gpio_write, | |
1345 | .endianness = DEVICE_NATIVE_ENDIAN, | |
718ec0be | 1346 | }; |
1347 | ||
d5b61ddd | 1348 | static void musicpal_gpio_reset(DeviceState *d) |
718ec0be | 1349 | { |
7012d4b4 | 1350 | musicpal_gpio_state *s = MUSICPAL_GPIO(d); |
30624c92 JK |
1351 | |
1352 | s->lcd_brightness = 0; | |
1353 | s->out_state = 0; | |
343ec8e4 | 1354 | s->in_state = 0xffffffff; |
708afdf3 JK |
1355 | s->ier = 0; |
1356 | s->imr = 0; | |
343ec8e4 BC |
1357 | s->isr = 0; |
1358 | } | |
1359 | ||
ece71994 | 1360 | static void musicpal_gpio_init(Object *obj) |
343ec8e4 | 1361 | { |
ece71994 | 1362 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
7012d4b4 AF |
1363 | DeviceState *dev = DEVICE(sbd); |
1364 | musicpal_gpio_state *s = MUSICPAL_GPIO(dev); | |
718ec0be | 1365 | |
7012d4b4 | 1366 | sysbus_init_irq(sbd, &s->irq); |
343ec8e4 | 1367 | |
ece71994 | 1368 | memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s, |
19b4a424 | 1369 | "musicpal-gpio", MP_GPIO_SIZE); |
7012d4b4 | 1370 | sysbus_init_mmio(sbd, &s->iomem); |
343ec8e4 | 1371 | |
7012d4b4 | 1372 | qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); |
708afdf3 | 1373 | |
7012d4b4 | 1374 | qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32); |
718ec0be | 1375 | } |
1376 | ||
d5b61ddd JK |
1377 | static const VMStateDescription musicpal_gpio_vmsd = { |
1378 | .name = "musicpal_gpio", | |
1379 | .version_id = 1, | |
1380 | .minimum_version_id = 1, | |
d5b61ddd JK |
1381 | .fields = (VMStateField[]) { |
1382 | VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), | |
1383 | VMSTATE_UINT32(out_state, musicpal_gpio_state), | |
1384 | VMSTATE_UINT32(in_state, musicpal_gpio_state), | |
1385 | VMSTATE_UINT32(ier, musicpal_gpio_state), | |
1386 | VMSTATE_UINT32(imr, musicpal_gpio_state), | |
1387 | VMSTATE_UINT32(isr, musicpal_gpio_state), | |
1388 | VMSTATE_END_OF_LIST() | |
1389 | } | |
1390 | }; | |
1391 | ||
999e12bb AL |
1392 | static void musicpal_gpio_class_init(ObjectClass *klass, void *data) |
1393 | { | |
39bffca2 | 1394 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1395 | |
39bffca2 AL |
1396 | dc->reset = musicpal_gpio_reset; |
1397 | dc->vmsd = &musicpal_gpio_vmsd; | |
999e12bb AL |
1398 | } |
1399 | ||
8c43a6f0 | 1400 | static const TypeInfo musicpal_gpio_info = { |
7012d4b4 | 1401 | .name = TYPE_MUSICPAL_GPIO, |
39bffca2 AL |
1402 | .parent = TYPE_SYS_BUS_DEVICE, |
1403 | .instance_size = sizeof(musicpal_gpio_state), | |
ece71994 | 1404 | .instance_init = musicpal_gpio_init, |
39bffca2 | 1405 | .class_init = musicpal_gpio_class_init, |
30624c92 JK |
1406 | }; |
1407 | ||
24859b68 | 1408 | /* Keyboard codes & masks */ |
7c6ce4ba | 1409 | #define KEY_RELEASED 0x80 |
24859b68 AZ |
1410 | #define KEY_CODE 0x7f |
1411 | ||
1412 | #define KEYCODE_TAB 0x0f | |
1413 | #define KEYCODE_ENTER 0x1c | |
1414 | #define KEYCODE_F 0x21 | |
1415 | #define KEYCODE_M 0x32 | |
1416 | ||
1417 | #define KEYCODE_EXTENDED 0xe0 | |
1418 | #define KEYCODE_UP 0x48 | |
1419 | #define KEYCODE_DOWN 0x50 | |
1420 | #define KEYCODE_LEFT 0x4b | |
1421 | #define KEYCODE_RIGHT 0x4d | |
1422 | ||
708afdf3 | 1423 | #define MP_KEY_WHEEL_VOL (1 << 0) |
343ec8e4 BC |
1424 | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1425 | #define MP_KEY_WHEEL_NAV (1 << 2) | |
1426 | #define MP_KEY_WHEEL_NAV_INV (1 << 3) | |
1427 | #define MP_KEY_BTN_FAVORITS (1 << 4) | |
1428 | #define MP_KEY_BTN_MENU (1 << 5) | |
1429 | #define MP_KEY_BTN_VOLUME (1 << 6) | |
1430 | #define MP_KEY_BTN_NAVIGATION (1 << 7) | |
1431 | ||
3bdf5327 AF |
1432 | #define TYPE_MUSICPAL_KEY "musicpal_key" |
1433 | #define MUSICPAL_KEY(obj) \ | |
1434 | OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY) | |
1435 | ||
343ec8e4 | 1436 | typedef struct musicpal_key_state { |
3bdf5327 AF |
1437 | /*< private >*/ |
1438 | SysBusDevice parent_obj; | |
1439 | /*< public >*/ | |
1440 | ||
4f5c9479 | 1441 | MemoryRegion iomem; |
343ec8e4 | 1442 | uint32_t kbd_extended; |
708afdf3 JK |
1443 | uint32_t pressed_keys; |
1444 | qemu_irq out[8]; | |
343ec8e4 BC |
1445 | } musicpal_key_state; |
1446 | ||
24859b68 AZ |
1447 | static void musicpal_key_event(void *opaque, int keycode) |
1448 | { | |
243cd13c | 1449 | musicpal_key_state *s = opaque; |
24859b68 | 1450 | uint32_t event = 0; |
343ec8e4 | 1451 | int i; |
24859b68 AZ |
1452 | |
1453 | if (keycode == KEYCODE_EXTENDED) { | |
343ec8e4 | 1454 | s->kbd_extended = 1; |
24859b68 AZ |
1455 | return; |
1456 | } | |
1457 | ||
49fedd0d | 1458 | if (s->kbd_extended) { |
24859b68 AZ |
1459 | switch (keycode & KEY_CODE) { |
1460 | case KEYCODE_UP: | |
343ec8e4 | 1461 | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
24859b68 AZ |
1462 | break; |
1463 | ||
1464 | case KEYCODE_DOWN: | |
343ec8e4 | 1465 | event = MP_KEY_WHEEL_NAV; |
24859b68 AZ |
1466 | break; |
1467 | ||
1468 | case KEYCODE_LEFT: | |
343ec8e4 | 1469 | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
24859b68 AZ |
1470 | break; |
1471 | ||
1472 | case KEYCODE_RIGHT: | |
343ec8e4 | 1473 | event = MP_KEY_WHEEL_VOL; |
24859b68 AZ |
1474 | break; |
1475 | } | |
49fedd0d | 1476 | } else { |
24859b68 AZ |
1477 | switch (keycode & KEY_CODE) { |
1478 | case KEYCODE_F: | |
343ec8e4 | 1479 | event = MP_KEY_BTN_FAVORITS; |
24859b68 AZ |
1480 | break; |
1481 | ||
1482 | case KEYCODE_TAB: | |
343ec8e4 | 1483 | event = MP_KEY_BTN_VOLUME; |
24859b68 AZ |
1484 | break; |
1485 | ||
1486 | case KEYCODE_ENTER: | |
343ec8e4 | 1487 | event = MP_KEY_BTN_NAVIGATION; |
24859b68 AZ |
1488 | break; |
1489 | ||
1490 | case KEYCODE_M: | |
343ec8e4 | 1491 | event = MP_KEY_BTN_MENU; |
24859b68 AZ |
1492 | break; |
1493 | } | |
7c6ce4ba | 1494 | /* Do not repeat already pressed buttons */ |
708afdf3 | 1495 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { |
7c6ce4ba | 1496 | event = 0; |
708afdf3 | 1497 | } |
7c6ce4ba | 1498 | } |
24859b68 | 1499 | |
7c6ce4ba | 1500 | if (event) { |
708afdf3 JK |
1501 | /* Raise GPIO pin first if repeating a key */ |
1502 | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { | |
1503 | for (i = 0; i <= 7; i++) { | |
1504 | if (event & (1 << i)) { | |
1505 | qemu_set_irq(s->out[i], 1); | |
1506 | } | |
1507 | } | |
1508 | } | |
1509 | for (i = 0; i <= 7; i++) { | |
1510 | if (event & (1 << i)) { | |
1511 | qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); | |
1512 | } | |
1513 | } | |
7c6ce4ba | 1514 | if (keycode & KEY_RELEASED) { |
708afdf3 | 1515 | s->pressed_keys &= ~event; |
7c6ce4ba | 1516 | } else { |
708afdf3 | 1517 | s->pressed_keys |= event; |
7c6ce4ba | 1518 | } |
24859b68 AZ |
1519 | } |
1520 | ||
343ec8e4 BC |
1521 | s->kbd_extended = 0; |
1522 | } | |
1523 | ||
ece71994 | 1524 | static void musicpal_key_init(Object *obj) |
343ec8e4 | 1525 | { |
ece71994 | 1526 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
3bdf5327 AF |
1527 | DeviceState *dev = DEVICE(sbd); |
1528 | musicpal_key_state *s = MUSICPAL_KEY(dev); | |
343ec8e4 | 1529 | |
ece71994 | 1530 | memory_region_init(&s->iomem, obj, "dummy", 0); |
3bdf5327 | 1531 | sysbus_init_mmio(sbd, &s->iomem); |
343ec8e4 BC |
1532 | |
1533 | s->kbd_extended = 0; | |
708afdf3 | 1534 | s->pressed_keys = 0; |
343ec8e4 | 1535 | |
3bdf5327 | 1536 | qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); |
343ec8e4 BC |
1537 | |
1538 | qemu_add_kbd_event_handler(musicpal_key_event, s); | |
24859b68 AZ |
1539 | } |
1540 | ||
d5b61ddd JK |
1541 | static const VMStateDescription musicpal_key_vmsd = { |
1542 | .name = "musicpal_key", | |
1543 | .version_id = 1, | |
1544 | .minimum_version_id = 1, | |
d5b61ddd JK |
1545 | .fields = (VMStateField[]) { |
1546 | VMSTATE_UINT32(kbd_extended, musicpal_key_state), | |
1547 | VMSTATE_UINT32(pressed_keys, musicpal_key_state), | |
1548 | VMSTATE_END_OF_LIST() | |
1549 | } | |
1550 | }; | |
1551 | ||
999e12bb AL |
1552 | static void musicpal_key_class_init(ObjectClass *klass, void *data) |
1553 | { | |
39bffca2 | 1554 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1555 | |
39bffca2 | 1556 | dc->vmsd = &musicpal_key_vmsd; |
999e12bb AL |
1557 | } |
1558 | ||
8c43a6f0 | 1559 | static const TypeInfo musicpal_key_info = { |
3bdf5327 | 1560 | .name = TYPE_MUSICPAL_KEY, |
39bffca2 AL |
1561 | .parent = TYPE_SYS_BUS_DEVICE, |
1562 | .instance_size = sizeof(musicpal_key_state), | |
ece71994 | 1563 | .instance_init = musicpal_key_init, |
39bffca2 | 1564 | .class_init = musicpal_key_class_init, |
d5b61ddd JK |
1565 | }; |
1566 | ||
24859b68 AZ |
1567 | static struct arm_boot_info musicpal_binfo = { |
1568 | .loader_start = 0x0, | |
1569 | .board_id = 0x20e, | |
1570 | }; | |
1571 | ||
3ef96221 | 1572 | static void musicpal_init(MachineState *machine) |
24859b68 | 1573 | { |
3ef96221 MA |
1574 | const char *kernel_filename = machine->kernel_filename; |
1575 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1576 | const char *initrd_filename = machine->initrd_filename; | |
f25608e9 | 1577 | ARMCPU *cpu; |
b47b50fa PB |
1578 | qemu_irq pic[32]; |
1579 | DeviceState *dev; | |
d074769c | 1580 | DeviceState *i2c_dev; |
343ec8e4 BC |
1581 | DeviceState *lcd_dev; |
1582 | DeviceState *key_dev; | |
d074769c AZ |
1583 | DeviceState *wm8750_dev; |
1584 | SysBusDevice *s; | |
a5c82852 | 1585 | I2CBus *i2c; |
b47b50fa | 1586 | int i; |
24859b68 | 1587 | unsigned long flash_size; |
751c6a17 | 1588 | DriveInfo *dinfo; |
19b4a424 AK |
1589 | MemoryRegion *address_space_mem = get_system_memory(); |
1590 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
1591 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
24859b68 | 1592 | |
ba1ba5cc | 1593 | cpu = ARM_CPU(cpu_create(machine->cpu_type)); |
24859b68 AZ |
1594 | |
1595 | /* For now we use a fixed - the original - RAM size */ | |
c8623c02 DM |
1596 | memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", |
1597 | MP_RAM_DEFAULT_SIZE); | |
19b4a424 | 1598 | memory_region_add_subregion(address_space_mem, 0, ram); |
24859b68 | 1599 | |
98a99ce0 | 1600 | memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, |
f8ed85ac | 1601 | &error_fatal); |
19b4a424 | 1602 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); |
24859b68 | 1603 | |
c7bd0fd9 | 1604 | dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
fcef61ec | 1605 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
b47b50fa | 1606 | for (i = 0; i < 32; i++) { |
067a3ddc | 1607 | pic[i] = qdev_get_gpio_in(dev, i); |
b47b50fa | 1608 | } |
4adc8541 | 1609 | sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], |
b47b50fa PB |
1610 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1611 | pic[MP_TIMER4_IRQ], NULL); | |
24859b68 | 1612 | |
9bca0edb | 1613 | if (serial_hd(0)) { |
39186d8a | 1614 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], |
9bca0edb | 1615 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
49fedd0d | 1616 | } |
9bca0edb | 1617 | if (serial_hd(1)) { |
39186d8a | 1618 | serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], |
9bca0edb | 1619 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); |
49fedd0d | 1620 | } |
24859b68 AZ |
1621 | |
1622 | /* Register flash */ | |
751c6a17 GH |
1623 | dinfo = drive_get(IF_PFLASH, 0, 0); |
1624 | if (dinfo) { | |
4be74634 | 1625 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); |
fa1d36df | 1626 | |
4be74634 | 1627 | flash_size = blk_getlength(blk); |
24859b68 AZ |
1628 | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1629 | flash_size != 32*1024*1024) { | |
c0dbca36 | 1630 | error_report("Invalid flash image size"); |
24859b68 AZ |
1631 | exit(1); |
1632 | } | |
1633 | ||
1634 | /* | |
1635 | * The original U-Boot accesses the flash at 0xFE000000 instead of | |
1636 | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the | |
1637 | * image is smaller than 32 MB. | |
1638 | */ | |
5f9fc5ad | 1639 | #ifdef TARGET_WORDS_BIGENDIAN |
940d5b13 | 1640 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, |
cfe5f011 | 1641 | "musicpal.flash", flash_size, |
ce14710f | 1642 | blk, 0x10000, |
24859b68 AZ |
1643 | MP_FLASH_SIZE_MAX / flash_size, |
1644 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
01e0451a | 1645 | 0x5555, 0x2AAA, 1); |
5f9fc5ad | 1646 | #else |
940d5b13 | 1647 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, |
cfe5f011 | 1648 | "musicpal.flash", flash_size, |
ce14710f | 1649 | blk, 0x10000, |
5f9fc5ad BS |
1650 | MP_FLASH_SIZE_MAX / flash_size, |
1651 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
01e0451a | 1652 | 0x5555, 0x2AAA, 0); |
5f9fc5ad BS |
1653 | #endif |
1654 | ||
24859b68 | 1655 | } |
5952b01c | 1656 | sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); |
24859b68 | 1657 | |
b47b50fa | 1658 | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
a77d90e6 | 1659 | dev = qdev_create(NULL, TYPE_MV88W8618_ETH); |
4c91cd28 | 1660 | qdev_set_nic_properties(dev, &nd_table[0]); |
e23a1b33 | 1661 | qdev_init_nofail(dev); |
1356b98d AF |
1662 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); |
1663 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | |
24859b68 | 1664 | |
b47b50fa | 1665 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
718ec0be | 1666 | |
a86f200a | 1667 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); |
343ec8e4 | 1668 | |
7012d4b4 AF |
1669 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, |
1670 | pic[MP_GPIO_IRQ]); | |
d04fba94 | 1671 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); |
a5c82852 | 1672 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); |
d074769c | 1673 | |
2cca58fd | 1674 | lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL); |
3bdf5327 | 1675 | key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL); |
343ec8e4 | 1676 | |
d074769c | 1677 | /* I2C read data */ |
708afdf3 JK |
1678 | qdev_connect_gpio_out(i2c_dev, 0, |
1679 | qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); | |
d074769c AZ |
1680 | /* I2C data */ |
1681 | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); | |
1682 | /* I2C clock */ | |
1683 | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); | |
1684 | ||
49fedd0d | 1685 | for (i = 0; i < 3; i++) { |
343ec8e4 | 1686 | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
49fedd0d | 1687 | } |
708afdf3 JK |
1688 | for (i = 0; i < 4; i++) { |
1689 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8)); | |
1690 | } | |
1691 | for (i = 4; i < 8; i++) { | |
1692 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15)); | |
1693 | } | |
24859b68 | 1694 | |
7ab14c5a | 1695 | wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); |
d436d4e7 | 1696 | dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); |
1356b98d | 1697 | s = SYS_BUS_DEVICE(dev); |
a8299ec1 | 1698 | object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), |
bd02b014 | 1699 | "wm8750", NULL); |
e23a1b33 | 1700 | qdev_init_nofail(dev); |
d074769c AZ |
1701 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); |
1702 | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | |
d074769c | 1703 | |
24859b68 AZ |
1704 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1705 | musicpal_binfo.kernel_filename = kernel_filename; | |
1706 | musicpal_binfo.kernel_cmdline = kernel_cmdline; | |
1707 | musicpal_binfo.initrd_filename = initrd_filename; | |
3aaa8dfa | 1708 | arm_load_kernel(cpu, &musicpal_binfo); |
24859b68 AZ |
1709 | } |
1710 | ||
e264d29d | 1711 | static void musicpal_machine_init(MachineClass *mc) |
f80f9ec9 | 1712 | { |
e264d29d EH |
1713 | mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; |
1714 | mc->init = musicpal_init; | |
4672cbd7 | 1715 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 1716 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
f80f9ec9 AL |
1717 | } |
1718 | ||
e264d29d | 1719 | DEFINE_MACHINE("musicpal", musicpal_machine_init) |
f80f9ec9 | 1720 | |
999e12bb AL |
1721 | static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data) |
1722 | { | |
7f7420a0 | 1723 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1724 | |
7f7420a0 | 1725 | dc->realize = mv88w8618_wlan_realize; |
999e12bb AL |
1726 | } |
1727 | ||
8c43a6f0 | 1728 | static const TypeInfo mv88w8618_wlan_info = { |
39bffca2 AL |
1729 | .name = "mv88w8618_wlan", |
1730 | .parent = TYPE_SYS_BUS_DEVICE, | |
1731 | .instance_size = sizeof(SysBusDevice), | |
1732 | .class_init = mv88w8618_wlan_class_init, | |
999e12bb AL |
1733 | }; |
1734 | ||
83f7d43a | 1735 | static void musicpal_register_types(void) |
b47b50fa | 1736 | { |
39bffca2 AL |
1737 | type_register_static(&mv88w8618_pic_info); |
1738 | type_register_static(&mv88w8618_pit_info); | |
1739 | type_register_static(&mv88w8618_flashcfg_info); | |
1740 | type_register_static(&mv88w8618_eth_info); | |
1741 | type_register_static(&mv88w8618_wlan_info); | |
1742 | type_register_static(&musicpal_lcd_info); | |
1743 | type_register_static(&musicpal_gpio_info); | |
1744 | type_register_static(&musicpal_key_info); | |
a86f200a | 1745 | type_register_static(&musicpal_misc_info); |
b47b50fa PB |
1746 | } |
1747 | ||
83f7d43a | 1748 | type_init(musicpal_register_types) |