[thirdparty/qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define PXA2XX_GPIO_BANKS	4

#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
    OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __func__, line);
        return;
    }

    bank = line >> 5;
    mask = 1U << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ctz32(diff);
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPSR\n");
        return 0;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPCR\n");
        return 0;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static void pxa2xx_gpio_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(sbd);
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
                          s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq0);
    sysbus_init_irq(sbd, &s->irq1);
    sysbus_init_irq(sbd, &s->irqX);
}

static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(dev, s->handler, s->lines);
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
    dc->vmsd = &vmstate_pxa2xx_gpio_regs;
    dc->realize = pxa2xx_gpio_realize;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = TYPE_PXA2XX_GPIO,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .instance_init = pxa2xx_gpio_initfn,
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
12b16722	10	#include "qemu/osdep.h"
33c11879	11	#include "cpu.h"
83c9f4ca	12	#include "hw/hw.h"
64552b6b	13	#include "hw/irq.h"
83c9f4ca	14	#include "hw/sysbus.h"
0d09e41a	15	#include "hw/arm/pxa.h"
03dd024f	16	#include "qemu/log.h"
0b8fa32f	17	#include "qemu/module.h"
c1713132 AZ	18
	19	#define PXA2XX_GPIO_BANKS 4
	20
922bb317 AF	21	#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
	22	#define PXA2XX_GPIO(obj) \
	23	OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
	24
0bb53337	25	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	26	struct PXA2xxGPIOInfo {
922bb317 AF	27	/< private >/
	28	SysBusDevice parent_obj;
	29	/< public >/
	30
55a8b801	31	MemoryRegion iomem;
0bb53337	32	qemu_irq irq0, irq1, irqX;
c1713132	33	int lines;
0bb53337	34	int ncpu;
95d42bb5	35	ARMCPU *cpu;
c1713132 AZ	36
	37	/* XXX: GNU C vectors are more suitable */
	38	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	39	uint32_t olevel[PXA2XX_GPIO_BANKS];
	40	uint32_t dir[PXA2XX_GPIO_BANKS];
	41	uint32_t rising[PXA2XX_GPIO_BANKS];
	42	uint32_t falling[PXA2XX_GPIO_BANKS];
	43	uint32_t status[PXA2XX_GPIO_BANKS];
	44	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	45
	46	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	47	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	48	qemu_irq read_notify;
c1713132 AZ	49	};
	50
	51	static struct {
	52	enum {
	53	GPIO_NONE,
	54	GPLR,
	55	GPSR,
	56	GPCR,
	57	GPDR,
	58	GRER,
	59	GFER,
	60	GEDR,
	61	GAFR_L,
	62	GAFR_U,
	63	} reg;
	64	int bank;
	65	} pxa2xx_gpio_regs[0x200] = {
	66	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	67	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	68	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	69
	70	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	71	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	72	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	73	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	74	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	75	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	76	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	77	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	78	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	79	};
	80
bc24a225	81	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	82	{
c1713132 AZ	83	if (s->status[0] & (1 << 0))
0bb53337	84	qemu_irq_raise(s->irq0);
c1713132	85	else
0bb53337	86	qemu_irq_lower(s->irq0);
c1713132 AZ	87
c1713132 AZ	88	if (s->status[0] & (1 << 1))
0bb53337	89	qemu_irq_raise(s->irq1);
c1713132	90	else
0bb53337	91	qemu_irq_lower(s->irq1);
c1713132 AZ	92
c1713132 AZ	93	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	94	qemu_irq_raise(s->irqX);
c1713132	95	else
0bb53337	96	qemu_irq_lower(s->irqX);
c1713132 AZ	97	}
	98
	99	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	100	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	101	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	102	};
	103
38641a52	104	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	105	{
bc24a225	106	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
259186a7	107	CPUState *cpu = CPU(s->cpu);
c1713132 AZ	108	int bank;
	109	uint32_t mask;
	110
	111	if (line >= s->lines) {
a89f364a	112	printf("%s: No GPIO pin %i\n", __func__, line);
c1713132 AZ	113	return;
	114	}
	115
	116	bank = line >> 5;
43a32ed6	117	mask = 1U << (line & 31);
c1713132 AZ	118
	119	if (level) {
	120	s->status[bank] \|= s->rising[bank] & mask &
	121	~s->ilevel[bank] & ~s->dir[bank];
	122	s->ilevel[bank] \|= mask;
	123	} else {
	124	s->status[bank] \|= s->falling[bank] & mask &
	125	s->ilevel[bank] & ~s->dir[bank];
	126	s->ilevel[bank] &= ~mask;
	127	}
	128
	129	if (s->status[bank] & mask)
	130	pxa2xx_gpio_irq_update(s);
	131
	132	/* Wake-up GPIOs */
259186a7	133	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
c3affe56	134	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
95d42bb5	135	}
c1713132 AZ	136	}
c1713132 AZ	137
bc24a225	138	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	139	uint32_t level, diff;
	140	int i, bit, line;
	141	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	142	level = s->olevel[i] & s->dir[i];
	143
	144	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
786a4ea8	145	bit = ctz32(diff);
c1713132	146	line = bit + 32 * i;
38641a52	147	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	148	}
	149
	150	s->prev_level[i] = level;
	151	}
	152	}
	153
a8170e5e	154	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
55a8b801	155	unsigned size)
c1713132	156	{
bc24a225	157	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	158	uint32_t ret;
c1713132 AZ	159	int bank;
c1713132 AZ	160	if (offset >= 0x200)
	161	return 0;
	162
	163	bank = pxa2xx_gpio_regs[offset].bank;
	164	switch (pxa2xx_gpio_regs[offset].reg) {
	165	case GPDR: /* GPIO Pin-Direction registers */
	166	return s->dir[bank];
	167
2b76bdc9	168	case GPSR: /* GPIO Pin-Output Set registers */
ab7a0f0b PM	169	qemu_log_mask(LOG_GUEST_ERROR,
	170	"pxa2xx GPIO: read from write only register GPSR\n");
	171	return 0;
2b76bdc9	172
e1dad5a6	173	case GPCR: /* GPIO Pin-Output Clear registers */
ab7a0f0b PM	174	qemu_log_mask(LOG_GUEST_ERROR,
	175	"pxa2xx GPIO: read from write only register GPCR\n");
	176	return 0;
e1dad5a6	177
c1713132 AZ	178	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	179	return s->rising[bank];
	180
	181	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	182	return s->falling[bank];
	183
	184	case GAFR_L: /* GPIO Alternate Function registers */
	185	return s->gafr[bank * 2];
	186
	187	case GAFR_U: /* GPIO Alternate Function registers */
	188	return s->gafr[bank * 2 + 1];
	189
	190	case GPLR: /* GPIO Pin-Level registers */
	191	ret = (s->olevel[bank] & s->dir[bank]) \|
	192	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	193	qemu_irq_raise(s->read_notify);
c1713132 AZ	194	return ret;
	195
	196	case GEDR: /* GPIO Edge Detect Status registers */
	197	return s->status[bank];
	198
	199	default:
a89f364a	200	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	201	}
	202
	203	return 0;
	204	}
	205
a8170e5e	206	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
55a8b801	207	uint64_t value, unsigned size)
c1713132	208	{
bc24a225	209	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	210	int bank;
c1713132 AZ	211	if (offset >= 0x200)
	212	return;
	213
	214	bank = pxa2xx_gpio_regs[offset].bank;
	215	switch (pxa2xx_gpio_regs[offset].reg) {
	216	case GPDR: /* GPIO Pin-Direction registers */
	217	s->dir[bank] = value;
	218	pxa2xx_gpio_handler_update(s);
	219	break;
	220
	221	case GPSR: /* GPIO Pin-Output Set registers */
	222	s->olevel[bank] \|= value;
	223	pxa2xx_gpio_handler_update(s);
	224	break;
	225
	226	case GPCR: /* GPIO Pin-Output Clear registers */
	227	s->olevel[bank] &= ~value;
	228	pxa2xx_gpio_handler_update(s);
	229	break;
	230
	231	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	232	s->rising[bank] = value;
	233	break;
	234
	235	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	236	s->falling[bank] = value;
	237	break;
	238
	239	case GAFR_L: /* GPIO Alternate Function registers */
	240	s->gafr[bank * 2] = value;
	241	break;
	242
	243	case GAFR_U: /* GPIO Alternate Function registers */
	244	s->gafr[bank * 2 + 1] = value;
	245	break;
	246
	247	case GEDR: /* GPIO Edge Detect Status registers */
	248	s->status[bank] &= ~value;
	249	pxa2xx_gpio_irq_update(s);
	250	break;
	251
	252	default:
a89f364a	253	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	254	}
	255	}
	256
55a8b801 BC	257	static const MemoryRegionOps pxa_gpio_ops = {
	258	.read = pxa2xx_gpio_read,
	259	.write = pxa2xx_gpio_write,
	260	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	261	};
c1713132 AZ	262
a8170e5e	263	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	264	ARMCPU cpu, DeviceState pic, int lines)
aa941b94	265	{
55e5c285	266	CPUState *cs = CPU(cpu);
0bb53337	267	DeviceState *dev;
aa941b94	268
922bb317	269	dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
0bb53337	270	qdev_prop_set_int32(dev, "lines", lines);
55e5c285	271	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
0bb53337	272	qdev_init_nofail(dev);
aa941b94	273
1356b98d AF	274	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	275	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
e1f8c729	276	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
1356b98d	277	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
e1f8c729	278	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
1356b98d	279	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
e1f8c729	280	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	281
0bb53337	282	return dev;
aa941b94 AZ	283	}
aa941b94 AZ	284
f79a7ff1	285	static void pxa2xx_gpio_initfn(Object *obj)
c1713132	286	{
f79a7ff1	287	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
922bb317 AF	288	DeviceState *dev = DEVICE(sbd);
922bb317 AF	289	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
c1713132	290
f79a7ff1 XZ	291	memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
f79a7ff1 XZ	292	s, "pxa2xx-gpio", 0x1000);
922bb317 AF	293	sysbus_init_mmio(sbd, &s->iomem);
	294	sysbus_init_irq(sbd, &s->irq0);
	295	sysbus_init_irq(sbd, &s->irq1);
	296	sysbus_init_irq(sbd, &s->irqX);
f79a7ff1	297	}
c1713132	298
f79a7ff1 XZ	299	static void pxa2xx_gpio_realize(DeviceState dev, Error *errp)
	300	{
	301	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	302
	303	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
	304
	305	qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
	306	qdev_init_gpio_out(dev, s->handler, s->lines);
c1713132 AZ	307	}
	308
	309	/*
	310	* Registers a callback to notify on GPLR reads. This normally
	311	* shouldn't be needed but it is used for the hack on Spitz machines.
	312	*/
0bb53337	313	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	314	{
922bb317 AF	315	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
922bb317 AF	316
c1713132	317	s->read_notify = handler;
c1713132	318	}
0bb53337 DES	319
	320	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	321	.name = "pxa2xx-gpio",
	322	.version_id = 1,
	323	.minimum_version_id = 1,
8f1e884b	324	.fields = (VMStateField[]) {
0bb53337 DES	325	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	326	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	327	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	328	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	329	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	330	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	331	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
166fa999	332	VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
0bb53337 DES	333	VMSTATE_END_OF_LIST(),
	334	},
	335	};
	336
999e12bb AL	337	static Property pxa2xx_gpio_properties[] = {
	338	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	339	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	340	DEFINE_PROP_END_OF_LIST(),
	341	};
	342
	343	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	344	{
39bffca2	345	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	346
39bffca2 AL	347	dc->desc = "PXA2xx GPIO controller";
39bffca2 AL	348	dc->props = pxa2xx_gpio_properties;
166fa999	349	dc->vmsd = &vmstate_pxa2xx_gpio_regs;
f79a7ff1	350	dc->realize = pxa2xx_gpio_realize;
999e12bb AL	351	}
999e12bb AL	352
8c43a6f0	353	static const TypeInfo pxa2xx_gpio_info = {
922bb317	354	.name = TYPE_PXA2XX_GPIO,
39bffca2 AL	355	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	356	.instance_size = sizeof(PXA2xxGPIOInfo),
f79a7ff1	357	.instance_init = pxa2xx_gpio_initfn,
39bffca2	358	.class_init = pxa2xx_gpio_class_init,
0bb53337 DES	359	};
0bb53337 DES	360
83f7d43a	361	static void pxa2xx_gpio_register_types(void)
0bb53337	362	{
39bffca2	363	type_register_static(&pxa2xx_gpio_info);
0bb53337	364	}
83f7d43a AF	365
83f7d43a AF	366	type_init(pxa2xx_gpio_register_types)