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Include qemu/module.h where needed, drop it from qemu-common.h
[thirdparty/qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a 32#include "hw/block/fdc.h"
da34e65c 33#include "qapi/error.h"
1de7afc9
PB		 34#include "qemu/error-report.h"
35#include "qemu/timer.h"
0d09e41a 36#include "hw/isa/isa.h"
83c9f4ca 37#include "hw/sysbus.h"
a92bd191 38#include "hw/block/block.h"
fa1d36df 39#include "sysemu/block-backend.h"
9c17d615
PB		 40#include "sysemu/blockdev.h"
41#include "sysemu/sysemu.h"
1de7afc9 42#include "qemu/log.h"
0b8fa32f 43#include "qemu/module.h"
1a5396d9 44#include "trace.h"
8977f3c1
FB		 45
46/********************************************************/
47/* debug Floppy devices */
8977f3c1 48
c691320f
JS		 49#define DEBUG_FLOPPY 0
50
001faf32 51#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 52 do { \
53 if (DEBUG_FLOPPY) { \
54 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
55 } \
56 } while (0)
8977f3c1 57
51e6e90e
KW		 58
59/********************************************************/
60/* qdev floppy bus */
61
62#define TYPE_FLOPPY_BUS "floppy-bus"
63#define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
64
65typedef struct FDCtrl FDCtrl;
394ea2ca
KW		 66typedef struct FDrive FDrive;
67static FDrive *get_drv(FDCtrl *fdctrl, int unit);
51e6e90e
KW		 68
69typedef struct FloppyBus {
70 BusState bus;
71 FDCtrl *fdc;
72} FloppyBus;
73
74static const TypeInfo floppy_bus_info = {
75 .name = TYPE_FLOPPY_BUS,
76 .parent = TYPE_BUS,
77 .instance_size = sizeof(FloppyBus),
78};
79
80static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
81{
82 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
83 bus->fdc = fdc;
84}
85
86
8977f3c1
FB		 87/********************************************************/
88/* Floppy drive emulation */
89
61a8d649
MA		 90typedef enum FDriveRate {
91 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
92 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
93 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
94 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
95} FDriveRate;
96
109c17bc
JS		 97typedef enum FDriveSize {
98 FDRIVE_SIZE_UNKNOWN,
99 FDRIVE_SIZE_350,
100 FDRIVE_SIZE_525,
101} FDriveSize;
102
61a8d649 103typedef struct FDFormat {
2da44dd0 104 FloppyDriveType drive;
61a8d649
MA		 105 uint8_t last_sect;
106 uint8_t max_track;
107 uint8_t max_head;
108 FDriveRate rate;
109} FDFormat;
110
109c17bc
JS		 111/* In many cases, the total sector size of a format is enough to uniquely
112 * identify it. However, there are some total sector collisions between
113 * formats of different physical size, and these are noted below by
114 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 115static const FDFormat fd_formats[] = {
116 /* First entry is default format */
117 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 118 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
119 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 120 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
121 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
122 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
123 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
124 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
125 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 126 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 127 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
128 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
129 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
130 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
131 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 132 /* 720 kB 3"1/2 floppy disks */
109c17bc 133 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 134 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
135 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
136 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
137 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
138 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 139 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 140 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 141 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 142 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
143 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 144 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 145 /* 720 kB 5"1/4 floppy disks */
109c17bc 146 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 147 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 148 /* 360 kB 5"1/4 floppy disks */
109c17bc 149 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 150 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
151 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
152 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 153 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 154 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
155 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 156 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 157 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 158 /* end */
2da44dd0 159 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 160};
161
109c17bc
JS		 162static FDriveSize drive_size(FloppyDriveType drive)
163{
164 switch (drive) {
165 case FLOPPY_DRIVE_TYPE_120:
166 return FDRIVE_SIZE_525;
167 case FLOPPY_DRIVE_TYPE_144:
168 case FLOPPY_DRIVE_TYPE_288:
169 return FDRIVE_SIZE_350;
170 default:
171 return FDRIVE_SIZE_UNKNOWN;
172 }
173}
174
cefec4f5
BS		 175#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
176#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
177
8977f3c1 178/* Will always be a fixed parameter for us */
f2d81b33
BS		 179#define FD_SECTOR_LEN 512
180#define FD_SECTOR_SC 2 /* Sector size code */
181#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1
FB		 182
183/* Floppy disk drive emulation */
5c02c033 184typedef enum FDiskFlags {
baca51fa 185 FDISK_DBL_SIDES = 0x01,
5c02c033 186} FDiskFlags;
baca51fa 187
394ea2ca 188struct FDrive {
844f65d6 189 FDCtrl *fdctrl;
4be74634 190 BlockBackend *blk;
a17c17a2 191 BlockConf *conf;
8977f3c1 192 /* Drive status */
2da44dd0 193 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 194 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 195 /* Position */
196 uint8_t head;
197 uint8_t track;
198 uint8_t sect;
8977f3c1 199 /* Media */
16c1e3ec 200 FloppyDriveType disk; /* Current disk type */
5c02c033 201 FDiskFlags flags;
8977f3c1
FB		 202 uint8_t last_sect; /* Nb sector per track */
203 uint8_t max_track; /* Nb of tracks */
baca51fa 204 uint16_t bps; /* Bytes per sector */
8977f3c1 205 uint8_t ro; /* Is read-only */
7d905f71 206 uint8_t media_changed; /* Is media changed */
844f65d6 207 uint8_t media_rate; /* Data rate of medium */
2e1280e8 208
d5d47efc 209 bool media_validated; /* Have we validated the media? */
394ea2ca 210};
8977f3c1 211
a73275dd
JS		 212
213static FloppyDriveType get_fallback_drive_type(FDrive *drv);
214
fd9bdbd3
JS		 215/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
216 * currently goes through some pains to keep seeks within the bounds
217 * established by last_sect and max_track. Correcting this is difficult,
218 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
219 *
220 * For now: allow empty drives to have large bounds so we can seek around,
221 * with the understanding that when a diskette is inserted, the bounds will
222 * properly tighten to match the geometry of that inserted medium.
223 */
224static void fd_empty_seek_hack(FDrive *drv)
225{
226 drv->last_sect = 0xFF;
227 drv->max_track = 0xFF;
228}
229
5c02c033 230static void fd_init(FDrive *drv)
8977f3c1
FB		 231{
232 /* Drive */
8977f3c1 233 drv->perpendicular = 0;
8977f3c1 234 /* Disk */
16c1e3ec 235 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 236 drv->last_sect = 0;
8977f3c1 237 drv->max_track = 0;
d5d47efc
JS		 238 drv->ro = true;
239 drv->media_changed = 1;
8977f3c1
FB		 240}
241
08388273
HP		 242#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
243
7859cb98 244static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 245 uint8_t last_sect, uint8_t num_sides)
8977f3c1 246{
08388273 247 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 248}
249
250/* Returns current position, in sectors, for given drive */
5c02c033 251static int fd_sector(FDrive *drv)
8977f3c1 252{
08388273
HP		 253 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
254 NUM_SIDES(drv));
8977f3c1
FB		 255}
256
a7a5b7c0
EB		 257/* Returns current position, in bytes, for given drive */
258static int fd_offset(FDrive *drv)
259{
260 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
261 return fd_sector(drv) << BDRV_SECTOR_BITS;
262}
263
77370520
BS		 264/* Seek to a new position:
265 * returns 0 if already on right track
266 * returns 1 if track changed
267 * returns 2 if track is invalid
268 * returns 3 if sector is invalid
269 * returns 4 if seek is disabled
270 */
5c02c033
BS		 271static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
272 int enable_seek)
8977f3c1
FB		 273{
274 uint32_t sector;
baca51fa
FB		 275 int ret;
276
277 if (track > drv->max_track ||
4f431960 278 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 279 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
280 head, track, sect, 1,
281 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
282 drv->max_track, drv->last_sect);
8977f3c1
FB		 283 return 2;
284 }
285 if (sect > drv->last_sect) {
ed5fd2cc
FB		 286 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
287 head, track, sect, 1,
288 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
289 drv->max_track, drv->last_sect);
8977f3c1
FB		 290 return 3;
291 }
08388273 292 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 293 ret = 0;
8977f3c1
FB		 294 if (sector != fd_sector(drv)) {
295#if 0
296 if (!enable_seek) {
cced7a13
BS		 297 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
298 " (max=%d %02x %02x)\n",
299 head, track, sect, 1, drv->max_track,
300 drv->last_sect);
8977f3c1
FB		 301 return 4;
302 }
303#endif
304 drv->head = head;
6be01b1e 305 if (drv->track != track) {
abb3e55b 306 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 307 drv->media_changed = 0;
308 }
4f431960 309 ret = 1;
6be01b1e 310 }
8977f3c1
FB		 311 drv->track = track;
312 drv->sect = sect;
8977f3c1
FB		 313 }
314
abb3e55b 315 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 316 ret = 2;
317 }
318
baca51fa 319 return ret;
8977f3c1
FB		 320}
321
322/* Set drive back to track 0 */
5c02c033 323static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 324{
325 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 326 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 327}
328
d5d47efc
JS		 329/**
330 * Determine geometry based on inserted diskette.
331 * Will not operate on an empty drive.
332 *
333 * @return: 0 on success, -1 if the drive is empty.
334 */
335static int pick_geometry(FDrive *drv)
9a972233 336{
21862658 337 BlockBackend *blk = drv->blk;
9a972233
JS		 338 const FDFormat *parse;
339 uint64_t nb_sectors, size;
f31937aa
JS		 340 int i;
341 int match, size_match, type_match;
342 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 343
d5d47efc 344 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 345 if (!drv->blk || !blk_is_inserted(drv->blk) ||
346 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
347 {
d5d47efc
JS		 348 return -1;
349 }
350
f31937aa
JS		 351 /* We need to determine the likely geometry of the inserted medium.
352 * In order of preference, we look for:
353 * (1) The same drive type and number of sectors,
354 * (2) The same diskette size and number of sectors,
355 * (3) The same drive type.
356 *
357 * In all cases, matches that occur higher in the drive table will take
358 * precedence over matches that occur later in the table.
359 */
9a972233 360 blk_get_geometry(blk, &nb_sectors);
f31937aa 361 match = size_match = type_match = -1;
9a972233
JS		 362 for (i = 0; ; i++) {
363 parse = &fd_formats[i];
2da44dd0 364 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 365 break;
366 }
f31937aa
JS		 367 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
368 if (nb_sectors == size) {
369 if (magic || parse->drive == drv->drive) {
370 /* (1) perfect match -- nb_sectors and drive type */
371 goto out;
372 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
373 /* (2) size match -- nb_sectors and physical medium size */
374 match = (match == -1) ? i : match;
375 } else {
376 /* This is suspicious -- Did the user misconfigure? */
377 size_match = (size_match == -1) ? i : size_match;
9a972233 378 }
f31937aa
JS		 379 } else if (type_match == -1) {
380 if ((parse->drive == drv->drive) ||
381 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
382 /* (3) type match -- nb_sectors mismatch, but matches the type
383 * specified explicitly by the user, or matches the fallback
384 * default type when using the drive autodetect mechanism */
385 type_match = i;
9a972233
JS		 386 }
387 }
388 }
f31937aa
JS		 389
390 /* No exact match found */
9a972233 391 if (match == -1) {
f31937aa
JS		 392 if (size_match != -1) {
393 parse = &fd_formats[size_match];
394 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
395 "but inserted medium appears to be a "
c691320f 396 "%"PRId64" sector '%s' type\n",
977c736f 397 FloppyDriveType_str(drv->drive),
f31937aa 398 nb_sectors,
977c736f 399 FloppyDriveType_str(parse->drive));
9a972233 400 }
329b7291 401 assert(type_match != -1 && "misconfigured fd_format");
f31937aa 402 match = type_match;
9a972233 403 }
f31937aa
JS		 404 parse = &(fd_formats[match]);
405
406 out:
21862658
JS		 407 if (parse->max_head == 0) {
408 drv->flags &= ~FDISK_DBL_SIDES;
409 } else {
410 drv->flags |= FDISK_DBL_SIDES;
411 }
412 drv->max_track = parse->max_track;
413 drv->last_sect = parse->last_sect;
d5d47efc 414 drv->disk = parse->drive;
21862658 415 drv->media_rate = parse->rate;
d5d47efc
JS		 416 return 0;
417}
418
419static void pick_drive_type(FDrive *drv)
420{
fff4687b
JS		 421 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
422 return;
423 }
424
d5d47efc
JS		 425 if (pick_geometry(drv) == 0) {
426 drv->drive = drv->disk;
427 } else {
a73275dd 428 drv->drive = get_fallback_drive_type(drv);
d5d47efc 429 }
fff4687b
JS		 430
431 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 432}
433
8977f3c1 434/* Revalidate a disk drive after a disk change */
5c02c033 435static void fd_revalidate(FDrive *drv)
8977f3c1 436{
d5d47efc
JS		 437 int rc;
438
8977f3c1 439 FLOPPY_DPRINTF("revalidate\n");
4be74634 440 if (drv->blk != NULL) {
21862658 441 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 442 if (!blk_is_inserted(drv->blk)) {
cfb08fba 443 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 444 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 445 fd_empty_seek_hack(drv);
d5d47efc
JS		 446 } else if (!drv->media_validated) {
447 rc = pick_geometry(drv);
448 if (rc) {
449 FLOPPY_DPRINTF("Could not validate floppy drive media");
450 } else {
451 drv->media_validated = true;
452 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
453 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
454 drv->max_track, drv->last_sect,
455 drv->ro ? "ro" : "rw");
456 }
4f431960 457 }
8977f3c1 458 } else {
cfb08fba 459 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 460 drv->last_sect = 0;
4f431960
JM		 461 drv->max_track = 0;
462 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 463 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
464 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 465 }
caed8802
FB		 466}
467
39829a01 468static void fd_change_cb(void *opaque, bool load, Error **errp)
394ea2ca
KW		 469{
470 FDrive *drive = opaque;
a17c17a2
KW		 471
472 if (!load) {
473 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
474 } else {
ceff3e1f
MZ		 475 if (!blkconf_apply_backend_options(drive->conf,
476 blk_is_read_only(drive->blk), false,
477 errp)) {
a17c17a2
KW		 478 return;
479 }
480 }
394ea2ca
KW		 481
482 drive->media_changed = 1;
483 drive->media_validated = false;
484 fd_revalidate(drive);
485}
486
487static const BlockDevOps fd_block_ops = {
488 .change_media_cb = fd_change_cb,
489};
490
491
492#define TYPE_FLOPPY_DRIVE "floppy"
493#define FLOPPY_DRIVE(obj) \
494 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
495
496typedef struct FloppyDrive {
a92bd191
KW		 497 DeviceState qdev;
498 uint32_t unit;
499 BlockConf conf;
500 FloppyDriveType type;
394ea2ca
KW		 501} FloppyDrive;
502
503static Property floppy_drive_properties[] = {
504 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
a92bd191 505 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
85bbd1e7 506 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
a92bd191
KW		 507 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
508 FloppyDriveType),
394ea2ca
KW		 509 DEFINE_PROP_END_OF_LIST(),
510};
511
ae34fce5 512static void floppy_drive_realize(DeviceState *qdev, Error **errp)
394ea2ca
KW		 513{
514 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
515 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
516 FDrive *drive;
a92bd191 517 int ret;
394ea2ca
KW		 518
519 if (dev->unit == -1) {
520 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
521 drive = get_drv(bus->fdc, dev->unit);
522 if (!drive->blk) {
523 break;
524 }
525 }
526 }
527
528 if (dev->unit >= MAX_FD) {
ae34fce5
MZ		 529 error_setg(errp, "Can't create floppy unit %d, bus supports "
530 "only %d units", dev->unit, MAX_FD);
531 return;
394ea2ca
KW		 532 }
533
394ea2ca 534 drive = get_drv(bus->fdc, dev->unit);
394ea2ca 535 if (drive->blk) {
ae34fce5
MZ		 536 error_setg(errp, "Floppy unit %d is in use", dev->unit);
537 return;
a92bd191
KW		 538 }
539
540 if (!dev->conf.blk) {
394ea2ca 541 /* Anonymous BlockBackend for an empty drive */
d861ab3a 542 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
a92bd191
KW		 543 ret = blk_attach_dev(dev->conf.blk, qdev);
544 assert(ret == 0);
394ea2ca
KW		 545 }
546
a92bd191
KW		 547 blkconf_blocksizes(&dev->conf);
548 if (dev->conf.logical_block_size != 512 ||
549 dev->conf.physical_block_size != 512)
550 {
ae34fce5
MZ		 551 error_setg(errp, "Physical and logical block size must "
552 "be 512 for floppy");
553 return;
a92bd191
KW		 554 }
555
556 /* rerror/werror aren't supported by fdc and therefore not even registered
557 * with qdev. So set the defaults manually before they are used in
558 * blkconf_apply_backend_options(). */
559 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
560 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
a17c17a2 561
ceff3e1f
MZ		 562 if (!blkconf_apply_backend_options(&dev->conf,
563 blk_is_read_only(dev->conf.blk),
564 false, errp)) {
ae34fce5 565 return;
a17c17a2 566 }
a92bd191
KW		 567
568 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
569 * for empty drives. */
570 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
571 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 572 error_setg(errp, "fdc doesn't support drive option werror");
573 return;
394ea2ca 574 }
a92bd191 575 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
ae34fce5
MZ		 576 error_setg(errp, "fdc doesn't support drive option rerror");
577 return;
a92bd191
KW		 578 }
579
a17c17a2 580 drive->conf = &dev->conf;
a92bd191
KW		 581 drive->blk = dev->conf.blk;
582 drive->fdctrl = bus->fdc;
583
584 fd_init(drive);
585 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
586
587 /* Keep 'type' qdev property and FDrive->drive in sync */
588 drive->drive = dev->type;
589 pick_drive_type(drive);
590 dev->type = drive->drive;
591
394ea2ca 592 fd_revalidate(drive);
394ea2ca
KW		 593}
594
595static void floppy_drive_class_init(ObjectClass *klass, void *data)
596{
597 DeviceClass *k = DEVICE_CLASS(klass);
ae34fce5 598 k->realize = floppy_drive_realize;
394ea2ca
KW		 599 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
600 k->bus_type = TYPE_FLOPPY_BUS;
601 k->props = floppy_drive_properties;
602 k->desc = "virtual floppy drive";
603}
604
605static const TypeInfo floppy_drive_info = {
606 .name = TYPE_FLOPPY_DRIVE,
607 .parent = TYPE_DEVICE,
608 .instance_size = sizeof(FloppyDrive),
609 .class_init = floppy_drive_class_init,
610};
611
8977f3c1 612/********************************************************/
4b19ec0c 613/* Intel 82078 floppy disk controller emulation */
8977f3c1 614
5c02c033 615static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 616static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 617static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 618 int dma_pos, int dma_len);
d497d534 619static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 620static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 621
622static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
623static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
624static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
625static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
626static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
627static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
628static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
629static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
630static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
631static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
632static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 633static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 634
8977f3c1
FB		 635enum {
636 FD_DIR_WRITE = 0,
637 FD_DIR_READ = 1,
638 FD_DIR_SCANE = 2,
639 FD_DIR_SCANL = 3,
640 FD_DIR_SCANH = 4,
7ea004ed 641 FD_DIR_VERIFY = 5,
8977f3c1
FB		 642};
643
644enum {
b9b3d225
BS		 645 FD_STATE_MULTI = 0x01, /* multi track flag */
646 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 647};
648
9fea808a 649enum {
8c6a4d77
BS		 650 FD_REG_SRA = 0x00,
651 FD_REG_SRB = 0x01,
9fea808a
BS		 652 FD_REG_DOR = 0x02,
653 FD_REG_TDR = 0x03,
654 FD_REG_MSR = 0x04,
655 FD_REG_DSR = 0x04,
656 FD_REG_FIFO = 0x05,
657 FD_REG_DIR = 0x07,
a758f8f4 658 FD_REG_CCR = 0x07,
9fea808a
BS		 659};
660
661enum {
65cef780 662 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 663 FD_CMD_SPECIFY = 0x03,
664 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 665 FD_CMD_WRITE = 0x05,
666 FD_CMD_READ = 0x06,
9fea808a
BS		 667 FD_CMD_RECALIBRATE = 0x07,
668 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 669 FD_CMD_WRITE_DELETED = 0x09,
670 FD_CMD_READ_ID = 0x0a,
671 FD_CMD_READ_DELETED = 0x0c,
672 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 673 FD_CMD_DUMPREG = 0x0e,
674 FD_CMD_SEEK = 0x0f,
675 FD_CMD_VERSION = 0x10,
65cef780 676 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 677 FD_CMD_PERPENDICULAR_MODE = 0x12,
678 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 679 FD_CMD_LOCK = 0x14,
680 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 681 FD_CMD_POWERDOWN_MODE = 0x17,
682 FD_CMD_PART_ID = 0x18,
65cef780
BS		 683 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
684 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 685 FD_CMD_SAVE = 0x2e,
9fea808a 686 FD_CMD_OPTION = 0x33,
bb350a5e 687 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 688 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
689 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 690 FD_CMD_FORMAT_AND_WRITE = 0xcd,
691 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
692};
693
694enum {
695 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
696 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
697 FD_CONFIG_POLL = 0x10, /* Poll enabled */
698 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
699 FD_CONFIG_EIS = 0x40, /* No implied seeks */
700};
701
702enum {
2fee0088
PH		 703 FD_SR0_DS0 = 0x01,
704 FD_SR0_DS1 = 0x02,
705 FD_SR0_HEAD = 0x04,
9fea808a
BS		 706 FD_SR0_EQPMT = 0x10,
707 FD_SR0_SEEK = 0x20,
708 FD_SR0_ABNTERM = 0x40,
709 FD_SR0_INVCMD = 0x80,
710 FD_SR0_RDYCHG = 0xc0,
711};
712
77370520 713enum {
844f65d6 714 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 715 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 716 FD_SR1_EC = 0x80, /* End of cylinder */
717};
718
719enum {
720 FD_SR2_SNS = 0x04, /* Scan not satisfied */
721 FD_SR2_SEH = 0x08, /* Scan equal hit */
722};
723
8c6a4d77
BS		 724enum {
725 FD_SRA_DIR = 0x01,
726 FD_SRA_nWP = 0x02,
727 FD_SRA_nINDX = 0x04,
728 FD_SRA_HDSEL = 0x08,
729 FD_SRA_nTRK0 = 0x10,
730 FD_SRA_STEP = 0x20,
731 FD_SRA_nDRV2 = 0x40,
732 FD_SRA_INTPEND = 0x80,
733};
734
735enum {
736 FD_SRB_MTR0 = 0x01,
737 FD_SRB_MTR1 = 0x02,
738 FD_SRB_WGATE = 0x04,
739 FD_SRB_RDATA = 0x08,
740 FD_SRB_WDATA = 0x10,
741 FD_SRB_DR0 = 0x20,
742};
743
9fea808a 744enum {
78ae820c
BS		 745#if MAX_FD == 4
746 FD_DOR_SELMASK = 0x03,
747#else
9fea808a 748 FD_DOR_SELMASK = 0x01,
78ae820c 749#endif
9fea808a
BS		 750 FD_DOR_nRESET = 0x04,
751 FD_DOR_DMAEN = 0x08,
752 FD_DOR_MOTEN0 = 0x10,
753 FD_DOR_MOTEN1 = 0x20,
754 FD_DOR_MOTEN2 = 0x40,
755 FD_DOR_MOTEN3 = 0x80,
756};
757
758enum {
78ae820c 759#if MAX_FD == 4
9fea808a 760 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 761#else
762 FD_TDR_BOOTSEL = 0x04,
763#endif
9fea808a
BS		 764};
765
766enum {
767 FD_DSR_DRATEMASK= 0x03,
768 FD_DSR_PWRDOWN = 0x40,
769 FD_DSR_SWRESET = 0x80,
770};
771
772enum {
773 FD_MSR_DRV0BUSY = 0x01,
774 FD_MSR_DRV1BUSY = 0x02,
775 FD_MSR_DRV2BUSY = 0x04,
776 FD_MSR_DRV3BUSY = 0x08,
777 FD_MSR_CMDBUSY = 0x10,
778 FD_MSR_NONDMA = 0x20,
779 FD_MSR_DIO = 0x40,
780 FD_MSR_RQM = 0x80,
781};
782
783enum {
784 FD_DIR_DSKCHG = 0x80,
785};
786
85d291a0
KW		 787/*
788 * See chapter 5.0 "Controller phases" of the spec:
789 *
790 * Command phase:
791 * The host writes a command and its parameters into the FIFO. The command
792 * phase is completed when all parameters for the command have been supplied,
793 * and execution phase is entered.
794 *
795 * Execution phase:
796 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
797 * contains the payload now, otherwise it's unused. When all bytes of the
798 * required data have been transferred, the state is switched to either result
799 * phase (if the command produces status bytes) or directly back into the
800 * command phase for the next command.
801 *
802 * Result phase:
803 * The host reads out the FIFO, which contains one or more result bytes now.
804 */
805enum {
806 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
807 FD_PHASE_RECONSTRUCT = 0,
808
809 FD_PHASE_COMMAND = 1,
810 FD_PHASE_EXECUTION = 2,
811 FD_PHASE_RESULT = 3,
812};
813
8977f3c1 814#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 815#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 816
5c02c033 817struct FDCtrl {
dc6c1b37 818 MemoryRegion iomem;
d537cf6c 819 qemu_irq irq;
4b19ec0c 820 /* Controller state */
ed5fd2cc 821 QEMUTimer *result_timer;
242cca4f 822 int dma_chann;
85d291a0 823 uint8_t phase;
c8a35f1c 824 IsaDma *dma;
242cca4f
BS		 825 /* Controller's identification */
826 uint8_t version;
827 /* HW */
8c6a4d77
BS		 828 uint8_t sra;
829 uint8_t srb;
368df94d 830 uint8_t dor;
d7a6c270 831 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 832 uint8_t tdr;
b9b3d225 833 uint8_t dsr;
368df94d 834 uint8_t msr;
8977f3c1 835 uint8_t cur_drv;
77370520
BS		 836 uint8_t status0;
837 uint8_t status1;
838 uint8_t status2;
8977f3c1 839 /* Command FIFO */
33f00271 840 uint8_t *fifo;
d7a6c270 841 int32_t fifo_size;
8977f3c1
FB		 842 uint32_t data_pos;
843 uint32_t data_len;
844 uint8_t data_state;
845 uint8_t data_dir;
890fa6be 846 uint8_t eot; /* last wanted sector */
8977f3c1 847 /* States kept only to be returned back */
8977f3c1
FB		 848 /* precompensation */
849 uint8_t precomp_trk;
850 uint8_t config;
851 uint8_t lock;
852 /* Power down config (also with status regB access mode */
853 uint8_t pwrd;
854 /* Floppy drives */
51e6e90e 855 FloppyBus bus;
d7a6c270 856 uint8_t num_floppies;
5c02c033 857 FDrive drives[MAX_FD];
a92bd191
KW		 858 struct {
859 BlockBackend *blk;
860 FloppyDriveType type;
861 } qdev_for_drives[MAX_FD];
f2d81b33 862 int reset_sensei;
09c6d585 863 uint32_t check_media_rate;
a73275dd 864 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 865 /* Timers state */
866 uint8_t timer0;
867 uint8_t timer1;
e305a165 868 PortioList portio_list;
baca51fa
FB		 869};
870
a73275dd
JS		 871static FloppyDriveType get_fallback_drive_type(FDrive *drv)
872{
873 return drv->fdctrl->fallback;
874}
875
19d46d71 876#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 877#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
878
5c02c033 879typedef struct FDCtrlSysBus {
dd3be742
HT		 880 /*< private >*/
881 SysBusDevice parent_obj;
882 /*< public >*/
883
5c02c033
BS		 884 struct FDCtrl state;
885} FDCtrlSysBus;
8baf73ad 886
020c8e76
AF		 887#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
888
5c02c033 889typedef struct FDCtrlISABus {
020c8e76
AF		 890 ISADevice parent_obj;
891
c9ae703d
HP		 892 uint32_t iobase;
893 uint32_t irq;
894 uint32_t dma;
5c02c033 895 struct FDCtrl state;
1ca4d09a
GN		 896 int32_t bootindexA;
897 int32_t bootindexB;
5c02c033 898} FDCtrlISABus;
8baf73ad 899
baca51fa
FB		 900static uint32_t fdctrl_read (void *opaque, uint32_t reg)
901{
5c02c033 902 FDCtrl *fdctrl = opaque;
baca51fa
FB		 903 uint32_t retval;
904
a18e67f5 905 reg &= 7;
e64d7d59 906 switch (reg) {
8c6a4d77
BS		 907 case FD_REG_SRA:
908 retval = fdctrl_read_statusA(fdctrl);
4f431960 909 break;
8c6a4d77 910 case FD_REG_SRB:
4f431960
JM		 911 retval = fdctrl_read_statusB(fdctrl);
912 break;
9fea808a 913 case FD_REG_DOR:
4f431960
JM		 914 retval = fdctrl_read_dor(fdctrl);
915 break;
9fea808a 916 case FD_REG_TDR:
baca51fa 917 retval = fdctrl_read_tape(fdctrl);
4f431960 918 break;
9fea808a 919 case FD_REG_MSR:
baca51fa 920 retval = fdctrl_read_main_status(fdctrl);
4f431960 921 break;
9fea808a 922 case FD_REG_FIFO:
baca51fa 923 retval = fdctrl_read_data(fdctrl);
4f431960 924 break;
9fea808a 925 case FD_REG_DIR:
baca51fa 926 retval = fdctrl_read_dir(fdctrl);
4f431960 927 break;
a541f297 928 default:
4f431960
JM		 929 retval = (uint32_t)(-1);
930 break;
a541f297 931 }
1a5396d9 932 trace_fdc_ioport_read(reg, retval);
baca51fa
FB		 933
934 return retval;
935}
936
937static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
938{
5c02c033 939 FDCtrl *fdctrl = opaque;
baca51fa 940
a18e67f5 941 reg &= 7;
1a5396d9 942 trace_fdc_ioport_write(reg, value);
e64d7d59 943 switch (reg) {
9fea808a 944 case FD_REG_DOR:
4f431960
JM		 945 fdctrl_write_dor(fdctrl, value);
946 break;
9fea808a 947 case FD_REG_TDR:
baca51fa 948 fdctrl_write_tape(fdctrl, value);
4f431960 949 break;
9fea808a 950 case FD_REG_DSR:
baca51fa 951 fdctrl_write_rate(fdctrl, value);
4f431960 952 break;
9fea808a 953 case FD_REG_FIFO:
baca51fa 954 fdctrl_write_data(fdctrl, value);
4f431960 955 break;
a758f8f4
HP		 956 case FD_REG_CCR:
957 fdctrl_write_ccr(fdctrl, value);
958 break;
a541f297 959 default:
4f431960 960 break;
a541f297 961 }
baca51fa
FB		 962}
963
a8170e5e 964static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 965 unsigned ize)
62a46c61 966{
5dcb6b91 967 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 968}
969
a8170e5e 970static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 971 uint64_t value, unsigned size)
62a46c61 972{
5dcb6b91 973 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 974}
975
dc6c1b37
AK		 976static const MemoryRegionOps fdctrl_mem_ops = {
977 .read = fdctrl_read_mem,
978 .write = fdctrl_write_mem,
979 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 980};
981
dc6c1b37
AK		 982static const MemoryRegionOps fdctrl_mem_strict_ops = {
983 .read = fdctrl_read_mem,
984 .write = fdctrl_write_mem,
985 .endianness = DEVICE_NATIVE_ENDIAN,
986 .valid = {
987 .min_access_size = 1,
988 .max_access_size = 1,
989 },
7c560456
BS		 990};
991
7d905f71
JW		 992static bool fdrive_media_changed_needed(void *opaque)
993{
994 FDrive *drive = opaque;
995
abb3e55b 996 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 997}
998
999static const VMStateDescription vmstate_fdrive_media_changed = {
1000 .name = "fdrive/media_changed",
1001 .version_id = 1,
1002 .minimum_version_id = 1,
5cd8cada 1003 .needed = fdrive_media_changed_needed,
d49805ae 1004 .fields = (VMStateField[]) {
7d905f71
JW		 1005 VMSTATE_UINT8(media_changed, FDrive),
1006 VMSTATE_END_OF_LIST()
1007 }
1008};
1009
844f65d6
HP		 1010static bool fdrive_media_rate_needed(void *opaque)
1011{
1012 FDrive *drive = opaque;
1013
1014 return drive->fdctrl->check_media_rate;
1015}
1016
1017static const VMStateDescription vmstate_fdrive_media_rate = {
1018 .name = "fdrive/media_rate",
1019 .version_id = 1,
1020 .minimum_version_id = 1,
5cd8cada 1021 .needed = fdrive_media_rate_needed,
d49805ae 1022 .fields = (VMStateField[]) {
844f65d6
HP		 1023 VMSTATE_UINT8(media_rate, FDrive),
1024 VMSTATE_END_OF_LIST()
1025 }
1026};
1027
c0b92f30
PD		 1028static bool fdrive_perpendicular_needed(void *opaque)
1029{
1030 FDrive *drive = opaque;
1031
1032 return drive->perpendicular != 0;
1033}
1034
1035static const VMStateDescription vmstate_fdrive_perpendicular = {
1036 .name = "fdrive/perpendicular",
1037 .version_id = 1,
1038 .minimum_version_id = 1,
5cd8cada 1039 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 1040 .fields = (VMStateField[]) {
1041 VMSTATE_UINT8(perpendicular, FDrive),
1042 VMSTATE_END_OF_LIST()
1043 }
1044};
1045
1046static int fdrive_post_load(void *opaque, int version_id)
1047{
1048 fd_revalidate(opaque);
1049 return 0;
1050}
1051
d7a6c270
JQ		 1052static const VMStateDescription vmstate_fdrive = {
1053 .name = "fdrive",
1054 .version_id = 1,
1055 .minimum_version_id = 1,
c0b92f30 1056 .post_load = fdrive_post_load,
d49805ae 1057 .fields = (VMStateField[]) {
5c02c033
BS		 1058 VMSTATE_UINT8(head, FDrive),
1059 VMSTATE_UINT8(track, FDrive),
1060 VMSTATE_UINT8(sect, FDrive),
d7a6c270 1061 VMSTATE_END_OF_LIST()
7d905f71 1062 },
5cd8cada
JQ		 1063 .subsections = (const VMStateDescription*[]) {
1064 &vmstate_fdrive_media_changed,
1065 &vmstate_fdrive_media_rate,
1066 &vmstate_fdrive_perpendicular,
1067 NULL
d7a6c270
JQ		 1068 }
1069};
3ccacc4a 1070
85d291a0
KW		 1071/*
1072 * Reconstructs the phase from register values according to the logic that was
1073 * implemented in qemu 2.3. This is the default value that is used if the phase
1074 * subsection is not present on migration.
1075 *
1076 * Don't change this function to reflect newer qemu versions, it is part of
1077 * the migration ABI.
1078 */
1079static int reconstruct_phase(FDCtrl *fdctrl)
1080{
1081 if (fdctrl->msr & FD_MSR_NONDMA) {
1082 return FD_PHASE_EXECUTION;
1083 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1084 /* qemu 2.3 disabled RQM only during DMA transfers */
1085 return FD_PHASE_EXECUTION;
1086 } else if (fdctrl->msr & FD_MSR_DIO) {
1087 return FD_PHASE_RESULT;
1088 } else {
1089 return FD_PHASE_COMMAND;
1090 }
1091}
1092
44b1ff31 1093static int fdc_pre_save(void *opaque)
3ccacc4a 1094{
5c02c033 1095 FDCtrl *s = opaque;
3ccacc4a 1096
d7a6c270 1097 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
44b1ff31
DDAG		 1098
1099 return 0;
3ccacc4a
BS		 1100}
1101
85d291a0
KW		 1102static int fdc_pre_load(void *opaque)
1103{
1104 FDCtrl *s = opaque;
1105 s->phase = FD_PHASE_RECONSTRUCT;
1106 return 0;
1107}
1108
e59fb374 1109static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 1110{
5c02c033 1111 FDCtrl *s = opaque;
3ccacc4a 1112
d7a6c270
JQ		 1113 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1114 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 1115
1116 if (s->phase == FD_PHASE_RECONSTRUCT) {
1117 s->phase = reconstruct_phase(s);
1118 }
1119
3ccacc4a
BS		 1120 return 0;
1121}
1122
c0b92f30
PD		 1123static bool fdc_reset_sensei_needed(void *opaque)
1124{
1125 FDCtrl *s = opaque;
1126
1127 return s->reset_sensei != 0;
1128}
1129
1130static const VMStateDescription vmstate_fdc_reset_sensei = {
1131 .name = "fdc/reset_sensei",
1132 .version_id = 1,
1133 .minimum_version_id = 1,
5cd8cada 1134 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 1135 .fields = (VMStateField[]) {
1136 VMSTATE_INT32(reset_sensei, FDCtrl),
1137 VMSTATE_END_OF_LIST()
1138 }
1139};
1140
1141static bool fdc_result_timer_needed(void *opaque)
1142{
1143 FDCtrl *s = opaque;
1144
1145 return timer_pending(s->result_timer);
1146}
1147
1148static const VMStateDescription vmstate_fdc_result_timer = {
1149 .name = "fdc/result_timer",
1150 .version_id = 1,
1151 .minimum_version_id = 1,
5cd8cada 1152 .needed = fdc_result_timer_needed,
c0b92f30 1153 .fields = (VMStateField[]) {
e720677e 1154 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 1155 VMSTATE_END_OF_LIST()
1156 }
1157};
1158
85d291a0
KW		 1159static bool fdc_phase_needed(void *opaque)
1160{
1161 FDCtrl *fdctrl = opaque;
1162
1163 return reconstruct_phase(fdctrl) != fdctrl->phase;
1164}
1165
1166static const VMStateDescription vmstate_fdc_phase = {
1167 .name = "fdc/phase",
1168 .version_id = 1,
1169 .minimum_version_id = 1,
5cd8cada 1170 .needed = fdc_phase_needed,
85d291a0
KW		 1171 .fields = (VMStateField[]) {
1172 VMSTATE_UINT8(phase, FDCtrl),
1173 VMSTATE_END_OF_LIST()
1174 }
1175};
1176
d7a6c270 1177static const VMStateDescription vmstate_fdc = {
aef30c3c 1178 .name = "fdc",
d7a6c270
JQ		 1179 .version_id = 2,
1180 .minimum_version_id = 2,
d7a6c270 1181 .pre_save = fdc_pre_save,
85d291a0 1182 .pre_load = fdc_pre_load,
d7a6c270 1183 .post_load = fdc_post_load,
d49805ae 1184 .fields = (VMStateField[]) {
d7a6c270 1185 /* Controller State */
5c02c033
BS		 1186 VMSTATE_UINT8(sra, FDCtrl),
1187 VMSTATE_UINT8(srb, FDCtrl),
1188 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1189 VMSTATE_UINT8(tdr, FDCtrl),
1190 VMSTATE_UINT8(dsr, FDCtrl),
1191 VMSTATE_UINT8(msr, FDCtrl),
1192 VMSTATE_UINT8(status0, FDCtrl),
1193 VMSTATE_UINT8(status1, FDCtrl),
1194 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1195 /* Command FIFO */
8ec68b06
BS		 1196 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1197 uint8_t),
5c02c033
BS		 1198 VMSTATE_UINT32(data_pos, FDCtrl),
1199 VMSTATE_UINT32(data_len, FDCtrl),
1200 VMSTATE_UINT8(data_state, FDCtrl),
1201 VMSTATE_UINT8(data_dir, FDCtrl),
1202 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1203 /* States kept only to be returned back */
5c02c033
BS		 1204 VMSTATE_UINT8(timer0, FDCtrl),
1205 VMSTATE_UINT8(timer1, FDCtrl),
1206 VMSTATE_UINT8(precomp_trk, FDCtrl),
1207 VMSTATE_UINT8(config, FDCtrl),
1208 VMSTATE_UINT8(lock, FDCtrl),
1209 VMSTATE_UINT8(pwrd, FDCtrl),
d2164ad3 1210 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
5c02c033
BS		 1211 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1212 vmstate_fdrive, FDrive),
d7a6c270 1213 VMSTATE_END_OF_LIST()
c0b92f30 1214 },
5cd8cada
JQ		 1215 .subsections = (const VMStateDescription*[]) {
1216 &vmstate_fdc_reset_sensei,
1217 &vmstate_fdc_result_timer,
1218 &vmstate_fdc_phase,
1219 NULL
78ae820c 1220 }
d7a6c270 1221};
3ccacc4a 1222
2be37833 1223static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1224{
dd3be742 1225 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1226 FDCtrl *s = &sys->state;
2be37833
BS		 1227
1228 fdctrl_reset(s, 0);
1229}
1230
1231static void fdctrl_external_reset_isa(DeviceState *d)
1232{
020c8e76 1233 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1234 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1235
1236 fdctrl_reset(s, 0);
1237}
1238
2be17ebd
BS		 1239static void fdctrl_handle_tc(void *opaque, int irq, int level)
1240{
5c02c033 1241 //FDCtrl *s = opaque;
2be17ebd
BS		 1242
1243 if (level) {
1244 // XXX
1245 FLOPPY_DPRINTF("TC pulsed\n");
1246 }
1247}
1248
8977f3c1 1249/* Change IRQ state */
5c02c033 1250static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1251{
d497d534 1252 fdctrl->status0 = 0;
8c6a4d77
BS		 1253 if (!(fdctrl->sra & FD_SRA_INTPEND))
1254 return;
ed5fd2cc 1255 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1256 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1257 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1258}
1259
d497d534 1260static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1261{
8c6a4d77 1262 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1263 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1264 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1265 }
21fcf360 1266
f2d81b33 1267 fdctrl->reset_sensei = 0;
77370520 1268 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1269}
1270
4b19ec0c 1271/* Reset controller */
5c02c033 1272static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1273{
1274 int i;
1275
4b19ec0c 1276 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1277 fdctrl_reset_irq(fdctrl);
4b19ec0c 1278 /* Initialise controller */
8c6a4d77
BS		 1279 fdctrl->sra = 0;
1280 fdctrl->srb = 0xc0;
4be74634 1281 if (!fdctrl->drives[1].blk) {
8c6a4d77 1282 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1283 }
baca51fa 1284 fdctrl->cur_drv = 0;
1c346df2 1285 fdctrl->dor = FD_DOR_nRESET;
368df94d 1286 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1287 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1288 fdctrl->reset_sensei = 0;
1289 timer_del(fdctrl->result_timer);
8977f3c1 1290 /* FIFO state */
baca51fa
FB		 1291 fdctrl->data_pos = 0;
1292 fdctrl->data_len = 0;
b9b3d225 1293 fdctrl->data_state = 0;
baca51fa 1294 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1295 for (i = 0; i < MAX_FD; i++)
1c346df2 1296 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1297 fdctrl_to_command_phase(fdctrl);
77370520 1298 if (do_irq) {
d497d534
HP		 1299 fdctrl->status0 |= FD_SR0_RDYCHG;
1300 fdctrl_raise_irq(fdctrl);
f2d81b33 1301 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1302 }
baca51fa
FB		 1303}
1304
5c02c033 1305static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1306{
46d3233b 1307 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1308}
1309
5c02c033 1310static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1311{
46d3233b
BS		 1312 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1313 return &fdctrl->drives[1];
1314 else
1315 return &fdctrl->drives[0];
baca51fa
FB		 1316}
1317
78ae820c 1318#if MAX_FD == 4
5c02c033 1319static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1320{
1321 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1322 return &fdctrl->drives[2];
1323 else
1324 return &fdctrl->drives[1];
1325}
1326
5c02c033 1327static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1328{
1329 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1330 return &fdctrl->drives[3];
1331 else
1332 return &fdctrl->drives[2];
1333}
1334#endif
1335
394ea2ca 1336static FDrive *get_drv(FDCtrl *fdctrl, int unit)
baca51fa 1337{
394ea2ca 1338 switch (unit) {
78ae820c
BS		 1339 case 0: return drv0(fdctrl);
1340 case 1: return drv1(fdctrl);
1341#if MAX_FD == 4
1342 case 2: return drv2(fdctrl);
1343 case 3: return drv3(fdctrl);
1344#endif
1345 default: return NULL;
1346 }
8977f3c1
FB		 1347}
1348
394ea2ca
KW		 1349static FDrive *get_cur_drv(FDCtrl *fdctrl)
1350{
1351 return get_drv(fdctrl, fdctrl->cur_drv);
1352}
1353
8c6a4d77 1354/* Status A register : 0x00 (read-only) */
5c02c033 1355static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1356{
1357 uint32_t retval = fdctrl->sra;
1358
1359 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1360
1361 return retval;
1362}
1363
8977f3c1 1364/* Status B register : 0x01 (read-only) */
5c02c033 1365static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1366{
8c6a4d77
BS		 1367 uint32_t retval = fdctrl->srb;
1368
1369 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1370
1371 return retval;
8977f3c1
FB		 1372}
1373
1374/* Digital output register : 0x02 */
5c02c033 1375static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1376{
1c346df2 1377 uint32_t retval = fdctrl->dor;
8977f3c1 1378
8977f3c1 1379 /* Selected drive */
baca51fa 1380 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1381 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1382
1383 return retval;
1384}
1385
5c02c033 1386static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1387{
8977f3c1 1388 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1389
1390 /* Motors */
1391 if (value & FD_DOR_MOTEN0)
1392 fdctrl->srb |= FD_SRB_MTR0;
1393 else
1394 fdctrl->srb &= ~FD_SRB_MTR0;
1395 if (value & FD_DOR_MOTEN1)
1396 fdctrl->srb |= FD_SRB_MTR1;
1397 else
1398 fdctrl->srb &= ~FD_SRB_MTR1;
1399
1400 /* Drive */
1401 if (value & 1)
1402 fdctrl->srb |= FD_SRB_DR0;
1403 else
1404 fdctrl->srb &= ~FD_SRB_DR0;
1405
8977f3c1 1406 /* Reset */
9fea808a 1407 if (!(value & FD_DOR_nRESET)) {
1c346df2 1408 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1409 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1410 }
1411 } else {
1c346df2 1412 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1413 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1414 fdctrl_reset(fdctrl, 1);
b9b3d225 1415 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1416 }
1417 }
1418 /* Selected drive */
9fea808a 1419 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1420
1421 fdctrl->dor = value;
8977f3c1
FB		 1422}
1423
1424/* Tape drive register : 0x03 */
5c02c033 1425static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1426{
46d3233b 1427 uint32_t retval = fdctrl->tdr;
8977f3c1 1428
8977f3c1
FB		 1429 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1430
1431 return retval;
1432}
1433
5c02c033 1434static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1435{
8977f3c1 1436 /* Reset mode */
1c346df2 1437 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1438 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1439 return;
1440 }
1441 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1442 /* Disk boot selection indicator */
46d3233b 1443 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1444 /* Tape indicators: never allow */
1445}
1446
1447/* Main status register : 0x04 (read) */
5c02c033 1448static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1449{
b9b3d225 1450 uint32_t retval = fdctrl->msr;
8977f3c1 1451
b9b3d225 1452 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1453 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1454
8977f3c1
FB		 1455 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1456
1457 return retval;
1458}
1459
1460/* Data select rate register : 0x04 (write) */
5c02c033 1461static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1462{
8977f3c1 1463 /* Reset mode */
1c346df2 1464 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1465 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1466 return;
1467 }
8977f3c1
FB		 1468 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1469 /* Reset: autoclear */
9fea808a 1470 if (value & FD_DSR_SWRESET) {
1c346df2 1471 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1472 fdctrl_reset(fdctrl, 1);
1c346df2 1473 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1474 }
9fea808a 1475 if (value & FD_DSR_PWRDOWN) {
baca51fa 1476 fdctrl_reset(fdctrl, 1);
8977f3c1 1477 }
b9b3d225 1478 fdctrl->dsr = value;
8977f3c1
FB		 1479}
1480
a758f8f4
HP		 1481/* Configuration control register: 0x07 (write) */
1482static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1483{
1484 /* Reset mode */
1485 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1486 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1487 return;
1488 }
1489 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1490
1491 /* Only the rate selection bits used in AT mode, and we
1492 * store those in the DSR.
1493 */
1494 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1495 (value & FD_DSR_DRATEMASK);
1496}
1497
5c02c033 1498static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1499{
21fcf360 1500 return drv->media_changed;
ea185bbd
FB		 1501}
1502
8977f3c1 1503/* Digital input register : 0x07 (read-only) */
5c02c033 1504static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1505{
8977f3c1
FB		 1506 uint32_t retval = 0;
1507
a2df5fa3 1508 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1509 retval |= FD_DIR_DSKCHG;
a2df5fa3 1510 }
3c83eb4f 1511 if (retval != 0) {
baca51fa 1512 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1513 }
8977f3c1
FB		 1514
1515 return retval;
1516}
1517
07e415f2
KW		 1518/* Clear the FIFO and update the state for receiving the next command */
1519static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1520{
85d291a0 1521 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1522 fdctrl->data_dir = FD_DIR_WRITE;
1523 fdctrl->data_pos = 0;
6cc8a11c 1524 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1525 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1526 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1527}
1528
83a26013
KW		 1529/* Update the state to allow the guest to read out the command status.
1530 * @fifo_len is the number of result bytes to be read out. */
1531static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1532{
85d291a0 1533 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1534 fdctrl->data_dir = FD_DIR_READ;
1535 fdctrl->data_len = fifo_len;
1536 fdctrl->data_pos = 0;
b9b3d225 1537 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1538}
1539
1540/* Set an error: unimplemented/unknown command */
5c02c033 1541static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1542{
cced7a13
BS		 1543 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1544 fdctrl->fifo[0]);
9fea808a 1545 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1546 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1547}
1548
6be01b1e
PH		 1549/* Seek to next sector
1550 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1551 * otherwise returns 1
1552 */
5c02c033 1553static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1554{
1555 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1556 cur_drv->head, cur_drv->track, cur_drv->sect,
1557 fd_sector(cur_drv));
1558 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1559 error in fact */
6be01b1e
PH		 1560 uint8_t new_head = cur_drv->head;
1561 uint8_t new_track = cur_drv->track;
1562 uint8_t new_sect = cur_drv->sect;
1563
1564 int ret = 1;
1565
1566 if (new_sect >= cur_drv->last_sect ||
1567 new_sect == fdctrl->eot) {
1568 new_sect = 1;
746d6de7 1569 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1570 if (new_head == 0 &&
746d6de7 1571 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1572 new_head = 1;
746d6de7 1573 } else {
6be01b1e
PH		 1574 new_head = 0;
1575 new_track++;
c5139bd9 1576 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1577 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1578 ret = 0;
1579 }
746d6de7
BS		 1580 }
1581 } else {
c5139bd9 1582 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1583 new_track++;
1584 ret = 0;
1585 }
1586 if (ret == 1) {
1587 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1588 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1589 }
746d6de7 1590 } else {
6be01b1e 1591 new_sect++;
746d6de7 1592 }
6be01b1e
PH		 1593 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1594 return ret;
746d6de7
BS		 1595}
1596
8977f3c1 1597/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1598static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1599 uint8_t status1, uint8_t status2)
8977f3c1 1600{
5c02c033 1601 FDrive *cur_drv;
baca51fa 1602 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1603
1604 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1605 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1606 if (cur_drv->head) {
1607 fdctrl->status0 |= FD_SR0_HEAD;
1608 }
1609 fdctrl->status0 |= status0;
2fee0088 1610
8977f3c1 1611 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1612 status0, status1, status2, fdctrl->status0);
1613 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1614 fdctrl->fifo[1] = status1;
1615 fdctrl->fifo[2] = status2;
1616 fdctrl->fifo[3] = cur_drv->track;
1617 fdctrl->fifo[4] = cur_drv->head;
1618 fdctrl->fifo[5] = cur_drv->sect;
1619 fdctrl->fifo[6] = FD_SECTOR_SC;
1620 fdctrl->data_dir = FD_DIR_READ;
441f6692 1621 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1622 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1623 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1624 }
b9b3d225 1625 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1626 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1627
83a26013 1628 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1629 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1630}
1631
1632/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1633static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1634{
5c02c033 1635 FDrive *cur_drv;
8977f3c1 1636 uint8_t kh, kt, ks;
8977f3c1 1637
cefec4f5 1638 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1639 cur_drv = get_cur_drv(fdctrl);
1640 kt = fdctrl->fifo[2];
1641 kh = fdctrl->fifo[3];
1642 ks = fdctrl->fifo[4];
4b19ec0c 1643 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1644 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1645 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1646 NUM_SIDES(cur_drv)));
77370520 1647 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1648 case 2:
1649 /* sect too big */
9fea808a 1650 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1651 fdctrl->fifo[3] = kt;
1652 fdctrl->fifo[4] = kh;
1653 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1654 return;
1655 case 3:
1656 /* track too big */
77370520 1657 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1658 fdctrl->fifo[3] = kt;
1659 fdctrl->fifo[4] = kh;
1660 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1661 return;
1662 case 4:
1663 /* No seek enabled */
9fea808a 1664 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1665 fdctrl->fifo[3] = kt;
1666 fdctrl->fifo[4] = kh;
1667 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1668 return;
1669 case 1:
d6ed4e21 1670 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1671 break;
1672 default:
1673 break;
1674 }
b9b3d225 1675
844f65d6
HP		 1676 /* Check the data rate. If the programmed data rate does not match
1677 * the currently inserted medium, the operation has to fail. */
1678 if (fdctrl->check_media_rate &&
1679 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1680 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1681 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1682 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1683 fdctrl->fifo[3] = kt;
1684 fdctrl->fifo[4] = kh;
1685 fdctrl->fifo[5] = ks;
1686 return;
1687 }
1688
8977f3c1 1689 /* Set the FIFO state */
baca51fa
FB		 1690 fdctrl->data_dir = direction;
1691 fdctrl->data_pos = 0;
27c86e24 1692 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1693 if (fdctrl->fifo[0] & 0x80)
1694 fdctrl->data_state |= FD_STATE_MULTI;
1695 else
1696 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1697 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1698 fdctrl->data_len = fdctrl->fifo[8];
1699 } else {
4f431960 1700 int tmp;
3bcb80f1 1701 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1702 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1703 if (fdctrl->fifo[0] & 0x80)
771effeb 1704 tmp += fdctrl->fifo[6];
4f431960 1705 fdctrl->data_len *= tmp;
baca51fa 1706 }
890fa6be 1707 fdctrl->eot = fdctrl->fifo[6];
368df94d 1708 if (fdctrl->dor & FD_DOR_DMAEN) {
c8a35f1c
HP		 1709 IsaDmaTransferMode dma_mode;
1710 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1711 bool dma_mode_ok;
8977f3c1 1712 /* DMA transfer are enabled. Check if DMA channel is well programmed */
c8a35f1c 1713 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
baca51fa 1714 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1715 dma_mode, direction,
baca51fa 1716 (128 << fdctrl->fifo[5]) *
4f431960 1717 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
c8a35f1c
HP		 1718 switch (direction) {
1719 case FD_DIR_SCANE:
1720 case FD_DIR_SCANL:
1721 case FD_DIR_SCANH:
1722 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1723 break;
1724 case FD_DIR_WRITE:
1725 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1726 break;
1727 case FD_DIR_READ:
1728 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1729 break;
1730 case FD_DIR_VERIFY:
1731 dma_mode_ok = true;
1732 break;
1733 default:
1734 dma_mode_ok = false;
1735 break;
1736 }
1737 if (dma_mode_ok) {
8977f3c1 1738 /* No access is allowed until DMA transfer has completed */
b9b3d225 1739 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1740 if (direction != FD_DIR_VERIFY) {
1741 /* Now, we just have to wait for the DMA controller to
1742 * recall us...
1743 */
c8a35f1c
HP		 1744 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1745 k->schedule(fdctrl->dma);
7ea004ed
HP		 1746 } else {
1747 /* Start transfer */
1748 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1749 fdctrl->data_len);
1750 }
8977f3c1 1751 return;
baca51fa 1752 } else {
cced7a13
BS		 1753 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1754 direction);
8977f3c1
FB		 1755 }
1756 }
1757 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1758 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1759 if (direction != FD_DIR_WRITE)
1760 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1761 /* IO based transfer: calculate len */
d497d534 1762 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1763}
1764
1765/* Prepare a transfer of deleted data */
5c02c033 1766static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1767{
cced7a13 1768 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1769
8977f3c1
FB		 1770 /* We don't handle deleted data,
1771 * so we don't return *ANYTHING*
1772 */
9fea808a 1773 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1774}
1775
1776/* handlers for DMA transfers */
85571bc7
FB		 1777static int fdctrl_transfer_handler (void *opaque, int nchan,
1778 int dma_pos, int dma_len)
8977f3c1 1779{
5c02c033
BS		 1780 FDCtrl *fdctrl;
1781 FDrive *cur_drv;
baca51fa 1782 int len, start_pos, rel_pos;
8977f3c1 1783 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1784 IsaDmaClass *k;
8977f3c1 1785
baca51fa 1786 fdctrl = opaque;
b9b3d225 1787 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1788 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1789 return 0;
1790 }
c8a35f1c 1791 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1792 cur_drv = get_cur_drv(fdctrl);
1793 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1794 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1795 status2 = FD_SR2_SNS;
85571bc7
FB		 1796 if (dma_len > fdctrl->data_len)
1797 dma_len = fdctrl->data_len;
4be74634 1798 if (cur_drv->blk == NULL) {
4f431960 1799 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1800 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1801 else
9fea808a 1802 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1803 len = 0;
890fa6be
FB		 1804 goto transfer_error;
1805 }
baca51fa 1806 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1807 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1808 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1809 if (len + rel_pos > FD_SECTOR_LEN)
1810 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1811 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1812 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1813 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1814 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1815 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1816 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1817 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1818 /* READ & SCAN commands and realign to a sector for WRITE */
a7a5b7c0
EB		 1819 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1820 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
8977f3c1
FB		 1821 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1822 fd_sector(cur_drv));
1823 /* Sure, image size is too small... */
baca51fa 1824 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1825 }
890fa6be 1826 }
4f431960
JM		 1827 switch (fdctrl->data_dir) {
1828 case FD_DIR_READ:
1829 /* READ commands */
c8a35f1c
HP		 1830 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1831 fdctrl->data_pos, len);
4f431960
JM		 1832 break;
1833 case FD_DIR_WRITE:
baca51fa 1834 /* WRITE commands */
8510854e
HP		 1835 if (cur_drv->ro) {
1836 /* Handle readonly medium early, no need to do DMA, touch the
1837 * LED or attempt any writes. A real floppy doesn't attempt
1838 * to write to readonly media either. */
1839 fdctrl_stop_transfer(fdctrl,
1840 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1841 0x00);
1842 goto transfer_error;
1843 }
1844
c8a35f1c
HP		 1845 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1846 fdctrl->data_pos, len);
a7a5b7c0
EB		 1847 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1848 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 1849 FLOPPY_DPRINTF("error writing sector %d\n",
1850 fd_sector(cur_drv));
9fea808a 1851 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1852 goto transfer_error;
890fa6be 1853 }
4f431960 1854 break;
7ea004ed
HP		 1855 case FD_DIR_VERIFY:
1856 /* VERIFY commands */
1857 break;
4f431960
JM		 1858 default:
1859 /* SCAN commands */
baca51fa 1860 {
4f431960 1861 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1862 int ret;
c8a35f1c
HP		 1863 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1864 len);
baca51fa 1865 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1866 if (ret == 0) {
77370520 1867 status2 = FD_SR2_SEH;
8977f3c1
FB		 1868 goto end_transfer;
1869 }
baca51fa
FB		 1870 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1871 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1872 status2 = 0x00;
1873 goto end_transfer;
1874 }
1875 }
4f431960 1876 break;
8977f3c1 1877 }
4f431960
JM		 1878 fdctrl->data_pos += len;
1879 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1880 if (rel_pos == 0) {
8977f3c1 1881 /* Seek to next sector */
746d6de7
BS		 1882 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1883 break;
8977f3c1
FB		 1884 }
1885 }
4f431960 1886 end_transfer:
baca51fa
FB		 1887 len = fdctrl->data_pos - start_pos;
1888 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1889 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1890 if (fdctrl->data_dir == FD_DIR_SCANE ||
1891 fdctrl->data_dir == FD_DIR_SCANL ||
1892 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1893 status2 = FD_SR2_SEH;
baca51fa 1894 fdctrl->data_len -= len;
890fa6be 1895 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1896 transfer_error:
8977f3c1 1897
baca51fa 1898 return len;
8977f3c1
FB		 1899}
1900
8977f3c1 1901/* Data register : 0x05 */
5c02c033 1902static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1903{
5c02c033 1904 FDrive *cur_drv;
8977f3c1 1905 uint32_t retval = 0;
e9077462 1906 uint32_t pos;
8977f3c1 1907
baca51fa 1908 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1909 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1910 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1911 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1912 return 0;
1913 }
f6c2d1d8
KW		 1914
1915 /* If data_len spans multiple sectors, the current position in the FIFO
1916 * wraps around while fdctrl->data_pos is the real position in the whole
1917 * request. */
baca51fa 1918 pos = fdctrl->data_pos;
e9077462 1919 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1920
1921 switch (fdctrl->phase) {
1922 case FD_PHASE_EXECUTION:
1923 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1924 if (pos == 0) {
746d6de7
BS		 1925 if (fdctrl->data_pos != 0)
1926 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1927 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1928 fd_sector(cur_drv));
1929 return 0;
1930 }
a7a5b7c0
EB		 1931 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1932 BDRV_SECTOR_SIZE)
4be74634 1933 < 0) {
77370520
BS		 1934 FLOPPY_DPRINTF("error getting sector %d\n",
1935 fd_sector(cur_drv));
1936 /* Sure, image size is too small... */
1937 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1938 }
8977f3c1 1939 }
f6c2d1d8
KW		 1940
1941 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1942 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1943 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1944 }
1945 break;
1946
1947 case FD_PHASE_RESULT:
1948 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1949 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1950 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1951 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1952 fdctrl_reset_irq(fdctrl);
1953 }
f6c2d1d8
KW		 1954 break;
1955
1956 case FD_PHASE_COMMAND:
1957 default:
1958 abort();
8977f3c1 1959 }
f6c2d1d8
KW		 1960
1961 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1962 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1963
1964 return retval;
1965}
1966
5c02c033 1967static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1968{
5c02c033 1969 FDrive *cur_drv;
baca51fa 1970 uint8_t kh, kt, ks;
8977f3c1 1971
cefec4f5 1972 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1973 cur_drv = get_cur_drv(fdctrl);
1974 kt = fdctrl->fifo[6];
1975 kh = fdctrl->fifo[7];
1976 ks = fdctrl->fifo[8];
1977 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1978 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1979 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1980 NUM_SIDES(cur_drv)));
9fea808a 1981 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1982 case 2:
1983 /* sect too big */
9fea808a 1984 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1985 fdctrl->fifo[3] = kt;
1986 fdctrl->fifo[4] = kh;
1987 fdctrl->fifo[5] = ks;
1988 return;
1989 case 3:
1990 /* track too big */
77370520 1991 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1992 fdctrl->fifo[3] = kt;
1993 fdctrl->fifo[4] = kh;
1994 fdctrl->fifo[5] = ks;
1995 return;
1996 case 4:
1997 /* No seek enabled */
9fea808a 1998 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1999 fdctrl->fifo[3] = kt;
2000 fdctrl->fifo[4] = kh;
2001 fdctrl->fifo[5] = ks;
2002 return;
2003 case 1:
cd30b53d 2004 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 2005 break;
2006 default:
2007 break;
2008 }
2009 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634 2010 if (cur_drv->blk == NULL ||
a7a5b7c0
EB		 2011 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2012 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13 2013 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 2014 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 2015 } else {
4f431960
JM		 2016 if (cur_drv->sect == cur_drv->last_sect) {
2017 fdctrl->data_state &= ~FD_STATE_FORMAT;
2018 /* Last sector done */
cd30b53d 2019 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 2020 } else {
2021 /* More to do */
2022 fdctrl->data_pos = 0;
2023 fdctrl->data_len = 4;
2024 }
baca51fa
FB		 2025 }
2026}
2027
5c02c033 2028static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 2029{
2030 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2031 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 2032 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2033}
2034
5c02c033 2035static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 2036{
5c02c033 2037 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2038
2039 /* Drives position */
2040 fdctrl->fifo[0] = drv0(fdctrl)->track;
2041 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 2042#if MAX_FD == 4
2043 fdctrl->fifo[2] = drv2(fdctrl)->track;
2044 fdctrl->fifo[3] = drv3(fdctrl)->track;
2045#else
65cef780
BS		 2046 fdctrl->fifo[2] = 0;
2047 fdctrl->fifo[3] = 0;
78ae820c 2048#endif
65cef780
BS		 2049 /* timers */
2050 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 2051 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 2052 fdctrl->fifo[6] = cur_drv->last_sect;
2053 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2054 (cur_drv->perpendicular << 2);
2055 fdctrl->fifo[8] = fdctrl->config;
2056 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 2057 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 2058}
2059
5c02c033 2060static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 2061{
2062 /* Controller's version */
2063 fdctrl->fifo[0] = fdctrl->version;
83a26013 2064 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2065}
2066
5c02c033 2067static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 2068{
2069 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 2070 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2071}
2072
5c02c033 2073static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 2074{
5c02c033 2075 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2076
2077 /* Drives position */
2078 drv0(fdctrl)->track = fdctrl->fifo[3];
2079 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 2080#if MAX_FD == 4
2081 drv2(fdctrl)->track = fdctrl->fifo[5];
2082 drv3(fdctrl)->track = fdctrl->fifo[6];
2083#endif
65cef780
BS		 2084 /* timers */
2085 fdctrl->timer0 = fdctrl->fifo[7];
2086 fdctrl->timer1 = fdctrl->fifo[8];
2087 cur_drv->last_sect = fdctrl->fifo[9];
2088 fdctrl->lock = fdctrl->fifo[10] >> 7;
2089 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2090 fdctrl->config = fdctrl->fifo[11];
2091 fdctrl->precomp_trk = fdctrl->fifo[12];
2092 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 2093 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2094}
2095
5c02c033 2096static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 2097{
5c02c033 2098 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2099
2100 fdctrl->fifo[0] = 0;
2101 fdctrl->fifo[1] = 0;
2102 /* Drives position */
2103 fdctrl->fifo[2] = drv0(fdctrl)->track;
2104 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 2105#if MAX_FD == 4
2106 fdctrl->fifo[4] = drv2(fdctrl)->track;
2107 fdctrl->fifo[5] = drv3(fdctrl)->track;
2108#else
65cef780
BS		 2109 fdctrl->fifo[4] = 0;
2110 fdctrl->fifo[5] = 0;
78ae820c 2111#endif
65cef780
BS		 2112 /* timers */
2113 fdctrl->fifo[6] = fdctrl->timer0;
2114 fdctrl->fifo[7] = fdctrl->timer1;
2115 fdctrl->fifo[8] = cur_drv->last_sect;
2116 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2117 (cur_drv->perpendicular << 2);
2118 fdctrl->fifo[10] = fdctrl->config;
2119 fdctrl->fifo[11] = fdctrl->precomp_trk;
2120 fdctrl->fifo[12] = fdctrl->pwrd;
2121 fdctrl->fifo[13] = 0;
2122 fdctrl->fifo[14] = 0;
83a26013 2123 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 2124}
2125
5c02c033 2126static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 2127{
5c02c033 2128 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2129
65cef780 2130 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 2131 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2132 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 2133}
2134
5c02c033 2135static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 2136{
5c02c033 2137 FDrive *cur_drv;
65cef780 2138
cefec4f5 2139 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2140 cur_drv = get_cur_drv(fdctrl);
2141 fdctrl->data_state |= FD_STATE_FORMAT;
2142 if (fdctrl->fifo[0] & 0x80)
2143 fdctrl->data_state |= FD_STATE_MULTI;
2144 else
2145 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 2146 cur_drv->bps =
2147 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2148#if 0
2149 cur_drv->last_sect =
2150 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2151 fdctrl->fifo[3] / 2;
2152#else
2153 cur_drv->last_sect = fdctrl->fifo[3];
2154#endif
2155 /* TODO: implement format using DMA expected by the Bochs BIOS
2156 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2157 * the sector with the specified fill byte
2158 */
2159 fdctrl->data_state &= ~FD_STATE_FORMAT;
2160 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2161}
2162
5c02c033 2163static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 2164{
2165 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2166 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 2167 if (fdctrl->fifo[2] & 1)
2168 fdctrl->dor &= ~FD_DOR_DMAEN;
2169 else
2170 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 2171 /* No result back */
07e415f2 2172 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2173}
2174
5c02c033 2175static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 2176{
5c02c033 2177 FDrive *cur_drv;
65cef780 2178
cefec4f5 2179 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2180 cur_drv = get_cur_drv(fdctrl);
2181 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2182 /* 1 Byte status back */
2183 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2184 (cur_drv->track == 0 ? 0x10 : 0x00) |
2185 (cur_drv->head << 2) |
cefec4f5 2186 GET_CUR_DRV(fdctrl) |
65cef780 2187 0x28;
83a26013 2188 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2189}
2190
5c02c033 2191static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2192{
5c02c033 2193 FDrive *cur_drv;
65cef780 2194
cefec4f5 2195 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2196 cur_drv = get_cur_drv(fdctrl);
2197 fd_recalibrate(cur_drv);
07e415f2 2198 fdctrl_to_command_phase(fdctrl);
65cef780 2199 /* Raise Interrupt */
d497d534
HP		 2200 fdctrl->status0 |= FD_SR0_SEEK;
2201 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2202}
2203
5c02c033 2204static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2205{
5c02c033 2206 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2207
2fee0088 2208 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2209 fdctrl->fifo[0] =
2210 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2211 fdctrl->reset_sensei--;
2fee0088
PH		 2212 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2213 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2214 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2215 return;
f2d81b33 2216 } else {
f2d81b33 2217 fdctrl->fifo[0] =
2fee0088
PH		 2218 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2219 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2220 }
2221
65cef780 2222 fdctrl->fifo[1] = cur_drv->track;
83a26013 2223 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2224 fdctrl_reset_irq(fdctrl);
77370520 2225 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2226}
2227
5c02c033 2228static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2229{
5c02c033 2230 FDrive *cur_drv;
65cef780 2231
cefec4f5 2232 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2233 cur_drv = get_cur_drv(fdctrl);
07e415f2 2234 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2235 /* The seek command just sends step pulses to the drive and doesn't care if
2236 * there is a medium inserted of if it's banging the head against the drive.
2237 */
6be01b1e 2238 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2239 /* Raise Interrupt */
d497d534
HP		 2240 fdctrl->status0 |= FD_SR0_SEEK;
2241 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2242}
2243
5c02c033 2244static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2245{
5c02c033 2246 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2247
2248 if (fdctrl->fifo[1] & 0x80)
2249 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2250 /* No result back */
07e415f2 2251 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2252}
2253
5c02c033 2254static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2255{
2256 fdctrl->config = fdctrl->fifo[2];
2257 fdctrl->precomp_trk = fdctrl->fifo[3];
2258 /* No result back */
07e415f2 2259 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2260}
2261
5c02c033 2262static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2263{
2264 fdctrl->pwrd = fdctrl->fifo[1];
2265 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2266 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2267}
2268
5c02c033 2269static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2270{
2271 /* No result back */
07e415f2 2272 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2273}
2274
5c02c033 2275static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2276{
5c02c033 2277 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2278 uint32_t pos;
65cef780 2279
e9077462
PM		 2280 pos = fdctrl->data_pos - 1;
2281 pos %= FD_SECTOR_LEN;
2282 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2283 /* Command parameters done */
e9077462 2284 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2285 fdctrl->fifo[0] = fdctrl->fifo[1];
2286 fdctrl->fifo[2] = 0;
2287 fdctrl->fifo[3] = 0;
83a26013 2288 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2289 } else {
07e415f2 2290 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2291 }
2292 } else if (fdctrl->data_len > 7) {
2293 /* ERROR */
2294 fdctrl->fifo[0] = 0x80 |
cefec4f5 2295 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2296 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2297 }
2298}
2299
6d013772 2300static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2301{
5c02c033 2302 FDrive *cur_drv;
65cef780 2303
cefec4f5 2304 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2305 cur_drv = get_cur_drv(fdctrl);
65cef780 2306 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2307 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2308 cur_drv->sect, 1);
65cef780 2309 } else {
6d013772
PH		 2310 fd_seek(cur_drv, cur_drv->head,
2311 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2312 }
07e415f2 2313 fdctrl_to_command_phase(fdctrl);
77370520 2314 /* Raise Interrupt */
d497d534
HP		 2315 fdctrl->status0 |= FD_SR0_SEEK;
2316 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2317}
2318
6d013772 2319static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2320{
5c02c033 2321 FDrive *cur_drv;
65cef780 2322
cefec4f5 2323 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2324 cur_drv = get_cur_drv(fdctrl);
65cef780 2325 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2326 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2327 } else {
6d013772
PH		 2328 fd_seek(cur_drv, cur_drv->head,
2329 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2330 }
07e415f2 2331 fdctrl_to_command_phase(fdctrl);
65cef780 2332 /* Raise Interrupt */
d497d534
HP		 2333 fdctrl->status0 |= FD_SR0_SEEK;
2334 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2335}
2336
85d291a0
KW		 2337/*
2338 * Handlers for the execution phase of each command
2339 */
d275b33d 2340typedef struct FDCtrlCommand {
678803ab
BS		 2341 uint8_t value;
2342 uint8_t mask;
2343 const char* name;
2344 int parameters;
5c02c033 2345 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2346 int direction;
d275b33d
KW		 2347} FDCtrlCommand;
2348
2349static const FDCtrlCommand handlers[] = {
678803ab
BS		 2350 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2351 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2352 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2353 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2354 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2355 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2356 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2357 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2358 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2359 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2360 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2361 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2362 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2363 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2364 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2365 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2366 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2367 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2368 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2369 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2370 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2371 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2372 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2373 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2374 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2375 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2376 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2377 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2378 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2379 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2380 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2381 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2382};
2383/* Associate command to an index in the 'handlers' array */
2384static uint8_t command_to_handler[256];
2385
d275b33d
KW		 2386static const FDCtrlCommand *get_command(uint8_t cmd)
2387{
2388 int idx;
2389
2390 idx = command_to_handler[cmd];
2391 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2392 return &handlers[idx];
2393}
2394
5c02c033 2395static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2396{
5c02c033 2397 FDrive *cur_drv;
d275b33d 2398 const FDCtrlCommand *cmd;
e9077462 2399 uint32_t pos;
baca51fa 2400
8977f3c1 2401 /* Reset mode */
1c346df2 2402 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2403 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2404 return;
2405 }
b9b3d225 2406 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2407 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2408 return;
2409 }
b9b3d225 2410 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2411
d275b33d
KW		 2412 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2413
2414 /* If data_len spans multiple sectors, the current position in the FIFO
2415 * wraps around while fdctrl->data_pos is the real position in the whole
2416 * request. */
2417 pos = fdctrl->data_pos++;
2418 pos %= FD_SECTOR_LEN;
2419 fdctrl->fifo[pos] = value;
2420
6cc8a11c
KW		 2421 if (fdctrl->data_pos == fdctrl->data_len) {
2422 fdctrl->msr &= ~FD_MSR_RQM;
2423 }
2424
5b0a25e8
KW		 2425 switch (fdctrl->phase) {
2426 case FD_PHASE_EXECUTION:
2427 /* For DMA requests, RQM should be cleared during execution phase, so
2428 * we would have errored out above. */
2429 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2430
8977f3c1 2431 /* FIFO data write */
b3bc1540 2432 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2433 fdctrl->data_pos == fdctrl->data_len) {
77370520 2434 cur_drv = get_cur_drv(fdctrl);
a7a5b7c0
EB		 2435 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2436 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 2437 FLOPPY_DPRINTF("error writing sector %d\n",
2438 fd_sector(cur_drv));
5b0a25e8 2439 break;
77370520 2440 }
746d6de7
BS		 2441 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2442 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2443 fd_sector(cur_drv));
5b0a25e8 2444 break;
746d6de7 2445 }
8977f3c1 2446 }
d275b33d
KW		 2447
2448 /* Switch to result phase when done with the transfer */
2449 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2450 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2451 }
5b0a25e8 2452 break;
678803ab 2453
5b0a25e8
KW		 2454 case FD_PHASE_COMMAND:
2455 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2456 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2457
d275b33d
KW		 2458 if (pos == 0) {
2459 /* The first byte specifies the command. Now we start reading
2460 * as many parameters as this command requires. */
2461 cmd = get_command(value);
2462 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2463 if (cmd->parameters) {
2464 fdctrl->msr |= FD_MSR_RQM;
2465 }
5b0a25e8 2466 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2467 }
65cef780 2468
5b0a25e8 2469 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2470 /* We have all parameters now, execute the command */
5b0a25e8 2471 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2472
5b0a25e8
KW		 2473 if (fdctrl->data_state & FD_STATE_FORMAT) {
2474 fdctrl_format_sector(fdctrl);
2475 break;
2476 }
2477
d275b33d
KW		 2478 cmd = get_command(fdctrl->fifo[0]);
2479 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2480 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2481 }
2482 break;
2483
2484 case FD_PHASE_RESULT:
2485 default:
2486 abort();
8977f3c1
FB		 2487 }
2488}
ed5fd2cc
FB		 2489
2490static void fdctrl_result_timer(void *opaque)
2491{
5c02c033
BS		 2492 FDCtrl *fdctrl = opaque;
2493 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2494
b7ffa3b1
TS		 2495 /* Pretend we are spinning.
2496 * This is needed for Coherent, which uses READ ID to check for
2497 * sector interleaving.
2498 */
2499 if (cur_drv->last_sect != 0) {
2500 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2501 }
844f65d6
HP		 2502 /* READ_ID can't automatically succeed! */
2503 if (fdctrl->check_media_rate &&
2504 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2505 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2506 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2507 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2508 } else {
2509 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2510 }
ed5fd2cc 2511}
678803ab
BS		 2512
2513/* Init functions */
c0ca74f6
FZ		 2514static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2515 Error **errp)
678803ab 2516{
12a71a02 2517 unsigned int i;
7d0d6950 2518 FDrive *drive;
394ea2ca 2519 DeviceState *dev;
a92bd191 2520 BlockBackend *blk;
394ea2ca 2521 Error *local_err = NULL;
678803ab 2522
678803ab 2523 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2524 drive = &fdctrl->drives[i];
844f65d6 2525 drive->fdctrl = fdctrl;
7d0d6950 2526
394ea2ca
KW		 2527 /* If the drive is not present, we skip creating the qdev device, but
2528 * still have to initialise the controller. */
a92bd191
KW		 2529 blk = fdctrl->qdev_for_drives[i].blk;
2530 if (!blk) {
394ea2ca
KW		 2531 fd_init(drive);
2532 fd_revalidate(drive);
2533 continue;
b47b3525
MA		 2534 }
2535
394ea2ca
KW		 2536 dev = qdev_create(&fdctrl->bus.bus, "floppy");
2537 qdev_prop_set_uint32(dev, "unit", i);
a92bd191
KW		 2538 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2539
2540 blk_ref(blk);
2541 blk_detach_dev(blk, fdc_dev);
2542 fdctrl->qdev_for_drives[i].blk = NULL;
2543 qdev_prop_set_drive(dev, "drive", blk, &local_err);
2544 blk_unref(blk);
2545
2546 if (local_err) {
2547 error_propagate(errp, local_err);
2548 return;
2549 }
2550
394ea2ca
KW		 2551 object_property_set_bool(OBJECT(dev), true, "realized", &local_err);
2552 if (local_err) {
2553 error_propagate(errp, local_err);
2554 return;
7d0d6950 2555 }
678803ab 2556 }
678803ab
BS		 2557}
2558
dfc65f1f
MA		 2559ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2560{
4a17cc4f
AF		 2561 DeviceState *dev;
2562 ISADevice *isadev;
dfc65f1f 2563
4a17cc4f
AF		 2564 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2565 if (!isadev) {
dfc65f1f
MA		 2566 return NULL;
2567 }
4a17cc4f 2568 dev = DEVICE(isadev);
dfc65f1f
MA		 2569
2570 if (fds[0]) {
6231a6da
MA		 2571 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2572 &error_fatal);
dfc65f1f
MA		 2573 }
2574 if (fds[1]) {
6231a6da
MA		 2575 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2576 &error_fatal);
dfc65f1f 2577 }
4a17cc4f 2578 qdev_init_nofail(dev);
dfc65f1f 2579
4a17cc4f 2580 return isadev;
dfc65f1f
MA		 2581}
2582
63ffb564 2583void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2584 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2585{
5c02c033 2586 FDCtrl *fdctrl;
2091ba23 2587 DeviceState *dev;
dd3be742 2588 SysBusDevice *sbd;
5c02c033 2589 FDCtrlSysBus *sys;
2091ba23 2590
19d46d71 2591 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2592 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2593 fdctrl = &sys->state;
2594 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2595 if (fds[0]) {
6231a6da
MA		 2596 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2597 &error_fatal);
995bf0ca
GH		 2598 }
2599 if (fds[1]) {
6231a6da
MA		 2600 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2601 &error_fatal);
995bf0ca 2602 }
e23a1b33 2603 qdev_init_nofail(dev);
dd3be742
HT		 2604 sbd = SYS_BUS_DEVICE(dev);
2605 sysbus_connect_irq(sbd, 0, irq);
2606 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2607}
2608
a8170e5e 2609void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2610 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2611{
f64ab228 2612 DeviceState *dev;
5c02c033 2613 FDCtrlSysBus *sys;
678803ab 2614
12a71a02 2615 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2616 if (fds[0]) {
6231a6da
MA		 2617 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2618 &error_fatal);
995bf0ca 2619 }
e23a1b33 2620 qdev_init_nofail(dev);
dd3be742
HT		 2621 sys = SYSBUS_FDC(dev);
2622 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2623 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2624 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2625}
f64ab228 2626
51e6e90e
KW		 2627static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2628 Error **errp)
f64ab228 2629{
12a71a02
BS		 2630 int i, j;
2631 static int command_tables_inited = 0;
f64ab228 2632
a73275dd
JS		 2633 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2634 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2635 }
2636
12a71a02
BS		 2637 /* Fill 'command_to_handler' lookup table */
2638 if (!command_tables_inited) {
2639 command_tables_inited = 1;
2640 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2641 for (j = 0; j < sizeof(command_to_handler); j++) {
2642 if ((j & handlers[i].mask) == handlers[i].value) {
2643 command_to_handler[j] = i;
2644 }
2645 }
2646 }
2647 }
2648
2649 FLOPPY_DPRINTF("init controller\n");
2650 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 2651 fdctrl->fifo_size = 512;
bc72ad67 2652 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2653 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2654
2655 fdctrl->version = 0x90; /* Intel 82078 controller */
2656 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2657 fdctrl->num_floppies = MAX_FD;
12a71a02 2658
a3ef7a61 2659 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2660 IsaDmaClass *k;
2661 assert(fdctrl->dma);
2662 k = ISADMA_GET_CLASS(fdctrl->dma);
2663 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2664 &fdctrl_transfer_handler, fdctrl);
a3ef7a61 2665 }
51e6e90e
KW		 2666
2667 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
c0ca74f6 2668 fdctrl_connect_drives(fdctrl, dev, errp);
f64ab228
BS		 2669}
2670
212ec7ba 2671static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2672 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2673 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2674 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2675};
2676
db895a1e 2677static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2678{
db895a1e 2679 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2680 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2681 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2682 Error *err = NULL;
8baf73ad 2683
e305a165
MAL		 2684 isa_register_portio_list(isadev, &fdctrl->portio_list,
2685 isa->iobase, fdc_portio_list, fdctrl,
db895a1e 2686 "fdc");
dee41d58 2687
db895a1e 2688 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2689 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2690 if (fdctrl->dma_chann != -1) {
2691 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
b3da5513
AK		 2692 if (!fdctrl->dma) {
2693 error_setg(errp, "ISA controller does not support DMA");
2694 return;
2695 }
c8a35f1c 2696 }
8baf73ad 2697
db895a1e 2698 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
51e6e90e 2699 fdctrl_realize_common(dev, fdctrl, &err);
a3ef7a61
AF		 2700 if (err != NULL) {
2701 error_propagate(errp, err);
db895a1e
AF		 2702 return;
2703 }
8baf73ad
GH		 2704}
2705
940194c2 2706static void sysbus_fdc_initfn(Object *obj)
12a71a02 2707{
19d46d71 2708 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2709 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2710 FDCtrl *fdctrl = &sys->state;
12a71a02 2711
19d46d71
AF		 2712 fdctrl->dma_chann = -1;
2713
940194c2 2714 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2715 "fdc", 0x08);
19d46d71 2716 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2717}
2718
19d46d71 2719static void sun4m_fdc_initfn(Object *obj)
940194c2 2720{
19d46d71
AF		 2721 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2722 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2723 FDCtrl *fdctrl = &sys->state;
940194c2 2724
dd446051
HP		 2725 fdctrl->dma_chann = -1;
2726
19d46d71
AF		 2727 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2728 fdctrl, "fdctrl", 0x08);
2729 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2730}
2be37833 2731
19d46d71 2732static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2733{
19d46d71
AF		 2734 DeviceState *dev = DEVICE(obj);
2735 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2736 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2737 FDCtrl *fdctrl = &sys->state;
2738
19d46d71
AF		 2739 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2740
2741 sysbus_init_irq(sbd, &fdctrl->irq);
2742 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2743}
2744
19d46d71 2745static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2746{
dd3be742
HT		 2747 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2748 FDCtrl *fdctrl = &sys->state;
12a71a02 2749
51e6e90e 2750 fdctrl_realize_common(dev, fdctrl, errp);
12a71a02 2751}
f64ab228 2752
2da44dd0 2753FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2754{
020c8e76 2755 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2756
61a8d649 2757 return isa->state.drives[i].drive;
34d4260e
KW		 2758}
2759
e08fde0c
RK		 2760void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2761 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2762{
2763 const FDFormat *fdf;
2764
2765 *maxc = *maxh = *maxs = 0;
2766 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2767 if (fdf->drive != type) {
2768 continue;
2769 }
2770 if (*maxc < fdf->max_track) {
2771 *maxc = fdf->max_track;
2772 }
2773 if (*maxh < fdf->max_head) {
2774 *maxh = fdf->max_head;
2775 }
2776 if (*maxs < fdf->last_sect) {
2777 *maxs = fdf->last_sect;
2778 }
2779 }
2780 (*maxc)--;
2781}
2782
a64405d1
JK		 2783static const VMStateDescription vmstate_isa_fdc ={
2784 .name = "fdc",
2785 .version_id = 2,
2786 .minimum_version_id = 2,
d49805ae 2787 .fields = (VMStateField[]) {
a64405d1
JK		 2788 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2789 VMSTATE_END_OF_LIST()
2790 }
2791};
2792
39bffca2 2793static Property isa_fdc_properties[] = {
c7bcc85d 2794 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2795 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2796 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
a92bd191
KW		 2797 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2798 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
09c6d585
HP		 2799 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2800 0, true),
85bbd1e7 2801 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
fff4687b
JS		 2802 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2803 FloppyDriveType),
85bbd1e7 2804 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
fff4687b
JS		 2805 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2806 FloppyDriveType),
85bbd1e7 2807 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
4812fa27 2808 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2809 FloppyDriveType),
39bffca2
AL		 2810 DEFINE_PROP_END_OF_LIST(),
2811};
2812
020c8e76 2813static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2814{
39bffca2 2815 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2816
2817 dc->realize = isabus_fdc_realize;
39bffca2 2818 dc->fw_name = "fdc";
39bffca2
AL		 2819 dc->reset = fdctrl_external_reset_isa;
2820 dc->vmsd = &vmstate_isa_fdc;
2821 dc->props = isa_fdc_properties;
125ee0ed 2822 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2823}
2824
81782b6a
GA		 2825static void isabus_fdc_instance_init(Object *obj)
2826{
2827 FDCtrlISABus *isa = ISA_FDC(obj);
2828
2829 device_add_bootindex_property(obj, &isa->bootindexA,
2830 "bootindexA", "/floppy@0",
2831 DEVICE(obj), NULL);
2832 device_add_bootindex_property(obj, &isa->bootindexB,
2833 "bootindexB", "/floppy@1",
2834 DEVICE(obj), NULL);
2835}
2836
8c43a6f0 2837static const TypeInfo isa_fdc_info = {
020c8e76 2838 .name = TYPE_ISA_FDC,
39bffca2
AL		 2839 .parent = TYPE_ISA_DEVICE,
2840 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2841 .class_init = isabus_fdc_class_init,
81782b6a 2842 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2843};
2844
a64405d1
JK		 2845static const VMStateDescription vmstate_sysbus_fdc ={
2846 .name = "fdc",
2847 .version_id = 2,
2848 .minimum_version_id = 2,
d49805ae 2849 .fields = (VMStateField[]) {
a64405d1
JK		 2850 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2851 VMSTATE_END_OF_LIST()
2852 }
2853};
2854
999e12bb 2855static Property sysbus_fdc_properties[] = {
a92bd191
KW		 2856 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2857 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
85bbd1e7 2858 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2859 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2860 FloppyDriveType),
85bbd1e7 2861 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
fff4687b
JS		 2862 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2863 FloppyDriveType),
85bbd1e7 2864 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2865 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2866 FloppyDriveType),
999e12bb 2867 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2868};
2869
999e12bb
AL		 2870static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2871{
39bffca2 2872 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2873
39bffca2 2874 dc->props = sysbus_fdc_properties;
125ee0ed 2875 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2876}
2877
8c43a6f0 2878static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2879 .name = "sysbus-fdc",
2880 .parent = TYPE_SYSBUS_FDC,
940194c2 2881 .instance_init = sysbus_fdc_initfn,
39bffca2 2882 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2883};
2884
2885static Property sun4m_fdc_properties[] = {
a92bd191 2886 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
85bbd1e7 2887 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
fff4687b
JS		 2888 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2889 FloppyDriveType),
85bbd1e7 2890 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
a73275dd
JS		 2891 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2892 FloppyDriveType),
999e12bb
AL		 2893 DEFINE_PROP_END_OF_LIST(),
2894};
2895
2896static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2897{
39bffca2 2898 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2899
39bffca2 2900 dc->props = sun4m_fdc_properties;
125ee0ed 2901 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2902}
2903
8c43a6f0 2904static const TypeInfo sun4m_fdc_info = {
39bffca2 2905 .name = "SUNW,fdtwo",
19d46d71 2906 .parent = TYPE_SYSBUS_FDC,
940194c2 2907 .instance_init = sun4m_fdc_initfn,
39bffca2 2908 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2909};
2910
19d46d71
AF		 2911static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2912{
2913 DeviceClass *dc = DEVICE_CLASS(klass);
2914
2915 dc->realize = sysbus_fdc_common_realize;
2916 dc->reset = fdctrl_external_reset_sysbus;
2917 dc->vmsd = &vmstate_sysbus_fdc;
2918}
2919
2920static const TypeInfo sysbus_fdc_type_info = {
2921 .name = TYPE_SYSBUS_FDC,
2922 .parent = TYPE_SYS_BUS_DEVICE,
2923 .instance_size = sizeof(FDCtrlSysBus),
2924 .instance_init = sysbus_fdc_common_initfn,
2925 .abstract = true,
2926 .class_init = sysbus_fdc_common_class_init,
2927};
2928
83f7d43a 2929static void fdc_register_types(void)
f64ab228 2930{
39bffca2 2931 type_register_static(&isa_fdc_info);
19d46d71 2932 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2933 type_register_static(&sysbus_fdc_info);
2934 type_register_static(&sun4m_fdc_info);
51e6e90e 2935 type_register_static(&floppy_bus_info);
394ea2ca 2936 type_register_static(&floppy_drive_info);
f64ab228
BS		 2937}
2938
83f7d43a 2939type_init(fdc_register_types)
Mirror of https://git.qemu.org/git/qemu.git