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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
29133e9a | 32 | * It does not implement software data protection as found in many real chips |
29133e9a FB |
33 | */ |
34 | ||
80c71a24 | 35 | #include "qemu/osdep.h" |
06f15217 | 36 | #include "hw/block/block.h" |
0d09e41a | 37 | #include "hw/block/flash.h" |
da34e65c | 38 | #include "qapi/error.h" |
ddb6f225 | 39 | #include "qemu/bitmap.h" |
1de7afc9 | 40 | #include "qemu/timer.h" |
4be74634 | 41 | #include "sysemu/block-backend.h" |
1de7afc9 | 42 | #include "qemu/host-utils.h" |
0b8fa32f | 43 | #include "qemu/module.h" |
83c9f4ca | 44 | #include "hw/sysbus.h" |
d6454270 | 45 | #include "migration/vmstate.h" |
13019f1f | 46 | #include "trace.h" |
29133e9a | 47 | |
6536987f | 48 | #define PFLASH_DEBUG false |
ec9ea489 PC |
49 | #define DPRINTF(fmt, ...) \ |
50 | do { \ | |
6536987f PMD |
51 | if (PFLASH_DEBUG) { \ |
52 | fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ | |
53 | } \ | |
29133e9a | 54 | } while (0) |
29133e9a | 55 | |
661bfc80 JK |
56 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
57 | ||
64659053 SC |
58 | /* |
59 | * The size of the cfi_table indirectly depends on this and the start of the | |
60 | * PRI table directly depends on it. 4 is the maximum size (and also what | |
61 | * seems common) without changing the PRT table address. | |
62 | */ | |
63 | #define PFLASH_MAX_ERASE_REGIONS 4 | |
64 | ||
aeaf6c20 PMD |
65 | /* Special write cycles for CFI queries. */ |
66 | enum { | |
67 | WCYCLE_CFI = 7, | |
46fb7809 | 68 | WCYCLE_AUTOSELECT_CFI = 8, |
aeaf6c20 PMD |
69 | }; |
70 | ||
16434065 | 71 | struct PFlashCFI02 { |
3509c396 HT |
72 | /*< private >*/ |
73 | SysBusDevice parent_obj; | |
74 | /*< public >*/ | |
75 | ||
4be74634 | 76 | BlockBackend *blk; |
64659053 SC |
77 | uint32_t uniform_nb_blocs; |
78 | uint32_t uniform_sector_len; | |
ddb6f225 | 79 | uint32_t total_sectors; |
64659053 SC |
80 | uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; |
81 | uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; | |
4fbd24ba | 82 | uint32_t chip_len; |
368a354f PC |
83 | uint8_t mappings; |
84 | uint8_t width; | |
85 | uint8_t be; | |
29133e9a FB |
86 | int wcycle; /* if 0, the flash is read normally */ |
87 | int bypass; | |
88 | int ro; | |
89 | uint8_t cmd; | |
90 | uint8_t status; | |
368a354f PC |
91 | /* FIXME: implement array device properties */ |
92 | uint16_t ident0; | |
93 | uint16_t ident1; | |
94 | uint16_t ident2; | |
95 | uint16_t ident3; | |
96 | uint16_t unlock_addr0; | |
97 | uint16_t unlock_addr1; | |
64659053 | 98 | uint8_t cfi_table[0x4d]; |
d80cf1eb | 99 | QEMUTimer timer; |
cfe5f011 AK |
100 | /* The device replicates the flash memory across its memory space. Emulate |
101 | * that by having a container (.mem) filled with an array of aliases | |
102 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
103 | */ | |
104 | MemoryRegion mem; | |
105 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
106 | MemoryRegion orig_mem; | |
9c9bb6c8 | 107 | int rom_mode; |
661bfc80 | 108 | int read_counter; /* used for lazy switch-back to rom mode */ |
a50547ac | 109 | int sectors_to_erase; |
ddb6f225 SC |
110 | uint64_t erase_time_remaining; |
111 | unsigned long *sector_erase_map; | |
368a354f | 112 | char *name; |
29133e9a FB |
113 | void *storage; |
114 | }; | |
115 | ||
1d311e73 PMD |
116 | /* |
117 | * Toggle status bit DQ7. | |
118 | */ | |
119 | static inline void toggle_dq7(PFlashCFI02 *pfl) | |
120 | { | |
121 | pfl->status ^= 0x80; | |
122 | } | |
123 | ||
124 | /* | |
125 | * Set status bit DQ7 to bit 7 of value. | |
126 | */ | |
127 | static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) | |
128 | { | |
129 | pfl->status &= 0x7F; | |
130 | pfl->status |= value & 0x80; | |
131 | } | |
132 | ||
133 | /* | |
134 | * Toggle status bit DQ6. | |
135 | */ | |
136 | static inline void toggle_dq6(PFlashCFI02 *pfl) | |
137 | { | |
138 | pfl->status ^= 0x40; | |
139 | } | |
140 | ||
a50547ac SC |
141 | /* |
142 | * Turn on DQ3. | |
143 | */ | |
144 | static inline void assert_dq3(PFlashCFI02 *pfl) | |
145 | { | |
146 | pfl->status |= 0x08; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Turn off DQ3. | |
151 | */ | |
152 | static inline void reset_dq3(PFlashCFI02 *pfl) | |
153 | { | |
154 | pfl->status &= ~0x08; | |
155 | } | |
156 | ||
ddb6f225 SC |
157 | /* |
158 | * Toggle status bit DQ2. | |
159 | */ | |
160 | static inline void toggle_dq2(PFlashCFI02 *pfl) | |
161 | { | |
162 | pfl->status ^= 0x04; | |
163 | } | |
164 | ||
cfe5f011 AK |
165 | /* |
166 | * Set up replicated mappings of the same region. | |
167 | */ | |
16434065 | 168 | static void pflash_setup_mappings(PFlashCFI02 *pfl) |
c8a50e59 | 169 | { |
cfe5f011 | 170 | unsigned i; |
a8170e5e | 171 | hwaddr size = memory_region_size(&pfl->orig_mem); |
cfe5f011 | 172 | |
2d256e6f | 173 | memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); |
cfe5f011 AK |
174 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
175 | for (i = 0; i < pfl->mappings; ++i) { | |
2d256e6f PB |
176 | memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), |
177 | "pflash-alias", &pfl->orig_mem, 0, size); | |
cfe5f011 AK |
178 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
179 | } | |
180 | } | |
01e0451a | 181 | |
16434065 | 182 | static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) |
cfe5f011 | 183 | { |
5f9a5ea1 | 184 | memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); |
bda254da | 185 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
186 | } |
187 | ||
102f0f79 PMD |
188 | static size_t pflash_regions_count(PFlashCFI02 *pfl) |
189 | { | |
190 | return pfl->cfi_table[0x2c]; | |
191 | } | |
192 | ||
ddb6f225 SC |
193 | /* |
194 | * Returns the time it takes to erase the number of sectors scheduled for | |
195 | * erasure based on CFI address 0x21 which is "Typical timeout per individual | |
196 | * block erase 2^N ms." | |
197 | */ | |
198 | static uint64_t pflash_erase_time(PFlashCFI02 *pfl) | |
199 | { | |
200 | /* | |
201 | * If there are no sectors to erase (which can happen if all of the sectors | |
202 | * to be erased are protected), then erase takes 100 us. Protected sectors | |
203 | * aren't supported so this should never happen. | |
204 | */ | |
205 | return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Returns true if the device is currently in erase suspend mode. | |
210 | */ | |
211 | static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl) | |
212 | { | |
213 | return pfl->erase_time_remaining > 0; | |
214 | } | |
215 | ||
a50547ac | 216 | static void pflash_timer(void *opaque) |
29133e9a | 217 | { |
16434065 | 218 | PFlashCFI02 *pfl = opaque; |
29133e9a | 219 | |
13019f1f | 220 | trace_pflash_timer_expired(pfl->cmd); |
a50547ac SC |
221 | if (pfl->cmd == 0x30) { |
222 | /* | |
223 | * Sector erase. If DQ3 is 0 when the timer expires, then the 50 | |
224 | * us erase timeout has expired so we need to start the timer for the | |
225 | * sector erase algorithm. Otherwise, the erase completed and we should | |
226 | * go back to read array mode. | |
227 | */ | |
228 | if ((pfl->status & 0x08) == 0) { | |
229 | assert_dq3(pfl); | |
ddb6f225 | 230 | uint64_t timeout = pflash_erase_time(pfl); |
a50547ac SC |
231 | timer_mod(&pfl->timer, |
232 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); | |
233 | DPRINTF("%s: erase timeout fired; erasing %d sectors\n", | |
234 | __func__, pfl->sectors_to_erase); | |
235 | return; | |
236 | } | |
237 | DPRINTF("%s: sector erase complete\n", __func__); | |
ddb6f225 | 238 | bitmap_zero(pfl->sector_erase_map, pfl->total_sectors); |
a50547ac SC |
239 | pfl->sectors_to_erase = 0; |
240 | reset_dq3(pfl); | |
241 | } | |
242 | ||
29133e9a | 243 | /* Reset flash */ |
1d311e73 | 244 | toggle_dq7(pfl); |
29133e9a FB |
245 | if (pfl->bypass) { |
246 | pfl->wcycle = 2; | |
247 | } else { | |
4fbd24ba | 248 | pflash_register_memory(pfl, 1); |
29133e9a FB |
249 | pfl->wcycle = 0; |
250 | } | |
251 | pfl->cmd = 0; | |
252 | } | |
253 | ||
06e8b8e3 PMD |
254 | /* |
255 | * Read data from flash. | |
256 | */ | |
257 | static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, | |
258 | unsigned int width) | |
259 | { | |
260 | uint8_t *p = (uint8_t *)pfl->storage + offset; | |
261 | uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); | |
262 | trace_pflash_data_read(offset, width << 1, ret); | |
263 | return ret; | |
264 | } | |
265 | ||
ddb6f225 SC |
266 | typedef struct { |
267 | uint32_t len; | |
268 | uint32_t num; | |
269 | } SectorInfo; | |
270 | ||
64659053 SC |
271 | /* |
272 | * offset should be a byte offset of the QEMU device and _not_ a device | |
273 | * offset. | |
274 | */ | |
ddb6f225 | 275 | static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset) |
64659053 SC |
276 | { |
277 | assert(offset < pfl->chip_len); | |
64659053 | 278 | hwaddr addr = 0; |
ddb6f225 | 279 | uint32_t sector_num = 0; |
102f0f79 | 280 | for (int i = 0; i < pflash_regions_count(pfl); ++i) { |
64659053 SC |
281 | uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i]; |
282 | if (addr <= offset && offset < addr + region_size) { | |
ddb6f225 SC |
283 | return (SectorInfo) { |
284 | .len = pfl->sector_len[i], | |
285 | .num = sector_num + (offset - addr) / pfl->sector_len[i], | |
286 | }; | |
64659053 | 287 | } |
ddb6f225 | 288 | sector_num += pfl->nb_blocs[i]; |
64659053 SC |
289 | addr += region_size; |
290 | } | |
291 | abort(); | |
292 | } | |
293 | ||
ddb6f225 SC |
294 | /* |
295 | * Returns true if the offset refers to a flash sector that is currently being | |
296 | * erased. | |
297 | */ | |
298 | static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset) | |
299 | { | |
300 | long sector_num = pflash_sector_info(pfl, offset).num; | |
301 | return test_bit(sector_num, pfl->sector_erase_map); | |
302 | } | |
303 | ||
aff498cf | 304 | static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) |
29133e9a | 305 | { |
aff498cf | 306 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 307 | hwaddr boff; |
aff498cf | 308 | uint64_t ret; |
29133e9a | 309 | |
29133e9a | 310 | ret = -1; |
661bfc80 JK |
311 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
312 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
313 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
314 | pflash_register_memory(pfl, 1); | |
0f459d16 | 315 | } |
4fbd24ba | 316 | offset &= pfl->chip_len - 1; |
29133e9a | 317 | boff = offset & 0xFF; |
64659053 | 318 | if (pfl->width == 2) { |
29133e9a | 319 | boff = boff >> 1; |
51500d37 PMD |
320 | } else if (pfl->width == 4) { |
321 | boff = boff >> 2; | |
64659053 | 322 | } |
29133e9a FB |
323 | switch (pfl->cmd) { |
324 | default: | |
325 | /* This should never happen : reset state & treat it as a read*/ | |
326 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
327 | pfl->wcycle = 0; | |
328 | pfl->cmd = 0; | |
30954850 | 329 | /* fall through to the read code */ |
b0349937 | 330 | case 0x80: /* Erase (unlock) */ |
29133e9a FB |
331 | /* We accept reads during second unlock sequence... */ |
332 | case 0x00: | |
ddb6f225 SC |
333 | if (pflash_erase_suspend_mode(pfl) && |
334 | pflash_sector_is_erasing(pfl, offset)) { | |
335 | /* Toggle bit 2, but not 6. */ | |
336 | toggle_dq2(pfl); | |
337 | /* Status register read */ | |
338 | ret = pfl->status; | |
339 | DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); | |
340 | break; | |
341 | } | |
29133e9a | 342 | /* Flash area read */ |
06e8b8e3 | 343 | ret = pflash_data_read(pfl, offset, width); |
29133e9a | 344 | break; |
b0349937 | 345 | case 0x90: /* flash ID read */ |
29133e9a FB |
346 | switch (boff) { |
347 | case 0x00: | |
348 | case 0x01: | |
368a354f | 349 | ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; |
29133e9a FB |
350 | break; |
351 | case 0x02: | |
352 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
353 | break; | |
354 | case 0x0E: | |
355 | case 0x0F: | |
368a354f | 356 | ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; |
7f7bdcaf PMD |
357 | if (ret != (uint8_t)-1) { |
358 | break; | |
368a354f | 359 | } |
7f7bdcaf | 360 | /* Fall through to data read. */ |
29133e9a | 361 | default: |
06e8b8e3 | 362 | ret = pflash_data_read(pfl, offset, width); |
29133e9a | 363 | } |
aff498cf | 364 | DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret); |
29133e9a | 365 | break; |
b0349937 PMD |
366 | case 0x10: /* Chip Erase */ |
367 | case 0x30: /* Sector Erase */ | |
ddb6f225 SC |
368 | /* Toggle bit 2 during erase, but not program. */ |
369 | toggle_dq2(pfl); | |
2658594f | 370 | /* fall through */ |
b0349937 | 371 | case 0xA0: /* Program */ |
ddb6f225 SC |
372 | /* Toggle bit 6 */ |
373 | toggle_dq6(pfl); | |
29133e9a FB |
374 | /* Status register read */ |
375 | ret = pfl->status; | |
aff498cf | 376 | DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); |
29133e9a FB |
377 | break; |
378 | case 0x98: | |
379 | /* CFI query mode */ | |
07c13a71 | 380 | if (boff < sizeof(pfl->cfi_table)) { |
29133e9a | 381 | ret = pfl->cfi_table[boff]; |
07c13a71 PMD |
382 | } else { |
383 | ret = 0; | |
384 | } | |
29133e9a FB |
385 | break; |
386 | } | |
e8aa2d95 | 387 | trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); |
29133e9a FB |
388 | |
389 | return ret; | |
390 | } | |
391 | ||
392 | /* update flash content on disk */ | |
aff498cf | 393 | static void pflash_update(PFlashCFI02 *pfl, int offset, int size) |
29133e9a FB |
394 | { |
395 | int offset_end; | |
4be74634 | 396 | if (pfl->blk) { |
29133e9a | 397 | offset_end = offset + size; |
098e732d EB |
398 | /* widen to sector boundaries */ |
399 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); | |
400 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); | |
401 | blk_pwrite(pfl->blk, offset, pfl->storage + offset, | |
402 | offset_end - offset, 0); | |
29133e9a FB |
403 | } |
404 | } | |
405 | ||
a50547ac SC |
406 | static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) |
407 | { | |
ddb6f225 SC |
408 | SectorInfo sector_info = pflash_sector_info(pfl, offset); |
409 | uint64_t sector_len = sector_info.len; | |
a50547ac SC |
410 | offset &= ~(sector_len - 1); |
411 | DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", | |
412 | __func__, pfl->width * 2, offset, | |
413 | pfl->width * 2, offset + sector_len - 1); | |
414 | if (!pfl->ro) { | |
415 | uint8_t *p = pfl->storage; | |
416 | memset(p + offset, 0xff, sector_len); | |
417 | pflash_update(pfl, offset, sector_len); | |
418 | } | |
419 | set_dq7(pfl, 0x00); | |
420 | ++pfl->sectors_to_erase; | |
ddb6f225 | 421 | set_bit(sector_info.num, pfl->sector_erase_map); |
a50547ac SC |
422 | /* Set (or reset) the 50 us timer for additional erase commands. */ |
423 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); | |
424 | } | |
425 | ||
aff498cf PMD |
426 | static void pflash_write(void *opaque, hwaddr offset, uint64_t value, |
427 | unsigned int width) | |
29133e9a | 428 | { |
aff498cf | 429 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 430 | hwaddr boff; |
29133e9a FB |
431 | uint8_t *p; |
432 | uint8_t cmd; | |
433 | ||
e8aa2d95 | 434 | trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); |
95d1f3ed | 435 | cmd = value; |
8a508e70 | 436 | if (pfl->cmd != 0xA0) { |
a9791042 SC |
437 | /* Reset does nothing during chip erase and sector erase. */ |
438 | if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) { | |
46fb7809 SC |
439 | if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) { |
440 | /* Return to autoselect mode. */ | |
441 | pfl->wcycle = 3; | |
442 | pfl->cmd = 0x90; | |
443 | return; | |
444 | } | |
8a508e70 PMD |
445 | goto reset_flash; |
446 | } | |
95d1f3ed | 447 | } |
4fbd24ba | 448 | offset &= pfl->chip_len - 1; |
3b46e624 | 449 | |
6682bc1e | 450 | boff = offset; |
64659053 | 451 | if (pfl->width == 2) { |
29133e9a | 452 | boff = boff >> 1; |
51500d37 PMD |
453 | } else if (pfl->width == 4) { |
454 | boff = boff >> 2; | |
64659053 | 455 | } |
6682bc1e SC |
456 | /* Only the least-significant 11 bits are used in most cases. */ |
457 | boff &= 0x7FF; | |
29133e9a FB |
458 | switch (pfl->wcycle) { |
459 | case 0: | |
9c9bb6c8 AZ |
460 | /* Set the device in I/O access mode if required */ |
461 | if (pfl->rom_mode) | |
462 | pflash_register_memory(pfl, 0); | |
661bfc80 | 463 | pfl->read_counter = 0; |
29133e9a FB |
464 | /* We're in read mode */ |
465 | check_unlock0: | |
466 | if (boff == 0x55 && cmd == 0x98) { | |
29133e9a | 467 | /* Enter CFI query mode */ |
aeaf6c20 | 468 | pfl->wcycle = WCYCLE_CFI; |
29133e9a FB |
469 | pfl->cmd = 0x98; |
470 | return; | |
471 | } | |
ddb6f225 | 472 | /* Handle erase resume in erase suspend mode, otherwise reset. */ |
b0349937 | 473 | if (cmd == 0x30) { /* Erase Resume */ |
ddb6f225 SC |
474 | if (pflash_erase_suspend_mode(pfl)) { |
475 | /* Resume the erase. */ | |
476 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
477 | pfl->erase_time_remaining); | |
478 | pfl->erase_time_remaining = 0; | |
479 | pfl->wcycle = 6; | |
480 | pfl->cmd = 0x30; | |
481 | set_dq7(pfl, 0x00); | |
482 | assert_dq3(pfl); | |
483 | return; | |
484 | } | |
485 | goto reset_flash; | |
486 | } | |
487 | /* Ignore erase suspend. */ | |
b0349937 | 488 | if (cmd == 0xB0) { /* Erase Suspend */ |
ddb6f225 SC |
489 | return; |
490 | } | |
368a354f | 491 | if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
f8be67ee | 492 | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
368a354f | 493 | __func__, boff, cmd, pfl->unlock_addr0); |
29133e9a FB |
494 | goto reset_flash; |
495 | } | |
496 | DPRINTF("%s: unlock sequence started\n", __func__); | |
497 | break; | |
498 | case 1: | |
499 | /* We started an unlock sequence */ | |
500 | check_unlock1: | |
368a354f | 501 | if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
f8be67ee | 502 | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 503 | boff, cmd); |
29133e9a FB |
504 | goto reset_flash; |
505 | } | |
506 | DPRINTF("%s: unlock sequence done\n", __func__); | |
507 | break; | |
508 | case 2: | |
509 | /* We finished an unlock sequence */ | |
368a354f | 510 | if (!pfl->bypass && boff != pfl->unlock_addr0) { |
f8be67ee | 511 | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 512 | boff, cmd); |
29133e9a FB |
513 | goto reset_flash; |
514 | } | |
515 | switch (cmd) { | |
516 | case 0x20: | |
517 | pfl->bypass = 1; | |
518 | goto do_bypass; | |
b0349937 PMD |
519 | case 0x80: /* Erase */ |
520 | case 0x90: /* Autoselect */ | |
521 | case 0xA0: /* Program */ | |
29133e9a FB |
522 | pfl->cmd = cmd; |
523 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
524 | break; | |
525 | default: | |
526 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
527 | goto reset_flash; | |
528 | } | |
529 | break; | |
530 | case 3: | |
531 | switch (pfl->cmd) { | |
b0349937 | 532 | case 0x80: /* Erase */ |
29133e9a FB |
533 | /* We need another unlock sequence */ |
534 | goto check_unlock0; | |
b0349937 | 535 | case 0xA0: /* Program */ |
ddb6f225 SC |
536 | if (pflash_erase_suspend_mode(pfl) && |
537 | pflash_sector_is_erasing(pfl, offset)) { | |
538 | /* Ignore writes to erasing sectors. */ | |
539 | if (pfl->bypass) { | |
540 | goto do_bypass; | |
541 | } | |
542 | goto reset_flash; | |
543 | } | |
c1474acd | 544 | trace_pflash_data_write(offset, width << 1, value, 0); |
de8efe8f | 545 | if (!pfl->ro) { |
c3d25271 PMD |
546 | p = (uint8_t *)pfl->storage + offset; |
547 | if (pfl->be) { | |
548 | uint64_t current = ldn_be_p(p, width); | |
549 | stn_be_p(p, width, current & value); | |
550 | } else { | |
551 | uint64_t current = ldn_le_p(p, width); | |
552 | stn_le_p(p, width, current & value); | |
5f9fc5ad | 553 | } |
c3d25271 | 554 | pflash_update(pfl, offset, width); |
29133e9a | 555 | } |
1d311e73 PMD |
556 | /* |
557 | * While programming, status bit DQ7 should hold the opposite | |
558 | * value from how it was programmed. | |
559 | */ | |
560 | set_dq7(pfl, ~value); | |
29133e9a FB |
561 | /* Let's pretend write is immediate */ |
562 | if (pfl->bypass) | |
563 | goto do_bypass; | |
564 | goto reset_flash; | |
b0349937 | 565 | case 0x90: /* Autoselect */ |
29133e9a FB |
566 | if (pfl->bypass && cmd == 0x00) { |
567 | /* Unlock bypass reset */ | |
568 | goto reset_flash; | |
569 | } | |
46fb7809 SC |
570 | /* |
571 | * We can enter CFI query mode from autoselect mode, but we must | |
572 | * return to autoselect mode after a reset. | |
573 | */ | |
574 | if (boff == 0x55 && cmd == 0x98) { | |
575 | /* Enter autoselect CFI query mode */ | |
576 | pfl->wcycle = WCYCLE_AUTOSELECT_CFI; | |
577 | pfl->cmd = 0x98; | |
578 | return; | |
579 | } | |
124e4cfa | 580 | /* fall through */ |
29133e9a FB |
581 | default: |
582 | DPRINTF("%s: invalid write for command %02x\n", | |
583 | __func__, pfl->cmd); | |
584 | goto reset_flash; | |
585 | } | |
586 | case 4: | |
587 | switch (pfl->cmd) { | |
b0349937 | 588 | case 0xA0: /* Program */ |
a1c7273b | 589 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
590 | /* As we suppose write is immediate, this should never happen */ |
591 | return; | |
b0349937 | 592 | case 0x80: /* Erase */ |
29133e9a FB |
593 | goto check_unlock1; |
594 | default: | |
595 | /* Should never happen */ | |
596 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
597 | __func__, pfl->cmd); | |
598 | goto reset_flash; | |
599 | } | |
600 | break; | |
601 | case 5: | |
ddb6f225 SC |
602 | if (pflash_erase_suspend_mode(pfl)) { |
603 | /* Erasing is not supported in erase suspend mode. */ | |
604 | goto reset_flash; | |
605 | } | |
29133e9a | 606 | switch (cmd) { |
b0349937 | 607 | case 0x10: /* Chip Erase */ |
368a354f | 608 | if (boff != pfl->unlock_addr0) { |
f8be67ee | 609 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
29133e9a FB |
610 | __func__, offset); |
611 | goto reset_flash; | |
612 | } | |
613 | /* Chip erase */ | |
614 | DPRINTF("%s: start chip erase\n", __func__); | |
de8efe8f | 615 | if (!pfl->ro) { |
1eb27d69 | 616 | memset(pfl->storage, 0xff, pfl->chip_len); |
de8efe8f JJ |
617 | pflash_update(pfl, 0, pfl->chip_len); |
618 | } | |
1d311e73 | 619 | set_dq7(pfl, 0x00); |
80f2c625 | 620 | /* Wait the time specified at CFI address 0x22. */ |
d80cf1eb | 621 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
80f2c625 | 622 | (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); |
29133e9a | 623 | break; |
b0349937 | 624 | case 0x30: /* Sector erase */ |
a50547ac | 625 | pflash_sector_erase(pfl, offset); |
29133e9a FB |
626 | break; |
627 | default: | |
628 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
629 | goto reset_flash; | |
630 | } | |
631 | pfl->cmd = cmd; | |
632 | break; | |
633 | case 6: | |
634 | switch (pfl->cmd) { | |
b0349937 | 635 | case 0x10: /* Chip Erase */ |
29133e9a FB |
636 | /* Ignore writes during chip erase */ |
637 | return; | |
b0349937 | 638 | case 0x30: /* Sector erase */ |
ddb6f225 SC |
639 | if (cmd == 0xB0) { |
640 | /* | |
641 | * If erase suspend happens during the erase timeout (so DQ3 is | |
642 | * 0), then the device suspends erasing immediately. Set the | |
643 | * remaining time to be the total time to erase. Otherwise, | |
644 | * there is a maximum amount of time it can take to enter | |
645 | * suspend mode. Let's ignore that and suspend immediately and | |
646 | * set the remaining time to the actual time remaining on the | |
647 | * timer. | |
648 | */ | |
649 | if ((pfl->status & 0x08) == 0) { | |
650 | pfl->erase_time_remaining = pflash_erase_time(pfl); | |
651 | } else { | |
652 | int64_t delta = timer_expire_time_ns(&pfl->timer) - | |
653 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
654 | /* Make sure we have a positive time remaining. */ | |
655 | pfl->erase_time_remaining = delta <= 0 ? 1 : delta; | |
656 | } | |
657 | reset_dq3(pfl); | |
658 | timer_del(&pfl->timer); | |
659 | pfl->wcycle = 0; | |
660 | pfl->cmd = 0; | |
661 | return; | |
662 | } | |
a50547ac SC |
663 | /* |
664 | * If DQ3 is 0, additional sector erase commands can be | |
665 | * written and anything else (other than an erase suspend) resets | |
666 | * the device. | |
667 | */ | |
668 | if ((pfl->status & 0x08) == 0) { | |
669 | if (cmd == 0x30) { | |
670 | pflash_sector_erase(pfl, offset); | |
671 | } else { | |
672 | goto reset_flash; | |
673 | } | |
674 | } | |
675 | /* Ignore writes during the actual erase. */ | |
29133e9a FB |
676 | return; |
677 | default: | |
678 | /* Should never happen */ | |
679 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
680 | __func__, pfl->cmd); | |
681 | goto reset_flash; | |
682 | } | |
683 | break; | |
aeaf6c20 PMD |
684 | /* Special values for CFI queries */ |
685 | case WCYCLE_CFI: | |
46fb7809 | 686 | case WCYCLE_AUTOSELECT_CFI: |
29133e9a FB |
687 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); |
688 | goto reset_flash; | |
689 | default: | |
690 | /* Should never happen */ | |
691 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
692 | goto reset_flash; | |
693 | } | |
694 | pfl->wcycle++; | |
695 | ||
696 | return; | |
697 | ||
698 | /* Reset flash */ | |
699 | reset_flash: | |
13019f1f | 700 | trace_pflash_reset(); |
29133e9a FB |
701 | pfl->bypass = 0; |
702 | pfl->wcycle = 0; | |
703 | pfl->cmd = 0; | |
704 | return; | |
705 | ||
706 | do_bypass: | |
707 | pfl->wcycle = 2; | |
708 | pfl->cmd = 0; | |
29133e9a FB |
709 | } |
710 | ||
aff498cf PMD |
711 | static const MemoryRegionOps pflash_cfi02_ops = { |
712 | .read = pflash_read, | |
713 | .write = pflash_write, | |
a4afb28d PM |
714 | .valid.min_access_size = 1, |
715 | .valid.max_access_size = 4, | |
cfe5f011 | 716 | .endianness = DEVICE_NATIVE_ENDIAN, |
29133e9a FB |
717 | }; |
718 | ||
da3bd642 | 719 | static void pflash_cfi02_realize(DeviceState *dev, Error **errp) |
29133e9a | 720 | { |
e7b62741 | 721 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d0e7605e | 722 | int ret; |
33e0eb52 | 723 | Error *local_err = NULL; |
29133e9a | 724 | |
64659053 | 725 | if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) { |
8929fc3a ZY |
726 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); |
727 | return; | |
728 | } | |
64659053 | 729 | if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) { |
8929fc3a ZY |
730 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); |
731 | return; | |
732 | } | |
733 | if (pfl->name == NULL) { | |
734 | error_setg(errp, "attribute \"name\" not specified."); | |
735 | return; | |
736 | } | |
737 | ||
64659053 SC |
738 | int nb_regions; |
739 | pfl->chip_len = 0; | |
ddb6f225 | 740 | pfl->total_sectors = 0; |
64659053 SC |
741 | for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) { |
742 | if (pfl->nb_blocs[nb_regions] == 0) { | |
743 | break; | |
744 | } | |
ddb6f225 | 745 | pfl->total_sectors += pfl->nb_blocs[nb_regions]; |
64659053 SC |
746 | uint64_t sector_len_per_device = pfl->sector_len[nb_regions]; |
747 | ||
748 | /* | |
749 | * The size of each flash sector must be a power of 2 and it must be | |
750 | * aligned at the same power of 2. | |
751 | */ | |
752 | if (sector_len_per_device & 0xff || | |
753 | sector_len_per_device >= (1 << 24) || | |
754 | !is_power_of_2(sector_len_per_device)) | |
755 | { | |
756 | error_setg(errp, "unsupported configuration: " | |
757 | "sector length[%d] per device = %" PRIx64 ".", | |
758 | nb_regions, sector_len_per_device); | |
759 | return; | |
760 | } | |
761 | if (pfl->chip_len & (sector_len_per_device - 1)) { | |
762 | error_setg(errp, "unsupported configuration: " | |
763 | "flash region %d not correctly aligned.", | |
764 | nb_regions); | |
765 | return; | |
766 | } | |
767 | ||
768 | pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] * | |
769 | pfl->nb_blocs[nb_regions]; | |
770 | } | |
771 | ||
772 | uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs * | |
773 | pfl->uniform_sector_len; | |
774 | if (nb_regions == 0) { | |
775 | nb_regions = 1; | |
776 | pfl->nb_blocs[0] = pfl->uniform_nb_blocs; | |
777 | pfl->sector_len[0] = pfl->uniform_sector_len; | |
778 | pfl->chip_len = uniform_len; | |
ddb6f225 | 779 | pfl->total_sectors = pfl->uniform_nb_blocs; |
64659053 SC |
780 | } else if (uniform_len != 0 && uniform_len != pfl->chip_len) { |
781 | error_setg(errp, "\"num-blocks\"*\"sector-length\" " | |
782 | "different from \"num-blocks0\"*\'sector-length0\" + ... + " | |
783 | "\"num-blocks3\"*\"sector-length3\""); | |
784 | return; | |
785 | } | |
368a354f | 786 | |
aff498cf PMD |
787 | memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), |
788 | &pflash_cfi02_ops, pfl, pfl->name, | |
1eb27d69 | 789 | pfl->chip_len, &local_err); |
33e0eb52 HT |
790 | if (local_err) { |
791 | error_propagate(errp, local_err); | |
792 | return; | |
793 | } | |
794 | ||
cfe5f011 | 795 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
a17c17a2 KW |
796 | |
797 | if (pfl->blk) { | |
798 | uint64_t perm; | |
799 | pfl->ro = blk_is_read_only(pfl->blk); | |
800 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); | |
801 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); | |
802 | if (ret < 0) { | |
803 | return; | |
804 | } | |
805 | } else { | |
806 | pfl->ro = 0; | |
807 | } | |
808 | ||
4be74634 | 809 | if (pfl->blk) { |
1eb27d69 PMD |
810 | if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, |
811 | pfl->chip_len, errp)) { | |
da3bd642 | 812 | vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); |
da3bd642 | 813 | return; |
d0e7605e | 814 | } |
29133e9a | 815 | } |
de8efe8f | 816 | |
6682bc1e SC |
817 | /* Only 11 bits are used in the comparison. */ |
818 | pfl->unlock_addr0 &= 0x7FF; | |
819 | pfl->unlock_addr1 &= 0x7FF; | |
820 | ||
ddb6f225 SC |
821 | /* Allocate memory for a bitmap for sectors being erased. */ |
822 | pfl->sector_erase_map = bitmap_new(pfl->total_sectors); | |
823 | ||
cfe5f011 AK |
824 | pflash_setup_mappings(pfl); |
825 | pfl->rom_mode = 1; | |
da3bd642 | 826 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
de8efe8f | 827 | |
d80cf1eb | 828 | timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
29133e9a FB |
829 | pfl->wcycle = 0; |
830 | pfl->cmd = 0; | |
831 | pfl->status = 0; | |
9ac45b88 | 832 | |
29133e9a | 833 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
64659053 | 834 | const uint16_t pri_ofs = 0x40; |
29133e9a FB |
835 | /* Standard "QRY" string */ |
836 | pfl->cfi_table[0x10] = 'Q'; | |
837 | pfl->cfi_table[0x11] = 'R'; | |
838 | pfl->cfi_table[0x12] = 'Y'; | |
839 | /* Command set (AMD/Fujitsu) */ | |
840 | pfl->cfi_table[0x13] = 0x02; | |
841 | pfl->cfi_table[0x14] = 0x00; | |
78556820 | 842 | /* Primary extended table address */ |
d6874c83 PMD |
843 | pfl->cfi_table[0x15] = pri_ofs; |
844 | pfl->cfi_table[0x16] = pri_ofs >> 8; | |
29133e9a FB |
845 | /* Alternate command set (none) */ |
846 | pfl->cfi_table[0x17] = 0x00; | |
847 | pfl->cfi_table[0x18] = 0x00; | |
848 | /* Alternate extended table (none) */ | |
849 | pfl->cfi_table[0x19] = 0x00; | |
850 | pfl->cfi_table[0x1A] = 0x00; | |
851 | /* Vcc min */ | |
852 | pfl->cfi_table[0x1B] = 0x27; | |
853 | /* Vcc max */ | |
854 | pfl->cfi_table[0x1C] = 0x36; | |
855 | /* Vpp min (no Vpp pin) */ | |
856 | pfl->cfi_table[0x1D] = 0x00; | |
857 | /* Vpp max (no Vpp pin) */ | |
858 | pfl->cfi_table[0x1E] = 0x00; | |
9ac45b88 | 859 | /* Timeout per single byte/word write (128 ms) */ |
29133e9a | 860 | pfl->cfi_table[0x1F] = 0x07; |
78556820 EI |
861 | /* Timeout for min size buffer write (NA) */ |
862 | pfl->cfi_table[0x20] = 0x00; | |
29133e9a FB |
863 | /* Typical timeout for block erase (512 ms) */ |
864 | pfl->cfi_table[0x21] = 0x09; | |
865 | /* Typical timeout for full chip erase (4096 ms) */ | |
866 | pfl->cfi_table[0x22] = 0x0C; | |
867 | /* Reserved */ | |
868 | pfl->cfi_table[0x23] = 0x01; | |
78556820 EI |
869 | /* Max timeout for buffer write (NA) */ |
870 | pfl->cfi_table[0x24] = 0x00; | |
29133e9a FB |
871 | /* Max timeout for block erase */ |
872 | pfl->cfi_table[0x25] = 0x0A; | |
873 | /* Max timeout for chip erase */ | |
874 | pfl->cfi_table[0x26] = 0x0D; | |
875 | /* Device size */ | |
1eb27d69 | 876 | pfl->cfi_table[0x27] = ctz32(pfl->chip_len); |
29133e9a FB |
877 | /* Flash device interface (8 & 16 bits) */ |
878 | pfl->cfi_table[0x28] = 0x02; | |
879 | pfl->cfi_table[0x29] = 0x00; | |
880 | /* Max number of bytes in multi-bytes write */ | |
95d1f3ed JM |
881 | /* XXX: disable buffered write as it's not supported */ |
882 | // pfl->cfi_table[0x2A] = 0x05; | |
883 | pfl->cfi_table[0x2A] = 0x00; | |
29133e9a | 884 | pfl->cfi_table[0x2B] = 0x00; |
64659053 SC |
885 | /* Number of erase block regions */ |
886 | pfl->cfi_table[0x2c] = nb_regions; | |
887 | /* Erase block regions */ | |
888 | for (int i = 0; i < nb_regions; ++i) { | |
889 | uint32_t sector_len_per_device = pfl->sector_len[i]; | |
890 | pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1; | |
891 | pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8; | |
892 | pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8; | |
893 | pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16; | |
894 | } | |
895 | assert(0x2c + 4 * nb_regions < pri_ofs); | |
29133e9a | 896 | |
78556820 | 897 | /* Extended */ |
d6874c83 PMD |
898 | pfl->cfi_table[0x00 + pri_ofs] = 'P'; |
899 | pfl->cfi_table[0x01 + pri_ofs] = 'R'; | |
900 | pfl->cfi_table[0x02 + pri_ofs] = 'I'; | |
78556820 | 901 | |
9ac45b88 | 902 | /* Extended version 1.0 */ |
d6874c83 PMD |
903 | pfl->cfi_table[0x03 + pri_ofs] = '1'; |
904 | pfl->cfi_table[0x04 + pri_ofs] = '0'; | |
78556820 | 905 | |
9ac45b88 | 906 | /* Address sensitive unlock required. */ |
d6874c83 | 907 | pfl->cfi_table[0x05 + pri_ofs] = 0x00; |
ddb6f225 SC |
908 | /* Erase suspend to read/write. */ |
909 | pfl->cfi_table[0x06 + pri_ofs] = 0x02; | |
9ac45b88 | 910 | /* Sector protect not supported. */ |
d6874c83 | 911 | pfl->cfi_table[0x07 + pri_ofs] = 0x00; |
9ac45b88 | 912 | /* Temporary sector unprotect not supported. */ |
d6874c83 | 913 | pfl->cfi_table[0x08 + pri_ofs] = 0x00; |
78556820 | 914 | |
9ac45b88 | 915 | /* Sector protect/unprotect scheme. */ |
d6874c83 | 916 | pfl->cfi_table[0x09 + pri_ofs] = 0x00; |
78556820 | 917 | |
9ac45b88 | 918 | /* Simultaneous operation not supported. */ |
d6874c83 | 919 | pfl->cfi_table[0x0a + pri_ofs] = 0x00; |
9ac45b88 | 920 | /* Burst mode not supported. */ |
d6874c83 | 921 | pfl->cfi_table[0x0b + pri_ofs] = 0x00; |
c2c1bf44 PMD |
922 | /* Page mode not supported. */ |
923 | pfl->cfi_table[0x0c + pri_ofs] = 0x00; | |
924 | assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); | |
368a354f PC |
925 | } |
926 | ||
927 | static Property pflash_cfi02_properties[] = { | |
16434065 | 928 | DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), |
64659053 SC |
929 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), |
930 | DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0), | |
931 | DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), | |
932 | DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), | |
933 | DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), | |
934 | DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), | |
935 | DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), | |
936 | DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), | |
937 | DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), | |
938 | DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), | |
16434065 MA |
939 | DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), |
940 | DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), | |
941 | DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), | |
942 | DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), | |
943 | DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), | |
944 | DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), | |
945 | DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), | |
946 | DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), | |
947 | DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), | |
948 | DEFINE_PROP_STRING("name", PFlashCFI02, name), | |
368a354f PC |
949 | DEFINE_PROP_END_OF_LIST(), |
950 | }; | |
951 | ||
d80cf1eb SC |
952 | static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) |
953 | { | |
e7b62741 | 954 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d80cf1eb | 955 | timer_del(&pfl->timer); |
ddb6f225 | 956 | g_free(pfl->sector_erase_map); |
d80cf1eb SC |
957 | } |
958 | ||
368a354f PC |
959 | static void pflash_cfi02_class_init(ObjectClass *klass, void *data) |
960 | { | |
961 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 962 | |
da3bd642 | 963 | dc->realize = pflash_cfi02_realize; |
d80cf1eb | 964 | dc->unrealize = pflash_cfi02_unrealize; |
368a354f | 965 | dc->props = pflash_cfi02_properties; |
df6f9318 | 966 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
967 | } |
968 | ||
969 | static const TypeInfo pflash_cfi02_info = { | |
e7b62741 | 970 | .name = TYPE_PFLASH_CFI02, |
368a354f | 971 | .parent = TYPE_SYS_BUS_DEVICE, |
16434065 | 972 | .instance_size = sizeof(PFlashCFI02), |
368a354f PC |
973 | .class_init = pflash_cfi02_class_init, |
974 | }; | |
975 | ||
976 | static void pflash_cfi02_register_types(void) | |
977 | { | |
978 | type_register_static(&pflash_cfi02_info); | |
979 | } | |
980 | ||
981 | type_init(pflash_cfi02_register_types) | |
982 | ||
16434065 | 983 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, |
940d5b13 | 984 | const char *name, |
16434065 MA |
985 | hwaddr size, |
986 | BlockBackend *blk, | |
ce14710f | 987 | uint32_t sector_len, |
16434065 MA |
988 | int nb_mappings, int width, |
989 | uint16_t id0, uint16_t id1, | |
990 | uint16_t id2, uint16_t id3, | |
991 | uint16_t unlock_addr0, | |
992 | uint16_t unlock_addr1, | |
993 | int be) | |
368a354f | 994 | { |
e7b62741 | 995 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); |
368a354f | 996 | |
9b3d111a MA |
997 | if (blk) { |
998 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f | 999 | } |
ce14710f MA |
1000 | assert(size % sector_len == 0); |
1001 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); | |
368a354f PC |
1002 | qdev_prop_set_uint32(dev, "sector-length", sector_len); |
1003 | qdev_prop_set_uint8(dev, "width", width); | |
1004 | qdev_prop_set_uint8(dev, "mappings", nb_mappings); | |
1005 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
1006 | qdev_prop_set_uint16(dev, "id0", id0); | |
1007 | qdev_prop_set_uint16(dev, "id1", id1); | |
1008 | qdev_prop_set_uint16(dev, "id2", id2); | |
1009 | qdev_prop_set_uint16(dev, "id3", id3); | |
1010 | qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); | |
1011 | qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); | |
1012 | qdev_prop_set_string(dev, "name", name); | |
1013 | qdev_init_nofail(dev); | |
1014 | ||
3509c396 | 1015 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
e7b62741 | 1016 | return PFLASH_CFI02(dev); |
29133e9a | 1017 | } |