[thirdparty/qemu.git] / hw / char / imx_serial.c

/*
 * IMX31 UARTS
 *
 * Copyright (c) 2008 OKL
 * Originally Written by Hans Jiang
 * Copyright (c) 2011 NICTA Pty Ltd.
 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * This is a `bare-bones' implementation of the IMX series serial ports.
 * TODO:
 *  -- implement FIFOs.  The real hardware has 32 word transmit
 *                       and receive FIFOs; we currently use a 1-char buffer
 *  -- implement DMA
 *  -- implement BAUD-rate and modem lines, for when the backend
 *     is a real serial device.
 */

#include "qemu/osdep.h"
#include "hw/char/imx_serial.h"
#include "hw/irq.h"
#include "sysemu/sysemu.h"
#include "qemu/log.h"
#include "qemu/module.h"

#ifndef DEBUG_IMX_UART
#define DEBUG_IMX_UART 0
#endif

#define DPRINTF(fmt, args...) \
    do { \
        if (DEBUG_IMX_UART) { \
            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
                                             __func__, ##args); \
        } \
    } while (0)

static const VMStateDescription vmstate_imx_serial = {
    .name = TYPE_IMX_SERIAL,
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(readbuff, IMXSerialState),
        VMSTATE_UINT32(usr1, IMXSerialState),
        VMSTATE_UINT32(usr2, IMXSerialState),
        VMSTATE_UINT32(ucr1, IMXSerialState),
        VMSTATE_UINT32(uts1, IMXSerialState),
        VMSTATE_UINT32(onems, IMXSerialState),
        VMSTATE_UINT32(ufcr, IMXSerialState),
        VMSTATE_UINT32(ubmr, IMXSerialState),
        VMSTATE_UINT32(ubrc, IMXSerialState),
        VMSTATE_UINT32(ucr3, IMXSerialState),
        VMSTATE_UINT32(ucr4, IMXSerialState),
        VMSTATE_END_OF_LIST()
    },
};

static void imx_update(IMXSerialState *s)
{
    uint32_t usr1;
    uint32_t usr2;
    uint32_t mask;

    /*
     * Lucky for us TRDY and RRDY has the same offset in both USR1 and
     * UCR1, so we can get away with something as simple as the
     * following:
     */
    usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
    /*
     * Bits that we want in USR2 are not as conveniently laid out,
     * unfortunately.
     */
    mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
    /*
     * TCEN and TXDC are both bit 3
     * RDR and DREN are both bit 0
     */
    mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);

    usr2 = s->usr2 & mask;

    qemu_set_irq(s->irq, usr1 || usr2);
}

static void imx_serial_reset(IMXSerialState *s)
{

    s->usr1 = USR1_TRDY | USR1_RXDS;
    /*
     * Fake attachment of a terminal: assert RTS.
     */
    s->usr1 |= USR1_RTSS;
    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
    s->ucr1 = 0;
    s->ucr2 = UCR2_SRST;
    s->ucr3 = 0x700;
    s->ubmr = 0;
    s->ubrc = 4;
    s->readbuff = URXD_ERR;
}

static void imx_serial_reset_at_boot(DeviceState *dev)
{
    IMXSerialState *s = IMX_SERIAL(dev);

    imx_serial_reset(s);

    /*
     * enable the uart on boot, so messages from the linux decompresser
     * are visible.  On real hardware this is done by the boot rom
     * before anything else is loaded.
     */
    s->ucr1 = UCR1_UARTEN;
    s->ucr2 = UCR2_TXEN;

}

static uint64_t imx_serial_read(void *opaque, hwaddr offset,
                                unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    uint32_t c;

    DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);

    switch (offset >> 2) {
    case 0x0: /* URXD */
        c = s->readbuff;
        if (!(s->uts1 & UTS1_RXEMPTY)) {
            /* Character is valid */
            c |= URXD_CHARRDY;
            s->usr1 &= ~USR1_RRDY;
            s->usr2 &= ~USR2_RDR;
            s->uts1 |= UTS1_RXEMPTY;
            imx_update(s);
            qemu_chr_fe_accept_input(&s->chr);
        }
        return c;

    case 0x20: /* UCR1 */
        return s->ucr1;

    case 0x21: /* UCR2 */
        return s->ucr2;

    case 0x25: /* USR1 */
        return s->usr1;

    case 0x26: /* USR2 */
        return s->usr2;

    case 0x2A: /* BRM Modulator */
        return s->ubmr;

    case 0x2B: /* Baud Rate Count */
        return s->ubrc;

    case 0x2d: /* Test register */
        return s->uts1;

    case 0x24: /* UFCR */
        return s->ufcr;

    case 0x2c:
        return s->onems;

    case 0x22: /* UCR3 */
        return s->ucr3;

    case 0x23: /* UCR4 */
        return s->ucr4;

    case 0x29: /* BRM Incremental */
        return 0x0; /* TODO */

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
        return 0;
    }
}

static void imx_serial_write(void *opaque, hwaddr offset,
                             uint64_t value, unsigned size)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
    unsigned char ch;

    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
            offset, (unsigned int)value, chr ? chr->label : "NODEV");

    switch (offset >> 2) {
    case 0x10: /* UTXD */
        ch = value;
        if (s->ucr2 & UCR2_TXEN) {
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
            s->usr1 &= ~USR1_TRDY;
            s->usr2 &= ~USR2_TXDC;
            imx_update(s);
            s->usr1 |= USR1_TRDY;
            s->usr2 |= USR2_TXDC;
            imx_update(s);
        }
        break;

    case 0x20: /* UCR1 */
        s->ucr1 = value & 0xffff;

        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);

        imx_update(s);
        break;

    case 0x21: /* UCR2 */
        /*
         * Only a few bits in control register 2 are implemented as yet.
         * If it's intended to use a real serial device as a back-end, this
         * register will have to be implemented more fully.
         */
        if (!(value & UCR2_SRST)) {
            imx_serial_reset(s);
            imx_update(s);
            value |= UCR2_SRST;
        }
        if (value & UCR2_RXEN) {
            if (!(s->ucr2 & UCR2_RXEN)) {
                qemu_chr_fe_accept_input(&s->chr);
            }
        }
        s->ucr2 = value & 0xffff;
        break;

    case 0x25: /* USR1 */
        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
        s->usr1 &= ~value;
        break;

    case 0x26: /* USR2 */
        /*
         * Writing 1 to some bits clears them; all other
         * values are ignored
         */
        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |
                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
        s->usr2 &= ~value;
        break;

    /*
     * Linux expects to see what it writes to these registers
     * We don't currently alter the baud rate
     */
    case 0x29: /* UBIR */
        s->ubrc = value & 0xffff;
        break;

    case 0x2a: /* UBMR */
        s->ubmr = value & 0xffff;
        break;

    case 0x2c: /* One ms reg */
        s->onems = value & 0xffff;
        break;

    case 0x24: /* FIFO control register */
        s->ufcr = value & 0xffff;
        break;

    case 0x22: /* UCR3 */
        s->ucr3 = value & 0xffff;
        break;

    case 0x23: /* UCR4 */
        s->ucr4 = value & 0xffff;
        imx_update(s);
        break;

    case 0x2d: /* UTS1 */
        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
        /* TODO */
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
    }
}

static int imx_can_receive(void *opaque)
{
    IMXSerialState *s = (IMXSerialState *)opaque;
    return !(s->usr1 & USR1_RRDY);
}

static void imx_put_data(void *opaque, uint32_t value)
{
    IMXSerialState *s = (IMXSerialState *)opaque;

    DPRINTF("received char\n");

    s->usr1 |= USR1_RRDY;
    s->usr2 |= USR2_RDR;
    s->uts1 &= ~UTS1_RXEMPTY;
    s->readbuff = value;
    if (value & URXD_BRK) {
        s->usr2 |= USR2_BRCD;
    }
    imx_update(s);
}

static void imx_receive(void *opaque, const uint8_t *buf, int size)
{
    imx_put_data(opaque, *buf);
}

static void imx_event(void *opaque, int event)
{
    if (event == CHR_EVENT_BREAK) {
        imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR);
    }
}


static const struct MemoryRegionOps imx_serial_ops = {
    .read = imx_serial_read,
    .write = imx_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void imx_serial_realize(DeviceState *dev, Error **errp)
{
    IMXSerialState *s = IMX_SERIAL(dev);

    DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));

    qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
                             imx_event, NULL, s, NULL, true);
}

static void imx_serial_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    IMXSerialState *s = IMX_SERIAL(obj);

    memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
                          TYPE_IMX_SERIAL, 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
}

static Property imx_serial_properties[] = {
    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void imx_serial_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = imx_serial_realize;
    dc->vmsd = &vmstate_imx_serial;
    dc->reset = imx_serial_reset_at_boot;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->desc = "i.MX series UART";
    dc->props = imx_serial_properties;
}

static const TypeInfo imx_serial_info = {
    .name           = TYPE_IMX_SERIAL,
    .parent         = TYPE_SYS_BUS_DEVICE,
    .instance_size  = sizeof(IMXSerialState),
    .instance_init  = imx_serial_init,
    .class_init     = imx_serial_class_init,
};

static void imx_serial_register_types(void)
{
    type_register_static(&imx_serial_info);
}

type_init(imx_serial_register_types)
Commit	Line	Data
40b6f911 PC	1	/*
	2	* IMX31 UARTS
	3	*
	4	* Copyright (c) 2008 OKL
	5	* Originally Written by Hans Jiang
	6	* Copyright (c) 2011 NICTA Pty Ltd.
cd0bda20	7	* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
40b6f911 PC	8	*
	9	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	10	* See the COPYING file in the top-level directory.
	11	*
	12	* This is a `bare-bones' implementation of the IMX series serial ports.
	13	* TODO:
	14	* -- implement FIFOs. The real hardware has 32 word transmit
	15	* and receive FIFOs; we currently use a 1-char buffer
	16	* -- implement DMA
	17	* -- implement BAUD-rate and modem lines, for when the backend
	18	* is a real serial device.
	19	*/
	20
8ef94f0b	21	#include "qemu/osdep.h"
cd0bda20	22	#include "hw/char/imx_serial.h"
64552b6b	23	#include "hw/irq.h"
9c17d615	24	#include "sysemu/sysemu.h"
03dd024f	25	#include "qemu/log.h"
0b8fa32f	26	#include "qemu/module.h"
40b6f911	27
8ccce77c JCD	28	#ifndef DEBUG_IMX_UART
8ccce77c JCD	29	#define DEBUG_IMX_UART 0
40b6f911 PC	30	#endif
40b6f911 PC	31
8ccce77c JCD	32	#define DPRINTF(fmt, args...) \
	33	do { \
	34	if (DEBUG_IMX_UART) { \
	35	fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
	36	__func__, ##args); \
	37	} \
	38	} while (0)
40b6f911	39
40b6f911	40	static const VMStateDescription vmstate_imx_serial = {
fa2650a3	41	.name = TYPE_IMX_SERIAL,
46d3fb63 AS	42	.version_id = 2,
46d3fb63 AS	43	.minimum_version_id = 2,
40b6f911 PC	44	.fields = (VMStateField[]) {
	45	VMSTATE_INT32(readbuff, IMXSerialState),
	46	VMSTATE_UINT32(usr1, IMXSerialState),
	47	VMSTATE_UINT32(usr2, IMXSerialState),
	48	VMSTATE_UINT32(ucr1, IMXSerialState),
	49	VMSTATE_UINT32(uts1, IMXSerialState),
	50	VMSTATE_UINT32(onems, IMXSerialState),
	51	VMSTATE_UINT32(ufcr, IMXSerialState),
	52	VMSTATE_UINT32(ubmr, IMXSerialState),
	53	VMSTATE_UINT32(ubrc, IMXSerialState),
	54	VMSTATE_UINT32(ucr3, IMXSerialState),
46d3fb63	55	VMSTATE_UINT32(ucr4, IMXSerialState),
40b6f911 PC	56	VMSTATE_END_OF_LIST()
	57	},
	58	};
	59
40b6f911 PC	60	static void imx_update(IMXSerialState *s)
40b6f911 PC	61	{
824e4a12 AS	62	uint32_t usr1;
	63	uint32_t usr2;
	64	uint32_t mask;
40b6f911	65
824e4a12 AS	66	/*
	67	* Lucky for us TRDY and RRDY has the same offset in both USR1 and
	68	* UCR1, so we can get away with something as simple as the
	69	* following:
	70	*/
	71	usr1 = s->usr1 & s->ucr1 & (USR1_TRDY \| USR1_RRDY);
	72	/*
	73	* Bits that we want in USR2 are not as conveniently laid out,
	74	* unfortunately.
	75	*/
	76	mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
46d3fb63 AS	77	/*
46d3fb63 AS	78	* TCEN and TXDC are both bit 3
3c54cf77	79	* RDR and DREN are both bit 0
46d3fb63	80	*/
3c54cf77	81	mask \|= s->ucr4 & (UCR4_TCEN \| UCR4_DREN);
46d3fb63	82
824e4a12	83	usr2 = s->usr2 & mask;
40b6f911	84
824e4a12	85	qemu_set_irq(s->irq, usr1 \|\| usr2);
40b6f911 PC	86	}
	87
	88	static void imx_serial_reset(IMXSerialState *s)
	89	{
	90
	91	s->usr1 = USR1_TRDY \| USR1_RXDS;
	92	/*
	93	* Fake attachment of a terminal: assert RTS.
	94	*/
	95	s->usr1 \|= USR1_RTSS;
	96	s->usr2 = USR2_TXFE \| USR2_TXDC \| USR2_DCDIN;
	97	s->uts1 = UTS1_RXEMPTY \| UTS1_TXEMPTY;
	98	s->ucr1 = 0;
	99	s->ucr2 = UCR2_SRST;
	100	s->ucr3 = 0x700;
	101	s->ubmr = 0;
	102	s->ubrc = 4;
	103	s->readbuff = URXD_ERR;
	104	}
	105
	106	static void imx_serial_reset_at_boot(DeviceState *dev)
	107	{
8d8e3481	108	IMXSerialState *s = IMX_SERIAL(dev);
40b6f911 PC	109
	110	imx_serial_reset(s);
	111
	112	/*
	113	* enable the uart on boot, so messages from the linux decompresser
	114	* are visible. On real hardware this is done by the boot rom
	115	* before anything else is loaded.
	116	*/
	117	s->ucr1 = UCR1_UARTEN;
	118	s->ucr2 = UCR2_TXEN;
	119
	120	}
	121
a8170e5e	122	static uint64_t imx_serial_read(void *opaque, hwaddr offset,
40b6f911 PC	123	unsigned size)
	124	{
	125	IMXSerialState s = (IMXSerialState )opaque;
	126	uint32_t c;
	127
8ccce77c JCD	128	DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
8ccce77c JCD	129
40b6f911 PC	130	switch (offset >> 2) {
	131	case 0x0: /* URXD */
	132	c = s->readbuff;
	133	if (!(s->uts1 & UTS1_RXEMPTY)) {
	134	/* Character is valid */
	135	c \|= URXD_CHARRDY;
	136	s->usr1 &= ~USR1_RRDY;
	137	s->usr2 &= ~USR2_RDR;
	138	s->uts1 \|= UTS1_RXEMPTY;
	139	imx_update(s);
fa394ed6	140	qemu_chr_fe_accept_input(&s->chr);
40b6f911 PC	141	}
	142	return c;
	143
	144	case 0x20: /* UCR1 */
	145	return s->ucr1;
	146
	147	case 0x21: /* UCR2 */
	148	return s->ucr2;
	149
	150	case 0x25: /* USR1 */
	151	return s->usr1;
	152
	153	case 0x26: /* USR2 */
	154	return s->usr2;
	155
	156	case 0x2A: /* BRM Modulator */
	157	return s->ubmr;
	158
	159	case 0x2B: /* Baud Rate Count */
	160	return s->ubrc;
	161
	162	case 0x2d: /* Test register */
	163	return s->uts1;
	164
	165	case 0x24: /* UFCR */
	166	return s->ufcr;
	167
	168	case 0x2c:
	169	return s->onems;
	170
	171	case 0x22: /* UCR3 */
	172	return s->ucr3;
	173
	174	case 0x23: /* UCR4 */
46d3fb63 AS	175	return s->ucr4;
46d3fb63 AS	176
40b6f911 PC	177	case 0x29: /* BRM Incremental */
	178	return 0x0; /* TODO */
	179
	180	default:
8ccce77c JCD	181	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
8ccce77c JCD	182	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	183	return 0;
	184	}
	185	}
	186
a8170e5e	187	static void imx_serial_write(void *opaque, hwaddr offset,
fa2650a3	188	uint64_t value, unsigned size)
40b6f911 PC	189	{
40b6f911 PC	190	IMXSerialState s = (IMXSerialState )opaque;
0ec7b3e7	191	Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
40b6f911 PC	192	unsigned char ch;
40b6f911 PC	193
8ccce77c	194	DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
5345fdb4	195	offset, (unsigned int)value, chr ? chr->label : "NODEV");
40b6f911 PC	196
	197	switch (offset >> 2) {
	198	case 0x10: /* UTXD */
	199	ch = value;
	200	if (s->ucr2 & UCR2_TXEN) {
fa394ed6 MAL	201	/* XXX this blocks entire thread. Rewrite to use
	202	* qemu_chr_fe_write and background I/O callbacks */
	203	qemu_chr_fe_write_all(&s->chr, &ch, 1);
40b6f911	204	s->usr1 &= ~USR1_TRDY;
46d3fb63	205	s->usr2 &= ~USR2_TXDC;
40b6f911 PC	206	imx_update(s);
40b6f911 PC	207	s->usr1 \|= USR1_TRDY;
46d3fb63	208	s->usr2 \|= USR2_TXDC;
40b6f911 PC	209	imx_update(s);
	210	}
	211	break;
	212
	213	case 0x20: /* UCR1 */
	214	s->ucr1 = value & 0xffff;
8ccce77c	215
40b6f911	216	DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
8ccce77c	217
40b6f911 PC	218	imx_update(s);
	219	break;
	220
	221	case 0x21: /* UCR2 */
	222	/*
	223	* Only a few bits in control register 2 are implemented as yet.
	224	* If it's intended to use a real serial device as a back-end, this
	225	* register will have to be implemented more fully.
	226	*/
	227	if (!(value & UCR2_SRST)) {
	228	imx_serial_reset(s);
	229	imx_update(s);
	230	value \|= UCR2_SRST;
	231	}
	232	if (value & UCR2_RXEN) {
	233	if (!(s->ucr2 & UCR2_RXEN)) {
fa394ed6	234	qemu_chr_fe_accept_input(&s->chr);
40b6f911 PC	235	}
	236	}
	237	s->ucr2 = value & 0xffff;
	238	break;
	239
	240	case 0x25: /* USR1 */
	241	value &= USR1_AWAKE \| USR1_AIRINT \| USR1_DTRD \| USR1_AGTIM \|
fa2650a3	242	USR1_FRAMERR \| USR1_ESCF \| USR1_RTSD \| USR1_PARTYER;
40b6f911 PC	243	s->usr1 &= ~value;
	244	break;
	245
	246	case 0x26: /* USR2 */
fa2650a3 JCD	247	/*
	248	* Writing 1 to some bits clears them; all other
	249	* values are ignored
	250	*/
40b6f911	251	value &= USR2_ADET \| USR2_DTRF \| USR2_IDLE \| USR2_ACST \|
fa2650a3 JCD	252	USR2_RIDELT \| USR2_IRINT \| USR2_WAKE \|
fa2650a3 JCD	253	USR2_DCDDELT \| USR2_RTSF \| USR2_BRCD \| USR2_ORE;
40b6f911 PC	254	s->usr2 &= ~value;
	255	break;
	256
fa2650a3 JCD	257	/*
	258	* Linux expects to see what it writes to these registers
	259	* We don't currently alter the baud rate
	260	*/
40b6f911 PC	261	case 0x29: /* UBIR */
	262	s->ubrc = value & 0xffff;
	263	break;
	264
	265	case 0x2a: /* UBMR */
	266	s->ubmr = value & 0xffff;
	267	break;
	268
	269	case 0x2c: /* One ms reg */
	270	s->onems = value & 0xffff;
	271	break;
	272
	273	case 0x24: /* FIFO control register */
	274	s->ufcr = value & 0xffff;
	275	break;
	276
	277	case 0x22: /* UCR3 */
	278	s->ucr3 = value & 0xffff;
	279	break;
	280
40b6f911	281	case 0x23: /* UCR4 */
46d3fb63 AS	282	s->ucr4 = value & 0xffff;
	283	imx_update(s);
	284	break;
	285
	286	case 0x2d: /* UTS1 */
8ccce77c JCD	287	qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
8ccce77c JCD	288	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	289	/* TODO */
	290	break;
	291
	292	default:
8ccce77c JCD	293	qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
8ccce77c JCD	294	HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
40b6f911 PC	295	}
	296	}
	297
	298	static int imx_can_receive(void *opaque)
	299	{
	300	IMXSerialState s = (IMXSerialState )opaque;
	301	return !(s->usr1 & USR1_RRDY);
	302	}
	303
	304	static void imx_put_data(void *opaque, uint32_t value)
	305	{
	306	IMXSerialState s = (IMXSerialState )opaque;
8ccce77c	307
40b6f911	308	DPRINTF("received char\n");
8ccce77c	309
40b6f911 PC	310	s->usr1 \|= USR1_RRDY;
	311	s->usr2 \|= USR2_RDR;
	312	s->uts1 &= ~UTS1_RXEMPTY;
	313	s->readbuff = value;
478a573a TP	314	if (value & URXD_BRK) {
	315	s->usr2 \|= USR2_BRCD;
	316	}
40b6f911 PC	317	imx_update(s);
	318	}
	319
	320	static void imx_receive(void opaque, const uint8_t buf, int size)
	321	{
	322	imx_put_data(opaque, *buf);
	323	}
	324
	325	static void imx_event(void *opaque, int event)
	326	{
	327	if (event == CHR_EVENT_BREAK) {
478a573a	328	imx_put_data(opaque, URXD_BRK \| URXD_FRMERR \| URXD_ERR);
40b6f911 PC	329	}
	330	}
	331
	332
	333	static const struct MemoryRegionOps imx_serial_ops = {
	334	.read = imx_serial_read,
	335	.write = imx_serial_write,
	336	.endianness = DEVICE_NATIVE_ENDIAN,
	337	};
	338
f6c64000	339	static void imx_serial_realize(DeviceState dev, Error *errp)
40b6f911	340	{
8d8e3481	341	IMXSerialState *s = IMX_SERIAL(dev);
40b6f911	342
fa394ed6 MAL	343	DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
	344
	345	qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
81517ba3	346	imx_event, NULL, s, NULL, true);
f6c64000 JCD	347	}
	348
	349	static void imx_serial_init(Object *obj)
	350	{
	351	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	352	IMXSerialState *s = IMX_SERIAL(obj);
40b6f911	353
f6c64000 JCD	354	memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
	355	TYPE_IMX_SERIAL, 0x1000);
	356	sysbus_init_mmio(sbd, &s->iomem);
	357	sysbus_init_irq(sbd, &s->irq);
40b6f911 PC	358	}
40b6f911 PC	359
f6c64000	360	static Property imx_serial_properties[] = {
40b6f911 PC	361	DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
	362	DEFINE_PROP_END_OF_LIST(),
	363	};
	364
	365	static void imx_serial_class_init(ObjectClass klass, void data)
	366	{
	367	DeviceClass *dc = DEVICE_CLASS(klass);
40b6f911	368
f6c64000	369	dc->realize = imx_serial_realize;
40b6f911 PC	370	dc->vmsd = &vmstate_imx_serial;
40b6f911 PC	371	dc->reset = imx_serial_reset_at_boot;
125ee0ed	372	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
40b6f911	373	dc->desc = "i.MX series UART";
f6c64000	374	dc->props = imx_serial_properties;
40b6f911 PC	375	}
40b6f911 PC	376
8c43a6f0	377	static const TypeInfo imx_serial_info = {
f6c64000 JCD	378	.name = TYPE_IMX_SERIAL,
	379	.parent = TYPE_SYS_BUS_DEVICE,
	380	.instance_size = sizeof(IMXSerialState),
	381	.instance_init = imx_serial_init,
	382	.class_init = imx_serial_class_init,
40b6f911 PC	383	};
	384
	385	static void imx_serial_register_types(void)
	386	{
	387	type_register_static(&imx_serial_info);
	388	}
	389
	390	type_init(imx_serial_register_types)