[thirdparty/qemu.git] / hw / char / mcf_uart.c

/*
 * ColdFire UART emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licensed under the GPL
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "chardev/char-fe.h"
#include "qom/object.h"

struct mcf_uart_state {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t mr[2];
    uint8_t sr;
    uint8_t isr;
    uint8_t imr;
    uint8_t bg1;
    uint8_t bg2;
    uint8_t fifo[4];
    uint8_t tb;
    int current_mr;
    int fifo_len;
    int tx_enabled;
    int rx_enabled;
    qemu_irq irq;
    CharBackend chr;
};
typedef struct mcf_uart_state mcf_uart_state;

#define TYPE_MCF_UART "mcf-uart"
#define MCF_UART(obj) OBJECT_CHECK(mcf_uart_state, (obj), TYPE_MCF_UART)

/* UART Status Register bits.  */
#define MCF_UART_RxRDY  0x01
#define MCF_UART_FFULL  0x02
#define MCF_UART_TxRDY  0x04
#define MCF_UART_TxEMP  0x08
#define MCF_UART_OE     0x10
#define MCF_UART_PE     0x20
#define MCF_UART_FE     0x40
#define MCF_UART_RB     0x80

/* Interrupt flags.  */
#define MCF_UART_TxINT  0x01
#define MCF_UART_RxINT  0x02
#define MCF_UART_DBINT  0x04
#define MCF_UART_COSINT 0x80

/* UMR1 flags.  */
#define MCF_UART_BC0    0x01
#define MCF_UART_BC1    0x02
#define MCF_UART_PT     0x04
#define MCF_UART_PM0    0x08
#define MCF_UART_PM1    0x10
#define MCF_UART_ERR    0x20
#define MCF_UART_RxIRQ  0x40
#define MCF_UART_RxRTS  0x80

static void mcf_uart_update(mcf_uart_state *s)
{
    s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
    if (s->sr & MCF_UART_TxRDY)
        s->isr |= MCF_UART_TxINT;
    if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
                  ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
        s->isr |= MCF_UART_RxINT;

    qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}

uint64_t mcf_uart_read(void *opaque, hwaddr addr,
                       unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        return s->mr[s->current_mr];
    case 0x04:
        return s->sr;
    case 0x0c:
        {
            uint8_t val;
            int i;

            if (s->fifo_len == 0)
                return 0;

            val = s->fifo[0];
            s->fifo_len--;
            for (i = 0; i < s->fifo_len; i++)
                s->fifo[i] = s->fifo[i + 1];
            s->sr &= ~MCF_UART_FFULL;
            if (s->fifo_len == 0)
                s->sr &= ~MCF_UART_RxRDY;
            mcf_uart_update(s);
            qemu_chr_fe_accept_input(&s->chr);
            return val;
        }
    case 0x10:
        /* TODO: Implement IPCR.  */
        return 0;
    case 0x14:
        return s->isr;
    case 0x18:
        return s->bg1;
    case 0x1c:
        return s->bg2;
    default:
        return 0;
    }
}

/* Update TxRDY flag and set data if present and enabled.  */
static void mcf_uart_do_tx(mcf_uart_state *s)
{
    if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
        /* XXX this blocks entire thread. Rewrite to use
         * qemu_chr_fe_write and background I/O callbacks */
        qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
        s->sr |= MCF_UART_TxEMP;
    }
    if (s->tx_enabled) {
        s->sr |= MCF_UART_TxRDY;
    } else {
        s->sr &= ~MCF_UART_TxRDY;
    }
}

static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
{
    /* Misc command.  */
    switch ((cmd >> 4) & 7) {
    case 0: /* No-op.  */
        break;
    case 1: /* Reset mode register pointer.  */
        s->current_mr = 0;
        break;
    case 2: /* Reset receiver.  */
        s->rx_enabled = 0;
        s->fifo_len = 0;
        s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
        break;
    case 3: /* Reset transmitter.  */
        s->tx_enabled = 0;
        s->sr |= MCF_UART_TxEMP;
        s->sr &= ~MCF_UART_TxRDY;
        break;
    case 4: /* Reset error status.  */
        break;
    case 5: /* Reset break-change interrupt.  */
        s->isr &= ~MCF_UART_DBINT;
        break;
    case 6: /* Start break.  */
    case 7: /* Stop break.  */
        break;
    }

    /* Transmitter command.  */
    switch ((cmd >> 2) & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->tx_enabled = 1;
        mcf_uart_do_tx(s);
        break;
    case 2: /* Disable.  */
        s->tx_enabled = 0;
        mcf_uart_do_tx(s);
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad TX command\n");
        break;
    }

    /* Receiver command.  */
    switch (cmd & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->rx_enabled = 1;
        break;
    case 2:
        s->rx_enabled = 0;
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad RX command\n");
        break;
    }
}

void mcf_uart_write(void *opaque, hwaddr addr,
                    uint64_t val, unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        s->mr[s->current_mr] = val;
        s->current_mr = 1;
        break;
    case 0x04:
        /* CSR is ignored.  */
        break;
    case 0x08: /* Command Register.  */
        mcf_do_command(s, val);
        break;
    case 0x0c: /* Transmit Buffer.  */
        s->sr &= ~MCF_UART_TxEMP;
        s->tb = val;
        mcf_uart_do_tx(s);
        break;
    case 0x10:
        /* ACR is ignored.  */
        break;
    case 0x14:
        s->imr = val;
        break;
    default:
        break;
    }
    mcf_uart_update(s);
}

static void mcf_uart_reset(DeviceState *dev)
{
    mcf_uart_state *s = MCF_UART(dev);

    s->fifo_len = 0;
    s->mr[0] = 0;
    s->mr[1] = 0;
    s->sr = MCF_UART_TxEMP;
    s->tx_enabled = 0;
    s->rx_enabled = 0;
    s->isr = 0;
    s->imr = 0;
}

static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
{
    /* Break events overwrite the last byte if the fifo is full.  */
    if (s->fifo_len == 4)
        s->fifo_len--;

    s->fifo[s->fifo_len] = data;
    s->fifo_len++;
    s->sr |= MCF_UART_RxRDY;
    if (s->fifo_len == 4)
        s->sr |= MCF_UART_FFULL;

    mcf_uart_update(s);
}

static void mcf_uart_event(void *opaque, QEMUChrEvent event)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    switch (event) {
    case CHR_EVENT_BREAK:
        s->isr |= MCF_UART_DBINT;
        mcf_uart_push_byte(s, 0);
        break;
    default:
        break;
    }
}

static int mcf_uart_can_receive(void *opaque)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
}

static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    mcf_uart_push_byte(s, buf[0]);
}

static const MemoryRegionOps mcf_uart_ops = {
    .read = mcf_uart_read,
    .write = mcf_uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mcf_uart_instance_init(Object *obj)
{
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    mcf_uart_state *s = MCF_UART(dev);

    memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_irq(dev, &s->irq);
}

static void mcf_uart_realize(DeviceState *dev, Error **errp)
{
    mcf_uart_state *s = MCF_UART(dev);

    qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
                             mcf_uart_event, NULL, s, NULL, true);
}

static Property mcf_uart_properties[] = {
    DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void mcf_uart_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = mcf_uart_realize;
    dc->reset = mcf_uart_reset;
    device_class_set_props(dc, mcf_uart_properties);
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo mcf_uart_info = {
    .name          = TYPE_MCF_UART,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mcf_uart_state),
    .instance_init = mcf_uart_instance_init,
    .class_init    = mcf_uart_class_init,
};

static void mcf_uart_register(void)
{
    type_register_static(&mcf_uart_info);
}

type_init(mcf_uart_register)

void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv)
{
    DeviceState  *dev;

    dev = qdev_new(TYPE_MCF_UART);
    if (chrdrv) {
        qdev_prop_set_chr(dev, "chardev", chrdrv);
    }
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
{
    DeviceState  *dev;

    dev = mcf_uart_init(irq, chrdrv);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
}
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* ColdFire UART emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
8e31bf38	6	* This code is licensed under the GPL
20dcee94	7	*/
0b8fa32f	8
0430891c	9	#include "qemu/osdep.h"
64552b6b	10	#include "hw/irq.h"
d9ff1d35	11	#include "hw/sysbus.h"
0b8fa32f	12	#include "qemu/module.h"
3e80f690	13	#include "qapi/error.h"
0d09e41a	14	#include "hw/m68k/mcf.h"
a27bd6c7	15	#include "hw/qdev-properties.h"
4d43a603	16	#include "chardev/char-fe.h"
db1015e9	17	#include "qom/object.h"
20dcee94	18
db1015e9	19	struct mcf_uart_state {
d9ff1d35 TH	20	SysBusDevice parent_obj;
d9ff1d35 TH	21
aa6e4986	22	MemoryRegion iomem;
20dcee94 PB	23	uint8_t mr[2];
	24	uint8_t sr;
	25	uint8_t isr;
	26	uint8_t imr;
	27	uint8_t bg1;
	28	uint8_t bg2;
	29	uint8_t fifo[4];
	30	uint8_t tb;
	31	int current_mr;
	32	int fifo_len;
	33	int tx_enabled;
	34	int rx_enabled;
	35	qemu_irq irq;
32a6ebec	36	CharBackend chr;
db1015e9 EH	37	};
db1015e9 EH	38	typedef struct mcf_uart_state mcf_uart_state;
20dcee94	39
d9ff1d35 TH	40	#define TYPE_MCF_UART "mcf-uart"
	41	#define MCF_UART(obj) OBJECT_CHECK(mcf_uart_state, (obj), TYPE_MCF_UART)
	42
20dcee94 PB	43	/* UART Status Register bits. */
	44	#define MCF_UART_RxRDY 0x01
	45	#define MCF_UART_FFULL 0x02
	46	#define MCF_UART_TxRDY 0x04
	47	#define MCF_UART_TxEMP 0x08
	48	#define MCF_UART_OE 0x10
	49	#define MCF_UART_PE 0x20
	50	#define MCF_UART_FE 0x40
	51	#define MCF_UART_RB 0x80
	52
	53	/* Interrupt flags. */
	54	#define MCF_UART_TxINT 0x01
	55	#define MCF_UART_RxINT 0x02
	56	#define MCF_UART_DBINT 0x04
	57	#define MCF_UART_COSINT 0x80
	58
	59	/* UMR1 flags. */
	60	#define MCF_UART_BC0 0x01
	61	#define MCF_UART_BC1 0x02
	62	#define MCF_UART_PT 0x04
	63	#define MCF_UART_PM0 0x08
	64	#define MCF_UART_PM1 0x10
	65	#define MCF_UART_ERR 0x20
	66	#define MCF_UART_RxIRQ 0x40
	67	#define MCF_UART_RxRTS 0x80
	68
	69	static void mcf_uart_update(mcf_uart_state *s)
	70	{
	71	s->isr &= ~(MCF_UART_TxINT \| MCF_UART_RxINT);
	72	if (s->sr & MCF_UART_TxRDY)
	73	s->isr \|= MCF_UART_TxINT;
	74	if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
	75	? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
	76	s->isr \|= MCF_UART_RxINT;
	77
	78	qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
	79	}
	80
a8170e5e	81	uint64_t mcf_uart_read(void *opaque, hwaddr addr,
aa6e4986	82	unsigned size)
20dcee94 PB	83	{
	84	mcf_uart_state s = (mcf_uart_state )opaque;
	85	switch (addr & 0x3f) {
	86	case 0x00:
	87	return s->mr[s->current_mr];
	88	case 0x04:
	89	return s->sr;
	90	case 0x0c:
	91	{
	92	uint8_t val;
	93	int i;
	94
	95	if (s->fifo_len == 0)
	96	return 0;
	97
	98	val = s->fifo[0];
	99	s->fifo_len--;
	100	for (i = 0; i < s->fifo_len; i++)
	101	s->fifo[i] = s->fifo[i + 1];
	102	s->sr &= ~MCF_UART_FFULL;
	103	if (s->fifo_len == 0)
	104	s->sr &= ~MCF_UART_RxRDY;
	105	mcf_uart_update(s);
5345fdb4	106	qemu_chr_fe_accept_input(&s->chr);
20dcee94 PB	107	return val;
	108	}
	109	case 0x10:
	110	/* TODO: Implement IPCR. */
	111	return 0;
	112	case 0x14:
	113	return s->isr;
	114	case 0x18:
	115	return s->bg1;
	116	case 0x1c:
	117	return s->bg2;
	118	default:
	119	return 0;
	120	}
	121	}
	122
	123	/* Update TxRDY flag and set data if present and enabled. */
	124	static void mcf_uart_do_tx(mcf_uart_state *s)
	125	{
	126	if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
fa394ed6 MAL	127	/* XXX this blocks entire thread. Rewrite to use
	128	* qemu_chr_fe_write and background I/O callbacks */
	129	qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
20dcee94 PB	130	s->sr \|= MCF_UART_TxEMP;
	131	}
	132	if (s->tx_enabled) {
	133	s->sr \|= MCF_UART_TxRDY;
	134	} else {
	135	s->sr &= ~MCF_UART_TxRDY;
	136	}
	137	}
	138
	139	static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
	140	{
	141	/* Misc command. */
491ffc1f	142	switch ((cmd >> 4) & 7) {
20dcee94 PB	143	case 0: /* No-op. */
	144	break;
	145	case 1: /* Reset mode register pointer. */
	146	s->current_mr = 0;
	147	break;
	148	case 2: /* Reset receiver. */
	149	s->rx_enabled = 0;
	150	s->fifo_len = 0;
	151	s->sr &= ~(MCF_UART_RxRDY \| MCF_UART_FFULL);
	152	break;
	153	case 3: /* Reset transmitter. */
	154	s->tx_enabled = 0;
	155	s->sr \|= MCF_UART_TxEMP;
	156	s->sr &= ~MCF_UART_TxRDY;
	157	break;
	158	case 4: /* Reset error status. */
	159	break;
	160	case 5: /* Reset break-change interrupt. */
	161	s->isr &= ~MCF_UART_DBINT;
	162	break;
	163	case 6: /* Start break. */
	164	case 7: /* Stop break. */
	165	break;
	166	}
	167
	168	/* Transmitter command. */
	169	switch ((cmd >> 2) & 3) {
	170	case 0: /* No-op. */
	171	break;
	172	case 1: /* Enable. */
	173	s->tx_enabled = 1;
	174	mcf_uart_do_tx(s);
	175	break;
	176	case 2: /* Disable. */
	177	s->tx_enabled = 0;
	178	mcf_uart_do_tx(s);
	179	break;
	180	case 3: /* Reserved. */
	181	fprintf(stderr, "mcf_uart: Bad TX command\n");
	182	break;
	183	}
	184
	185	/* Receiver command. */
	186	switch (cmd & 3) {
	187	case 0: /* No-op. */
	188	break;
	189	case 1: /* Enable. */
	190	s->rx_enabled = 1;
	191	break;
	192	case 2:
	193	s->rx_enabled = 0;
	194	break;
	195	case 3: /* Reserved. */
	196	fprintf(stderr, "mcf_uart: Bad RX command\n");
	197	break;
	198	}
	199	}
	200
a8170e5e	201	void mcf_uart_write(void *opaque, hwaddr addr,
aa6e4986	202	uint64_t val, unsigned size)
20dcee94 PB	203	{
	204	mcf_uart_state s = (mcf_uart_state )opaque;
	205	switch (addr & 0x3f) {
	206	case 0x00:
	207	s->mr[s->current_mr] = val;
	208	s->current_mr = 1;
	209	break;
	210	case 0x04:
	211	/* CSR is ignored. */
	212	break;
	213	case 0x08: /* Command Register. */
	214	mcf_do_command(s, val);
	215	break;
	216	case 0x0c: /* Transmit Buffer. */
	217	s->sr &= ~MCF_UART_TxEMP;
	218	s->tb = val;
	219	mcf_uart_do_tx(s);
	220	break;
	221	case 0x10:
	222	/* ACR is ignored. */
	223	break;
	224	case 0x14:
	225	s->imr = val;
	226	break;
	227	default:
	228	break;
	229	}
	230	mcf_uart_update(s);
	231	}
	232
d9ff1d35	233	static void mcf_uart_reset(DeviceState *dev)
20dcee94	234	{
d9ff1d35 TH	235	mcf_uart_state *s = MCF_UART(dev);
d9ff1d35 TH	236
20dcee94 PB	237	s->fifo_len = 0;
	238	s->mr[0] = 0;
	239	s->mr[1] = 0;
	240	s->sr = MCF_UART_TxEMP;
	241	s->tx_enabled = 0;
	242	s->rx_enabled = 0;
	243	s->isr = 0;
	244	s->imr = 0;
	245	}
	246
	247	static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
	248	{
	249	/* Break events overwrite the last byte if the fifo is full. */
	250	if (s->fifo_len == 4)
	251	s->fifo_len--;
	252
	253	s->fifo[s->fifo_len] = data;
	254	s->fifo_len++;
	255	s->sr \|= MCF_UART_RxRDY;
	256	if (s->fifo_len == 4)
	257	s->sr \|= MCF_UART_FFULL;
	258
	259	mcf_uart_update(s);
	260	}
	261
083b266f	262	static void mcf_uart_event(void *opaque, QEMUChrEvent event)
20dcee94 PB	263	{
	264	mcf_uart_state s = (mcf_uart_state )opaque;
	265
	266	switch (event) {
	267	case CHR_EVENT_BREAK:
	268	s->isr \|= MCF_UART_DBINT;
	269	mcf_uart_push_byte(s, 0);
	270	break;
	271	default:
	272	break;
	273	}
	274	}
	275
	276	static int mcf_uart_can_receive(void *opaque)
	277	{
	278	mcf_uart_state s = (mcf_uart_state )opaque;
	279
	280	return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
	281	}
	282
	283	static void mcf_uart_receive(void opaque, const uint8_t buf, int size)
	284	{
	285	mcf_uart_state s = (mcf_uart_state )opaque;
	286
	287	mcf_uart_push_byte(s, buf[0]);
	288	}
	289
aa6e4986 BC	290	static const MemoryRegionOps mcf_uart_ops = {
	291	.read = mcf_uart_read,
	292	.write = mcf_uart_write,
	293	.endianness = DEVICE_NATIVE_ENDIAN,
20dcee94 PB	294	};
20dcee94 PB	295
d9ff1d35 TH	296	static void mcf_uart_instance_init(Object *obj)
	297	{
	298	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
	299	mcf_uart_state *s = MCF_UART(dev);
	300
	301	memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
	302	sysbus_init_mmio(dev, &s->iomem);
	303
	304	sysbus_init_irq(dev, &s->irq);
	305	}
	306
	307	static void mcf_uart_realize(DeviceState dev, Error *errp)
	308	{
	309	mcf_uart_state *s = MCF_UART(dev);
	310
	311	qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
81517ba3	312	mcf_uart_event, NULL, s, NULL, true);
d9ff1d35 TH	313	}
	314
	315	static Property mcf_uart_properties[] = {
	316	DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
	317	DEFINE_PROP_END_OF_LIST(),
	318	};
	319
	320	static void mcf_uart_class_init(ObjectClass oc, void data)
	321	{
	322	DeviceClass *dc = DEVICE_CLASS(oc);
	323
	324	dc->realize = mcf_uart_realize;
	325	dc->reset = mcf_uart_reset;
4f67d30b	326	device_class_set_props(dc, mcf_uart_properties);
d9ff1d35 TH	327	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	328	}
	329
	330	static const TypeInfo mcf_uart_info = {
	331	.name = TYPE_MCF_UART,
	332	.parent = TYPE_SYS_BUS_DEVICE,
	333	.instance_size = sizeof(mcf_uart_state),
	334	.instance_init = mcf_uart_instance_init,
	335	.class_init = mcf_uart_class_init,
	336	};
	337
	338	static void mcf_uart_register(void)
	339	{
	340	type_register_static(&mcf_uart_info);
	341	}
	342
	343	type_init(mcf_uart_register)
	344
	345	void mcf_uart_init(qemu_irq irq, Chardev chrdrv)
	346	{
	347	DeviceState *dev;
	348
3e80f690	349	dev = qdev_new(TYPE_MCF_UART);
d9ff1d35 TH	350	if (chrdrv) {
	351	qdev_prop_set_chr(dev, "chardev", chrdrv);
	352	}
3c6ef471	353	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d9ff1d35 TH	354
	355	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
	356
	357	return dev;
	358	}
	359
	360	void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
20dcee94	361	{
d9ff1d35	362	DeviceState *dev;
20dcee94	363
d9ff1d35 TH	364	dev = mcf_uart_init(irq, chrdrv);
d9ff1d35 TH	365	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
20dcee94	366	}