]>
Commit | Line | Data |
---|---|---|
80cabfad | 1 | /* |
81174dae | 2 | * QEMU 16550A UART emulation |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
81174dae | 5 | * Copyright (c) 2008 Citrix Systems, Inc. |
5fafdf24 | 6 | * |
80cabfad FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
488cb996 | 25 | |
b6a0aa05 | 26 | #include "qemu/osdep.h" |
0d09e41a | 27 | #include "hw/char/serial.h" |
64552b6b | 28 | #include "hw/irq.h" |
7566c6ef | 29 | #include "chardev/char-serial.h" |
da34e65c | 30 | #include "qapi/error.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
71e8a915 | 32 | #include "sysemu/reset.h" |
4a44d85e | 33 | #include "qemu/error-report.h" |
00609186 | 34 | #include "trace.h" |
80cabfad FB |
35 | |
36 | //#define DEBUG_SERIAL | |
37 | ||
38 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
39 | ||
40 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
41 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
42 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
43 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
44 | ||
45 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
46 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
47 | ||
48 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
49 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
50 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
51 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
81174dae AL |
52 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
53 | ||
54 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ | |
55 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ | |
80cabfad FB |
56 | |
57 | /* | |
58 | * These are the definitions for the Modem Control Register | |
59 | */ | |
60 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
61 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
62 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
63 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
64 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
65 | ||
66 | /* | |
67 | * These are the definitions for the Modem Status Register | |
68 | */ | |
69 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
70 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
71 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
72 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
73 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
74 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
75 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
76 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
77 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
78 | ||
79 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
80 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
81 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
82 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
83 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
84 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
85 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
81174dae | 86 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
80cabfad | 87 | |
81174dae AL |
88 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ |
89 | ||
90 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ | |
91 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ | |
92 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ | |
93 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ | |
94 | ||
95 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ | |
96 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ | |
97 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ | |
98 | #define UART_FCR_FE 0x01 /* FIFO Enable */ | |
99 | ||
81174dae AL |
100 | #define MAX_XMIT_RETRY 4 |
101 | ||
b6601141 MN |
102 | #ifdef DEBUG_SERIAL |
103 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 104 | do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
b6601141 MN |
105 | #else |
106 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 107 | do {} while (0) |
b6601141 MN |
108 | #endif |
109 | ||
81174dae | 110 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
b0585e7e | 111 | static void serial_xmit(SerialState *s); |
b2a5160c | 112 | |
8e8638fa | 113 | static inline void recv_fifo_put(SerialState *s, uint8_t chr) |
80cabfad | 114 | { |
71e605f8 | 115 | /* Receive overruns do not overwrite FIFO contents. */ |
8e8638fa PC |
116 | if (!fifo8_is_full(&s->recv_fifo)) { |
117 | fifo8_push(&s->recv_fifo, chr); | |
118 | } else { | |
71e605f8 | 119 | s->lsr |= UART_LSR_OE; |
8e8638fa | 120 | } |
81174dae | 121 | } |
6936bfe5 | 122 | |
81174dae AL |
123 | static void serial_update_irq(SerialState *s) |
124 | { | |
125 | uint8_t tmp_iir = UART_IIR_NO_INT; | |
126 | ||
81174dae AL |
127 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { |
128 | tmp_iir = UART_IIR_RLSI; | |
5628a626 | 129 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
c9a33054 AZ |
130 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, |
131 | * this is not in the specification but is observed on existing | |
132 | * hardware. */ | |
81174dae | 133 | tmp_iir = UART_IIR_CTI; |
2d6ee8e7 JL |
134 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
135 | (!(s->fcr & UART_FCR_FE) || | |
8e8638fa | 136 | s->recv_fifo.num >= s->recv_fifo_itl)) { |
2d6ee8e7 | 137 | tmp_iir = UART_IIR_RDI; |
81174dae AL |
138 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
139 | tmp_iir = UART_IIR_THRI; | |
140 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { | |
141 | tmp_iir = UART_IIR_MSI; | |
142 | } | |
143 | ||
144 | s->iir = tmp_iir | (s->iir & 0xF0); | |
145 | ||
146 | if (tmp_iir != UART_IIR_NO_INT) { | |
147 | qemu_irq_raise(s->irq); | |
148 | } else { | |
149 | qemu_irq_lower(s->irq); | |
6936bfe5 | 150 | } |
6936bfe5 AJ |
151 | } |
152 | ||
f8d179e3 FB |
153 | static void serial_update_parameters(SerialState *s) |
154 | { | |
01478834 CL |
155 | float speed; |
156 | int parity, data_bits, stop_bits, frame_size; | |
2122c51a | 157 | QEMUSerialSetParams ssp; |
f8d179e3 | 158 | |
718b8aec | 159 | /* Start bit. */ |
81174dae | 160 | frame_size = 1; |
f8d179e3 | 161 | if (s->lcr & 0x08) { |
718b8aec SW |
162 | /* Parity bit. */ |
163 | frame_size++; | |
f8d179e3 FB |
164 | if (s->lcr & 0x10) |
165 | parity = 'E'; | |
166 | else | |
167 | parity = 'O'; | |
168 | } else { | |
169 | parity = 'N'; | |
170 | } | |
01478834 | 171 | if (s->lcr & 0x04) { |
f8d179e3 | 172 | stop_bits = 2; |
01478834 | 173 | } else { |
f8d179e3 | 174 | stop_bits = 1; |
01478834 | 175 | } |
81174dae | 176 | |
f8d179e3 | 177 | data_bits = (s->lcr & 0x03) + 5; |
81174dae | 178 | frame_size += data_bits + stop_bits; |
01478834 CL |
179 | /* Zero divisor should give about 3500 baud */ |
180 | speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider; | |
2122c51a FB |
181 | ssp.speed = speed; |
182 | ssp.parity = parity; | |
183 | ssp.data_bits = data_bits; | |
184 | ssp.stop_bits = stop_bits; | |
73bcb24d | 185 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; |
5345fdb4 | 186 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
b6601141 | 187 | |
01478834 | 188 | DPRINTF("speed=%.2f parity=%c data=%d stop=%d\n", |
f8d179e3 | 189 | speed, parity, data_bits, stop_bits); |
f8d179e3 FB |
190 | } |
191 | ||
81174dae AL |
192 | static void serial_update_msl(SerialState *s) |
193 | { | |
194 | uint8_t omsr; | |
195 | int flags; | |
196 | ||
bc72ad67 | 197 | timer_del(s->modem_status_poll); |
81174dae | 198 | |
5345fdb4 | 199 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, |
becdfa00 | 200 | &flags) == -ENOTSUP) { |
81174dae AL |
201 | s->poll_msl = -1; |
202 | return; | |
203 | } | |
204 | ||
205 | omsr = s->msr; | |
206 | ||
207 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; | |
208 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; | |
209 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; | |
210 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; | |
211 | ||
212 | if (s->msr != omsr) { | |
213 | /* Set delta bits */ | |
214 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); | |
215 | /* UART_MSR_TERI only if change was from 1 -> 0 */ | |
216 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) | |
217 | s->msr &= ~UART_MSR_TERI; | |
218 | serial_update_irq(s); | |
219 | } | |
220 | ||
221 | /* The real 16550A apparently has a 250ns response latency to line status changes. | |
222 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ | |
223 | ||
73bcb24d RS |
224 | if (s->poll_msl) { |
225 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
226 | NANOSECONDS_PER_SECOND / 100); | |
227 | } | |
81174dae AL |
228 | } |
229 | ||
b0585e7e PB |
230 | static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond, |
231 | void *opaque) | |
81174dae AL |
232 | { |
233 | SerialState *s = opaque; | |
a1df76da | 234 | s->watch_tag = 0; |
b0585e7e PB |
235 | serial_xmit(s); |
236 | return FALSE; | |
237 | } | |
81174dae | 238 | |
b0585e7e PB |
239 | static void serial_xmit(SerialState *s) |
240 | { | |
f702e62a | 241 | do { |
0d931d70 | 242 | assert(!(s->lsr & UART_LSR_TEMT)); |
807464d8 | 243 | if (s->tsr_retry == 0) { |
0d931d70 PB |
244 | assert(!(s->lsr & UART_LSR_THRE)); |
245 | ||
f702e62a | 246 | if (s->fcr & UART_FCR_FE) { |
0d931d70 | 247 | assert(!fifo8_is_empty(&s->xmit_fifo)); |
f702e62a KB |
248 | s->tsr = fifo8_pop(&s->xmit_fifo); |
249 | if (!s->xmit_fifo.num) { | |
250 | s->lsr |= UART_LSR_THRE; | |
251 | } | |
f702e62a KB |
252 | } else { |
253 | s->tsr = s->thr; | |
81174dae | 254 | s->lsr |= UART_LSR_THRE; |
0d931d70 PB |
255 | } |
256 | if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { | |
257 | s->thr_ipending = 1; | |
258 | serial_update_irq(s); | |
7f4f0a22 | 259 | } |
81174dae | 260 | } |
81174dae | 261 | |
f702e62a KB |
262 | if (s->mcr & UART_MCR_LOOP) { |
263 | /* in loopback mode, say that we just received a char */ | |
264 | serial_receive1(s, &s->tsr, 1); | |
f3575af1 MAL |
265 | } else { |
266 | int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1); | |
267 | ||
268 | if ((rc == 0 || | |
269 | (rc == -1 && errno == EAGAIN)) && | |
270 | s->tsr_retry < MAX_XMIT_RETRY) { | |
271 | assert(s->watch_tag == 0); | |
272 | s->watch_tag = | |
273 | qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, | |
274 | serial_watch_cb, s); | |
275 | if (s->watch_tag > 0) { | |
276 | s->tsr_retry++; | |
277 | return; | |
278 | } | |
f702e62a | 279 | } |
81174dae | 280 | } |
bce933b8 | 281 | s->tsr_retry = 0; |
0d931d70 | 282 | |
f702e62a KB |
283 | /* Transmit another byte if it is already available. It is only |
284 | possible when FIFO is enabled and not empty. */ | |
0d931d70 | 285 | } while (!(s->lsr & UART_LSR_THRE)); |
81174dae | 286 | |
bc72ad67 | 287 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
0d931d70 | 288 | s->lsr |= UART_LSR_TEMT; |
81174dae AL |
289 | } |
290 | ||
7385b275 PD |
291 | /* Setter for FCR. |
292 | is_load flag means, that value is set while loading VM state | |
293 | and interrupt should not be invoked */ | |
294 | static void serial_write_fcr(SerialState *s, uint8_t val) | |
295 | { | |
296 | /* Set fcr - val only has the bits that are supposed to "stick" */ | |
297 | s->fcr = val; | |
298 | ||
299 | if (val & UART_FCR_FE) { | |
300 | s->iir |= UART_IIR_FE; | |
301 | /* Set recv_fifo trigger Level */ | |
302 | switch (val & 0xC0) { | |
303 | case UART_FCR_ITL_1: | |
304 | s->recv_fifo_itl = 1; | |
305 | break; | |
306 | case UART_FCR_ITL_2: | |
307 | s->recv_fifo_itl = 4; | |
308 | break; | |
309 | case UART_FCR_ITL_3: | |
310 | s->recv_fifo_itl = 8; | |
311 | break; | |
312 | case UART_FCR_ITL_4: | |
313 | s->recv_fifo_itl = 14; | |
314 | break; | |
315 | } | |
316 | } else { | |
317 | s->iir &= ~UART_IIR_FE; | |
318 | } | |
319 | } | |
320 | ||
75735842 AN |
321 | static void serial_update_tiocm(SerialState *s) |
322 | { | |
323 | int flags; | |
324 | ||
325 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags); | |
326 | ||
327 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); | |
328 | ||
329 | if (s->mcr & UART_MCR_RTS) { | |
330 | flags |= CHR_TIOCM_RTS; | |
331 | } | |
332 | if (s->mcr & UART_MCR_DTR) { | |
333 | flags |= CHR_TIOCM_DTR; | |
334 | } | |
335 | ||
336 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags); | |
337 | } | |
338 | ||
5ec3a23e AG |
339 | static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
340 | unsigned size) | |
80cabfad | 341 | { |
b41a2cd1 | 342 | SerialState *s = opaque; |
3b46e624 | 343 | |
80cabfad | 344 | addr &= 7; |
00609186 | 345 | trace_serial_ioport_write(addr, val); |
80cabfad FB |
346 | switch(addr) { |
347 | default: | |
348 | case 0: | |
349 | if (s->lcr & UART_LCR_DLAB) { | |
61a9346f | 350 | if (size == 1) { |
01478834 | 351 | s->divider = (s->divider & 0xff00) | val; |
61a9346f | 352 | } else { |
01478834 CL |
353 | s->divider = val; |
354 | } | |
f8d179e3 | 355 | serial_update_parameters(s); |
80cabfad | 356 | } else { |
81174dae AL |
357 | s->thr = (uint8_t) val; |
358 | if(s->fcr & UART_FCR_FE) { | |
8e8638fa PC |
359 | /* xmit overruns overwrite data, so make space if needed */ |
360 | if (fifo8_is_full(&s->xmit_fifo)) { | |
361 | fifo8_pop(&s->xmit_fifo); | |
362 | } | |
363 | fifo8_push(&s->xmit_fifo, s->thr); | |
6936bfe5 | 364 | } |
b5601df7 PC |
365 | s->thr_ipending = 0; |
366 | s->lsr &= ~UART_LSR_THRE; | |
0d931d70 | 367 | s->lsr &= ~UART_LSR_TEMT; |
b5601df7 | 368 | serial_update_irq(s); |
807464d8 | 369 | if (s->tsr_retry == 0) { |
b0585e7e | 370 | serial_xmit(s); |
f702e62a | 371 | } |
80cabfad FB |
372 | } |
373 | break; | |
374 | case 1: | |
375 | if (s->lcr & UART_LCR_DLAB) { | |
376 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
f8d179e3 | 377 | serial_update_parameters(s); |
80cabfad | 378 | } else { |
1645b8ee | 379 | uint8_t changed = (s->ier ^ val) & 0x0f; |
60e336db | 380 | s->ier = val & 0x0f; |
81174dae | 381 | /* If the backend device is a real serial port, turn polling of the modem |
1645b8ee PB |
382 | * status lines on physical port on or off depending on UART_IER_MSI state. |
383 | */ | |
384 | if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { | |
81174dae AL |
385 | if (s->ier & UART_IER_MSI) { |
386 | s->poll_msl = 1; | |
387 | serial_update_msl(s); | |
388 | } else { | |
bc72ad67 | 389 | timer_del(s->modem_status_poll); |
81174dae AL |
390 | s->poll_msl = 0; |
391 | } | |
392 | } | |
4e02b0fc PB |
393 | |
394 | /* Turning on the THRE interrupt on IER can trigger the interrupt | |
395 | * if LSR.THRE=1, even if it had been masked before by reading IIR. | |
396 | * This is not in the datasheet, but Windows relies on it. It is | |
397 | * unclear if THRE has to be resampled every time THRI becomes | |
398 | * 1, or only on the rising edge. Bochs does the latter, and Windows | |
1645b8ee PB |
399 | * always toggles IER to all zeroes and back to all ones, so do the |
400 | * same. | |
4e02b0fc PB |
401 | * |
402 | * If IER.THRI is zero, thr_ipending is not used. Set it to zero | |
403 | * so that the thr_ipending subsection is not migrated. | |
404 | */ | |
1645b8ee PB |
405 | if (changed & UART_IER_THRI) { |
406 | if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { | |
407 | s->thr_ipending = 1; | |
408 | } else { | |
409 | s->thr_ipending = 0; | |
410 | } | |
411 | } | |
412 | ||
413 | if (changed) { | |
414 | serial_update_irq(s); | |
60e336db | 415 | } |
80cabfad FB |
416 | } |
417 | break; | |
418 | case 2: | |
81174dae | 419 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ |
7385b275 | 420 | if ((val ^ s->fcr) & UART_FCR_FE) { |
81174dae | 421 | val |= UART_FCR_XFR | UART_FCR_RFR; |
7385b275 | 422 | } |
81174dae AL |
423 | |
424 | /* FIFO clear */ | |
425 | ||
426 | if (val & UART_FCR_RFR) { | |
023c3a97 | 427 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
bc72ad67 | 428 | timer_del(s->fifo_timeout_timer); |
7385b275 | 429 | s->timeout_ipending = 0; |
8e8638fa | 430 | fifo8_reset(&s->recv_fifo); |
81174dae AL |
431 | } |
432 | ||
433 | if (val & UART_FCR_XFR) { | |
023c3a97 PB |
434 | s->lsr |= UART_LSR_THRE; |
435 | s->thr_ipending = 1; | |
8e8638fa | 436 | fifo8_reset(&s->xmit_fifo); |
81174dae AL |
437 | } |
438 | ||
7385b275 | 439 | serial_write_fcr(s, val & 0xC9); |
81174dae | 440 | serial_update_irq(s); |
80cabfad FB |
441 | break; |
442 | case 3: | |
f8d179e3 FB |
443 | { |
444 | int break_enable; | |
445 | s->lcr = val; | |
446 | serial_update_parameters(s); | |
447 | break_enable = (val >> 6) & 1; | |
448 | if (break_enable != s->last_break_enable) { | |
449 | s->last_break_enable = break_enable; | |
5345fdb4 MAL |
450 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
451 | &break_enable); | |
f8d179e3 FB |
452 | } |
453 | } | |
80cabfad FB |
454 | break; |
455 | case 4: | |
81174dae | 456 | { |
81174dae AL |
457 | int old_mcr = s->mcr; |
458 | s->mcr = val & 0x1f; | |
459 | if (val & UART_MCR_LOOP) | |
460 | break; | |
461 | ||
462 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { | |
75735842 | 463 | serial_update_tiocm(s); |
81174dae AL |
464 | /* Update the modem status after a one-character-send wait-time, since there may be a response |
465 | from the device/computer at the other end of the serial line */ | |
bc72ad67 | 466 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); |
81174dae AL |
467 | } |
468 | } | |
80cabfad FB |
469 | break; |
470 | case 5: | |
471 | break; | |
472 | case 6: | |
80cabfad FB |
473 | break; |
474 | case 7: | |
475 | s->scr = val; | |
476 | break; | |
477 | } | |
478 | } | |
479 | ||
5ec3a23e | 480 | static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) |
80cabfad | 481 | { |
b41a2cd1 | 482 | SerialState *s = opaque; |
80cabfad FB |
483 | uint32_t ret; |
484 | ||
485 | addr &= 7; | |
486 | switch(addr) { | |
487 | default: | |
488 | case 0: | |
489 | if (s->lcr & UART_LCR_DLAB) { | |
5fafdf24 | 490 | ret = s->divider & 0xff; |
80cabfad | 491 | } else { |
81174dae | 492 | if(s->fcr & UART_FCR_FE) { |
b165b0d8 | 493 | ret = fifo8_is_empty(&s->recv_fifo) ? |
8e8638fa PC |
494 | 0 : fifo8_pop(&s->recv_fifo); |
495 | if (s->recv_fifo.num == 0) { | |
81174dae | 496 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
7f4f0a22 | 497 | } else { |
bc72ad67 | 498 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
7f4f0a22 | 499 | } |
81174dae AL |
500 | s->timeout_ipending = 0; |
501 | } else { | |
502 | ret = s->rbr; | |
503 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
504 | } | |
b41a2cd1 | 505 | serial_update_irq(s); |
b2a5160c AZ |
506 | if (!(s->mcr & UART_MCR_LOOP)) { |
507 | /* in loopback mode, don't receive any data */ | |
5345fdb4 | 508 | qemu_chr_fe_accept_input(&s->chr); |
b2a5160c | 509 | } |
80cabfad FB |
510 | } |
511 | break; | |
512 | case 1: | |
513 | if (s->lcr & UART_LCR_DLAB) { | |
514 | ret = (s->divider >> 8) & 0xff; | |
515 | } else { | |
516 | ret = s->ier; | |
517 | } | |
518 | break; | |
519 | case 2: | |
520 | ret = s->iir; | |
cdee7bdf | 521 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { |
80cabfad | 522 | s->thr_ipending = 0; |
71e605f8 JG |
523 | serial_update_irq(s); |
524 | } | |
80cabfad FB |
525 | break; |
526 | case 3: | |
527 | ret = s->lcr; | |
528 | break; | |
529 | case 4: | |
530 | ret = s->mcr; | |
531 | break; | |
532 | case 5: | |
533 | ret = s->lsr; | |
71e605f8 JG |
534 | /* Clear break and overrun interrupts */ |
535 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { | |
536 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); | |
81174dae AL |
537 | serial_update_irq(s); |
538 | } | |
80cabfad FB |
539 | break; |
540 | case 6: | |
541 | if (s->mcr & UART_MCR_LOOP) { | |
542 | /* in loopback, the modem output pins are connected to the | |
543 | inputs */ | |
544 | ret = (s->mcr & 0x0c) << 4; | |
545 | ret |= (s->mcr & 0x02) << 3; | |
546 | ret |= (s->mcr & 0x01) << 5; | |
547 | } else { | |
81174dae AL |
548 | if (s->poll_msl >= 0) |
549 | serial_update_msl(s); | |
80cabfad | 550 | ret = s->msr; |
81174dae AL |
551 | /* Clear delta bits & msr int after read, if they were set */ |
552 | if (s->msr & UART_MSR_ANY_DELTA) { | |
553 | s->msr &= 0xF0; | |
554 | serial_update_irq(s); | |
555 | } | |
80cabfad FB |
556 | } |
557 | break; | |
558 | case 7: | |
559 | ret = s->scr; | |
560 | break; | |
561 | } | |
00609186 | 562 | trace_serial_ioport_read(addr, ret); |
80cabfad FB |
563 | return ret; |
564 | } | |
565 | ||
82c643ff | 566 | static int serial_can_receive(SerialState *s) |
80cabfad | 567 | { |
81174dae | 568 | if(s->fcr & UART_FCR_FE) { |
8e8638fa | 569 | if (s->recv_fifo.num < UART_FIFO_LENGTH) { |
7f4f0a22 PC |
570 | /* |
571 | * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 | |
572 | * if above. If UART_FIFO_LENGTH - fifo.count is advertised the | |
573 | * effect will be to almost always fill the fifo completely before | |
574 | * the guest has a chance to respond, effectively overriding the ITL | |
575 | * that the guest has set. | |
576 | */ | |
8e8638fa PC |
577 | return (s->recv_fifo.num <= s->recv_fifo_itl) ? |
578 | s->recv_fifo_itl - s->recv_fifo.num : 1; | |
7f4f0a22 PC |
579 | } else { |
580 | return 0; | |
581 | } | |
81174dae | 582 | } else { |
7f4f0a22 | 583 | return !(s->lsr & UART_LSR_DR); |
81174dae | 584 | } |
80cabfad FB |
585 | } |
586 | ||
82c643ff | 587 | static void serial_receive_break(SerialState *s) |
80cabfad | 588 | { |
80cabfad | 589 | s->rbr = 0; |
40ff1624 | 590 | /* When the LSR_DR is set a null byte is pushed into the fifo */ |
8e8638fa | 591 | recv_fifo_put(s, '\0'); |
80cabfad | 592 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
b41a2cd1 | 593 | serial_update_irq(s); |
80cabfad FB |
594 | } |
595 | ||
81174dae AL |
596 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ |
597 | static void fifo_timeout_int (void *opaque) { | |
598 | SerialState *s = opaque; | |
8e8638fa | 599 | if (s->recv_fifo.num) { |
81174dae AL |
600 | s->timeout_ipending = 1; |
601 | serial_update_irq(s); | |
602 | } | |
603 | } | |
604 | ||
b41a2cd1 | 605 | static int serial_can_receive1(void *opaque) |
80cabfad | 606 | { |
b41a2cd1 FB |
607 | SerialState *s = opaque; |
608 | return serial_can_receive(s); | |
609 | } | |
610 | ||
611 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
612 | { | |
613 | SerialState *s = opaque; | |
9826fd59 GH |
614 | |
615 | if (s->wakeup) { | |
fb064112 | 616 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER, NULL); |
9826fd59 | 617 | } |
81174dae AL |
618 | if(s->fcr & UART_FCR_FE) { |
619 | int i; | |
620 | for (i = 0; i < size; i++) { | |
8e8638fa | 621 | recv_fifo_put(s, buf[i]); |
81174dae AL |
622 | } |
623 | s->lsr |= UART_LSR_DR; | |
624 | /* call the timeout receive callback in 4 char transmit time */ | |
bc72ad67 | 625 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
81174dae | 626 | } else { |
71e605f8 JG |
627 | if (s->lsr & UART_LSR_DR) |
628 | s->lsr |= UART_LSR_OE; | |
81174dae AL |
629 | s->rbr = buf[0]; |
630 | s->lsr |= UART_LSR_DR; | |
631 | } | |
632 | serial_update_irq(s); | |
b41a2cd1 | 633 | } |
80cabfad | 634 | |
82c643ff FB |
635 | static void serial_event(void *opaque, int event) |
636 | { | |
637 | SerialState *s = opaque; | |
b6601141 | 638 | DPRINTF("event %x\n", event); |
82c643ff FB |
639 | if (event == CHR_EVENT_BREAK) |
640 | serial_receive_break(s); | |
641 | } | |
642 | ||
44b1ff31 | 643 | static int serial_pre_save(void *opaque) |
8738a8d0 | 644 | { |
d4bfa4d7 | 645 | SerialState *s = opaque; |
747791f1 | 646 | s->fcr_vmstate = s->fcr; |
44b1ff31 DDAG |
647 | |
648 | return 0; | |
8738a8d0 FB |
649 | } |
650 | ||
7385b275 PD |
651 | static int serial_pre_load(void *opaque) |
652 | { | |
653 | SerialState *s = opaque; | |
654 | s->thr_ipending = -1; | |
655 | s->poll_msl = -1; | |
656 | return 0; | |
657 | } | |
658 | ||
e59fb374 | 659 | static int serial_post_load(void *opaque, int version_id) |
747791f1 JQ |
660 | { |
661 | SerialState *s = opaque; | |
81174dae | 662 | |
4c18ce94 JQ |
663 | if (version_id < 3) { |
664 | s->fcr_vmstate = 0; | |
665 | } | |
7385b275 PD |
666 | if (s->thr_ipending == -1) { |
667 | s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
668 | } | |
9f34a35e PB |
669 | |
670 | if (s->tsr_retry > 0) { | |
671 | /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */ | |
672 | if (s->lsr & UART_LSR_TEMT) { | |
673 | error_report("inconsistent state in serial device " | |
674 | "(tsr empty, tsr_retry=%d", s->tsr_retry); | |
675 | return -1; | |
676 | } | |
677 | ||
678 | if (s->tsr_retry > MAX_XMIT_RETRY) { | |
679 | s->tsr_retry = MAX_XMIT_RETRY; | |
680 | } | |
681 | ||
682 | assert(s->watch_tag == 0); | |
5345fdb4 | 683 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
9f34a35e PB |
684 | serial_watch_cb, s); |
685 | } else { | |
686 | /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */ | |
687 | if (!(s->lsr & UART_LSR_TEMT)) { | |
688 | error_report("inconsistent state in serial device " | |
689 | "(tsr not empty, tsr_retry=0"); | |
690 | return -1; | |
691 | } | |
807464d8 PB |
692 | } |
693 | ||
7385b275 | 694 | s->last_break_enable = (s->lcr >> 6) & 1; |
81174dae | 695 | /* Initialize fcr via setter to perform essential side-effects */ |
7385b275 | 696 | serial_write_fcr(s, s->fcr_vmstate); |
9a7c4878 | 697 | serial_update_parameters(s); |
8738a8d0 FB |
698 | return 0; |
699 | } | |
700 | ||
7385b275 PD |
701 | static bool serial_thr_ipending_needed(void *opaque) |
702 | { | |
703 | SerialState *s = opaque; | |
bfa73628 PB |
704 | |
705 | if (s->ier & UART_IER_THRI) { | |
706 | bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
707 | return s->thr_ipending != expected_value; | |
708 | } else { | |
709 | /* LSR.THRE will be sampled again when the interrupt is | |
710 | * enabled. thr_ipending is not used in this case, do | |
711 | * not migrate it. | |
712 | */ | |
713 | return false; | |
714 | } | |
7385b275 PD |
715 | } |
716 | ||
92013cf8 | 717 | static const VMStateDescription vmstate_serial_thr_ipending = { |
7385b275 PD |
718 | .name = "serial/thr_ipending", |
719 | .version_id = 1, | |
720 | .minimum_version_id = 1, | |
5cd8cada | 721 | .needed = serial_thr_ipending_needed, |
7385b275 PD |
722 | .fields = (VMStateField[]) { |
723 | VMSTATE_INT32(thr_ipending, SerialState), | |
724 | VMSTATE_END_OF_LIST() | |
725 | } | |
726 | }; | |
727 | ||
728 | static bool serial_tsr_needed(void *opaque) | |
729 | { | |
730 | SerialState *s = (SerialState *)opaque; | |
731 | return s->tsr_retry != 0; | |
732 | } | |
733 | ||
92013cf8 | 734 | static const VMStateDescription vmstate_serial_tsr = { |
7385b275 PD |
735 | .name = "serial/tsr", |
736 | .version_id = 1, | |
737 | .minimum_version_id = 1, | |
5cd8cada | 738 | .needed = serial_tsr_needed, |
7385b275 | 739 | .fields = (VMStateField[]) { |
807464d8 | 740 | VMSTATE_UINT32(tsr_retry, SerialState), |
7385b275 PD |
741 | VMSTATE_UINT8(thr, SerialState), |
742 | VMSTATE_UINT8(tsr, SerialState), | |
743 | VMSTATE_END_OF_LIST() | |
744 | } | |
745 | }; | |
746 | ||
747 | static bool serial_recv_fifo_needed(void *opaque) | |
748 | { | |
749 | SerialState *s = (SerialState *)opaque; | |
750 | return !fifo8_is_empty(&s->recv_fifo); | |
751 | ||
752 | } | |
753 | ||
92013cf8 | 754 | static const VMStateDescription vmstate_serial_recv_fifo = { |
7385b275 PD |
755 | .name = "serial/recv_fifo", |
756 | .version_id = 1, | |
757 | .minimum_version_id = 1, | |
5cd8cada | 758 | .needed = serial_recv_fifo_needed, |
7385b275 PD |
759 | .fields = (VMStateField[]) { |
760 | VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
761 | VMSTATE_END_OF_LIST() | |
762 | } | |
763 | }; | |
764 | ||
765 | static bool serial_xmit_fifo_needed(void *opaque) | |
766 | { | |
767 | SerialState *s = (SerialState *)opaque; | |
768 | return !fifo8_is_empty(&s->xmit_fifo); | |
769 | } | |
770 | ||
92013cf8 | 771 | static const VMStateDescription vmstate_serial_xmit_fifo = { |
7385b275 PD |
772 | .name = "serial/xmit_fifo", |
773 | .version_id = 1, | |
774 | .minimum_version_id = 1, | |
5cd8cada | 775 | .needed = serial_xmit_fifo_needed, |
7385b275 PD |
776 | .fields = (VMStateField[]) { |
777 | VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
778 | VMSTATE_END_OF_LIST() | |
779 | } | |
780 | }; | |
781 | ||
782 | static bool serial_fifo_timeout_timer_needed(void *opaque) | |
783 | { | |
784 | SerialState *s = (SerialState *)opaque; | |
785 | return timer_pending(s->fifo_timeout_timer); | |
786 | } | |
787 | ||
92013cf8 | 788 | static const VMStateDescription vmstate_serial_fifo_timeout_timer = { |
7385b275 PD |
789 | .name = "serial/fifo_timeout_timer", |
790 | .version_id = 1, | |
791 | .minimum_version_id = 1, | |
5cd8cada | 792 | .needed = serial_fifo_timeout_timer_needed, |
7385b275 | 793 | .fields = (VMStateField[]) { |
e720677e | 794 | VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState), |
7385b275 PD |
795 | VMSTATE_END_OF_LIST() |
796 | } | |
797 | }; | |
798 | ||
799 | static bool serial_timeout_ipending_needed(void *opaque) | |
800 | { | |
801 | SerialState *s = (SerialState *)opaque; | |
802 | return s->timeout_ipending != 0; | |
803 | } | |
804 | ||
92013cf8 | 805 | static const VMStateDescription vmstate_serial_timeout_ipending = { |
7385b275 PD |
806 | .name = "serial/timeout_ipending", |
807 | .version_id = 1, | |
808 | .minimum_version_id = 1, | |
5cd8cada | 809 | .needed = serial_timeout_ipending_needed, |
7385b275 PD |
810 | .fields = (VMStateField[]) { |
811 | VMSTATE_INT32(timeout_ipending, SerialState), | |
812 | VMSTATE_END_OF_LIST() | |
813 | } | |
814 | }; | |
815 | ||
816 | static bool serial_poll_needed(void *opaque) | |
817 | { | |
818 | SerialState *s = (SerialState *)opaque; | |
819 | return s->poll_msl >= 0; | |
820 | } | |
821 | ||
92013cf8 | 822 | static const VMStateDescription vmstate_serial_poll = { |
7385b275 PD |
823 | .name = "serial/poll", |
824 | .version_id = 1, | |
5cd8cada | 825 | .needed = serial_poll_needed, |
7385b275 PD |
826 | .minimum_version_id = 1, |
827 | .fields = (VMStateField[]) { | |
828 | VMSTATE_INT32(poll_msl, SerialState), | |
e720677e | 829 | VMSTATE_TIMER_PTR(modem_status_poll, SerialState), |
7385b275 PD |
830 | VMSTATE_END_OF_LIST() |
831 | } | |
832 | }; | |
833 | ||
488cb996 | 834 | const VMStateDescription vmstate_serial = { |
747791f1 JQ |
835 | .name = "serial", |
836 | .version_id = 3, | |
837 | .minimum_version_id = 2, | |
838 | .pre_save = serial_pre_save, | |
7385b275 | 839 | .pre_load = serial_pre_load, |
747791f1 | 840 | .post_load = serial_post_load, |
d49805ae | 841 | .fields = (VMStateField[]) { |
747791f1 JQ |
842 | VMSTATE_UINT16_V(divider, SerialState, 2), |
843 | VMSTATE_UINT8(rbr, SerialState), | |
844 | VMSTATE_UINT8(ier, SerialState), | |
845 | VMSTATE_UINT8(iir, SerialState), | |
846 | VMSTATE_UINT8(lcr, SerialState), | |
847 | VMSTATE_UINT8(mcr, SerialState), | |
848 | VMSTATE_UINT8(lsr, SerialState), | |
849 | VMSTATE_UINT8(msr, SerialState), | |
850 | VMSTATE_UINT8(scr, SerialState), | |
851 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), | |
852 | VMSTATE_END_OF_LIST() | |
7385b275 | 853 | }, |
5cd8cada JQ |
854 | .subsections = (const VMStateDescription*[]) { |
855 | &vmstate_serial_thr_ipending, | |
856 | &vmstate_serial_tsr, | |
857 | &vmstate_serial_recv_fifo, | |
858 | &vmstate_serial_xmit_fifo, | |
859 | &vmstate_serial_fifo_timeout_timer, | |
860 | &vmstate_serial_timeout_ipending, | |
861 | &vmstate_serial_poll, | |
862 | NULL | |
747791f1 JQ |
863 | } |
864 | }; | |
865 | ||
b2a5160c AZ |
866 | static void serial_reset(void *opaque) |
867 | { | |
868 | SerialState *s = opaque; | |
869 | ||
a1df76da PB |
870 | if (s->watch_tag > 0) { |
871 | g_source_remove(s->watch_tag); | |
872 | s->watch_tag = 0; | |
873 | } | |
874 | ||
b2a5160c AZ |
875 | s->rbr = 0; |
876 | s->ier = 0; | |
877 | s->iir = UART_IIR_NO_INT; | |
878 | s->lcr = 0; | |
b2a5160c AZ |
879 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
880 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; | |
718b8aec | 881 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ |
81174dae AL |
882 | s->divider = 0x0C; |
883 | s->mcr = UART_MCR_OUT2; | |
b2a5160c | 884 | s->scr = 0; |
81174dae | 885 | s->tsr_retry = 0; |
73bcb24d | 886 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10; |
81174dae AL |
887 | s->poll_msl = 0; |
888 | ||
7385b275 PD |
889 | s->timeout_ipending = 0; |
890 | timer_del(s->fifo_timeout_timer); | |
891 | timer_del(s->modem_status_poll); | |
892 | ||
8e8638fa PC |
893 | fifo8_reset(&s->recv_fifo); |
894 | fifo8_reset(&s->xmit_fifo); | |
81174dae | 895 | |
bc72ad67 | 896 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
b2a5160c AZ |
897 | |
898 | s->thr_ipending = 0; | |
899 | s->last_break_enable = 0; | |
900 | qemu_irq_lower(s->irq); | |
a30cf876 PB |
901 | |
902 | serial_update_msl(s); | |
903 | s->msr &= ~UART_MSR_ANY_DELTA; | |
b2a5160c AZ |
904 | } |
905 | ||
1a29cc8f AN |
906 | static int serial_be_change(void *opaque) |
907 | { | |
908 | SerialState *s = opaque; | |
909 | ||
910 | qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, | |
911 | serial_event, serial_be_change, s, NULL, true); | |
912 | ||
913 | serial_update_parameters(s); | |
914 | ||
915 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, | |
916 | &s->last_break_enable); | |
917 | ||
918 | s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0; | |
919 | serial_update_msl(s); | |
920 | ||
921 | if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) { | |
922 | serial_update_tiocm(s); | |
923 | } | |
924 | ||
925 | if (s->watch_tag > 0) { | |
926 | g_source_remove(s->watch_tag); | |
927 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, | |
928 | serial_watch_cb, s); | |
929 | } | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
db895a1e | 934 | void serial_realize_core(SerialState *s, Error **errp) |
81174dae | 935 | { |
bc72ad67 | 936 | s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); |
81174dae | 937 | |
bc72ad67 | 938 | s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); |
a08d4367 | 939 | qemu_register_reset(serial_reset, s); |
81174dae | 940 | |
5345fdb4 | 941 | qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, |
1a29cc8f | 942 | serial_event, serial_be_change, s, NULL, true); |
8e8638fa PC |
943 | fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); |
944 | fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); | |
4df7961f | 945 | serial_reset(s); |
81174dae AL |
946 | } |
947 | ||
419ad672 GH |
948 | void serial_exit_core(SerialState *s) |
949 | { | |
1ce2610c | 950 | qemu_chr_fe_deinit(&s->chr, false); |
8409dc88 LQ |
951 | |
952 | timer_del(s->modem_status_poll); | |
953 | timer_free(s->modem_status_poll); | |
954 | ||
955 | timer_del(s->fifo_timeout_timer); | |
956 | timer_free(s->fifo_timeout_timer); | |
957 | ||
958 | fifo8_destroy(&s->recv_fifo); | |
959 | fifo8_destroy(&s->xmit_fifo); | |
960 | ||
419ad672 GH |
961 | qemu_unregister_reset(serial_reset, s); |
962 | } | |
963 | ||
038eaf82 SW |
964 | /* Change the main reference oscillator frequency. */ |
965 | void serial_set_frequency(SerialState *s, uint32_t frequency) | |
966 | { | |
967 | s->baudbase = frequency; | |
968 | serial_update_parameters(s); | |
969 | } | |
970 | ||
488cb996 | 971 | const MemoryRegionOps serial_io_ops = { |
5ec3a23e AG |
972 | .read = serial_ioport_read, |
973 | .write = serial_ioport_write, | |
974 | .impl = { | |
975 | .min_access_size = 1, | |
976 | .max_access_size = 1, | |
977 | }, | |
978 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a941ae45 RH |
979 | }; |
980 | ||
b6cd0ea1 | 981 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
0ec7b3e7 | 982 | Chardev *chr, MemoryRegion *system_io) |
b41a2cd1 FB |
983 | { |
984 | SerialState *s; | |
985 | ||
7267c094 | 986 | s = g_malloc0(sizeof(SerialState)); |
6936bfe5 | 987 | |
ac0be998 GH |
988 | s->irq = irq; |
989 | s->baudbase = baudbase; | |
becdfa00 | 990 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
007b0657 | 991 | serial_realize_core(s, &error_fatal); |
b41a2cd1 | 992 | |
0be71e32 | 993 | vmstate_register(NULL, base, &vmstate_serial, s); |
8738a8d0 | 994 | |
2c9b15ca | 995 | memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); |
568fd159 | 996 | memory_region_add_subregion(system_io, base, &s->io); |
5ec3a23e | 997 | |
b41a2cd1 | 998 | return s; |
80cabfad | 999 | } |
e5d13e2f FB |
1000 | |
1001 | /* Memory mapped interface */ | |
a8170e5e | 1002 | static uint64_t serial_mm_read(void *opaque, hwaddr addr, |
8e8ffc44 | 1003 | unsigned size) |
e5d13e2f FB |
1004 | { |
1005 | SerialState *s = opaque; | |
5ec3a23e | 1006 | return serial_ioport_read(s, addr >> s->it_shift, 1); |
e5d13e2f FB |
1007 | } |
1008 | ||
a8170e5e | 1009 | static void serial_mm_write(void *opaque, hwaddr addr, |
8e8ffc44 | 1010 | uint64_t value, unsigned size) |
2d48377a BS |
1011 | { |
1012 | SerialState *s = opaque; | |
e5a11847 | 1013 | value &= 255; |
5ec3a23e | 1014 | serial_ioport_write(s, addr >> s->it_shift, value, 1); |
2d48377a BS |
1015 | } |
1016 | ||
8e8ffc44 RH |
1017 | static const MemoryRegionOps serial_mm_ops[3] = { |
1018 | [DEVICE_NATIVE_ENDIAN] = { | |
1019 | .read = serial_mm_read, | |
1020 | .write = serial_mm_write, | |
1021 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e5a11847 MN |
1022 | .valid.max_access_size = 8, |
1023 | .impl.max_access_size = 8, | |
8e8ffc44 RH |
1024 | }, |
1025 | [DEVICE_LITTLE_ENDIAN] = { | |
1026 | .read = serial_mm_read, | |
1027 | .write = serial_mm_write, | |
1028 | .endianness = DEVICE_LITTLE_ENDIAN, | |
e5a11847 MN |
1029 | .valid.max_access_size = 8, |
1030 | .impl.max_access_size = 8, | |
8e8ffc44 RH |
1031 | }, |
1032 | [DEVICE_BIG_ENDIAN] = { | |
1033 | .read = serial_mm_read, | |
1034 | .write = serial_mm_write, | |
1035 | .endianness = DEVICE_BIG_ENDIAN, | |
e5a11847 MN |
1036 | .valid.max_access_size = 8, |
1037 | .impl.max_access_size = 8, | |
8e8ffc44 | 1038 | }, |
e5d13e2f FB |
1039 | }; |
1040 | ||
39186d8a | 1041 | SerialState *serial_mm_init(MemoryRegion *address_space, |
a8170e5e | 1042 | hwaddr base, int it_shift, |
39186d8a | 1043 | qemu_irq irq, int baudbase, |
0ec7b3e7 | 1044 | Chardev *chr, enum device_endian end) |
e5d13e2f FB |
1045 | { |
1046 | SerialState *s; | |
e5d13e2f | 1047 | |
7267c094 | 1048 | s = g_malloc0(sizeof(SerialState)); |
81174dae | 1049 | |
e5d13e2f | 1050 | s->it_shift = it_shift; |
ac0be998 GH |
1051 | s->irq = irq; |
1052 | s->baudbase = baudbase; | |
becdfa00 | 1053 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
e5d13e2f | 1054 | |
007b0657 | 1055 | serial_realize_core(s, &error_fatal); |
0be71e32 | 1056 | vmstate_register(NULL, base, &vmstate_serial, s); |
e5d13e2f | 1057 | |
2c9b15ca | 1058 | memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, |
8e8ffc44 | 1059 | "serial", 8 << it_shift); |
39186d8a | 1060 | memory_region_add_subregion(address_space, base, &s->io); |
e5d13e2f FB |
1061 | return s; |
1062 | } |