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Commit | Line | Data |
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5fafdf24 | 1 | /* |
bdd5003a PB |
2 | * Arm PrimeCell PL110 Color LCD Controller |
3 | * | |
2e9bdce5 | 4 | * Copyright (c) 2005-2009 CodeSourcery. |
bdd5003a PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GNU LGPL |
bdd5003a PB |
8 | */ |
9 | ||
8ef94f0b | 10 | #include "qemu/osdep.h" |
64552b6b | 11 | #include "hw/irq.h" |
83c9f4ca | 12 | #include "hw/sysbus.h" |
d6454270 | 13 | #include "migration/vmstate.h" |
28ecbaee | 14 | #include "ui/console.h" |
47b43a1f | 15 | #include "framebuffer.h" |
28ecbaee | 16 | #include "ui/pixel_ops.h" |
24da047a | 17 | #include "qemu/timer.h" |
03dd024f | 18 | #include "qemu/log.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
db1015e9 | 20 | #include "qom/object.h" |
bdd5003a PB |
21 | |
22 | #define PL110_CR_EN 0x001 | |
e9c05b42 | 23 | #define PL110_CR_BGR 0x100 |
bdd5003a PB |
24 | #define PL110_CR_BEBO 0x200 |
25 | #define PL110_CR_BEPO 0x400 | |
26 | #define PL110_CR_PWR 0x800 | |
24da047a LW |
27 | #define PL110_IE_NB 0x004 |
28 | #define PL110_IE_VC 0x008 | |
bdd5003a PB |
29 | |
30 | enum pl110_bppmode | |
31 | { | |
32 | BPP_1, | |
33 | BPP_2, | |
34 | BPP_4, | |
35 | BPP_8, | |
36 | BPP_16, | |
4fbf5556 PM |
37 | BPP_32, |
38 | BPP_16_565, /* PL111 only */ | |
39 | BPP_12 /* PL111 only */ | |
40 | }; | |
41 | ||
42 | ||
43 | /* The Versatile/PB uses a slightly modified PL110 controller. */ | |
44 | enum pl110_version | |
45 | { | |
c7bf3492 EH |
46 | VERSION_PL110, |
47 | VERSION_PL110_VERSATILE, | |
48 | VERSION_PL111 | |
bdd5003a PB |
49 | }; |
50 | ||
5d7a11e4 | 51 | #define TYPE_PL110 "pl110" |
8063396b | 52 | OBJECT_DECLARE_SIMPLE_TYPE(PL110State, PL110) |
5d7a11e4 | 53 | |
db1015e9 | 54 | struct PL110State { |
5d7a11e4 AF |
55 | SysBusDevice parent_obj; |
56 | ||
1a6b31ce | 57 | MemoryRegion iomem; |
c1076c3e | 58 | MemoryRegionSection fbsection; |
c78f7137 | 59 | QemuConsole *con; |
24da047a | 60 | QEMUTimer *vblank_timer; |
c60e08d9 | 61 | |
4fbf5556 | 62 | int version; |
bdd5003a PB |
63 | uint32_t timing[4]; |
64 | uint32_t cr; | |
65 | uint32_t upbase; | |
66 | uint32_t lpbase; | |
67 | uint32_t int_status; | |
68 | uint32_t int_mask; | |
69 | int cols; | |
70 | int rows; | |
71 | enum pl110_bppmode bpp; | |
72 | int invalidate; | |
242ea2c6 | 73 | uint32_t mux_ctrl; |
6e4c0d1f PM |
74 | uint32_t palette[256]; |
75 | uint32_t raw_palette[128]; | |
d537cf6c | 76 | qemu_irq irq; |
db1015e9 | 77 | }; |
bdd5003a | 78 | |
128939a9 PM |
79 | static int vmstate_pl110_post_load(void *opaque, int version_id); |
80 | ||
8c60d065 PM |
81 | static const VMStateDescription vmstate_pl110 = { |
82 | .name = "pl110", | |
242ea2c6 | 83 | .version_id = 2, |
8c60d065 | 84 | .minimum_version_id = 1, |
128939a9 | 85 | .post_load = vmstate_pl110_post_load, |
8c60d065 | 86 | .fields = (VMStateField[]) { |
513960ea AF |
87 | VMSTATE_INT32(version, PL110State), |
88 | VMSTATE_UINT32_ARRAY(timing, PL110State, 4), | |
89 | VMSTATE_UINT32(cr, PL110State), | |
90 | VMSTATE_UINT32(upbase, PL110State), | |
91 | VMSTATE_UINT32(lpbase, PL110State), | |
92 | VMSTATE_UINT32(int_status, PL110State), | |
93 | VMSTATE_UINT32(int_mask, PL110State), | |
94 | VMSTATE_INT32(cols, PL110State), | |
95 | VMSTATE_INT32(rows, PL110State), | |
96 | VMSTATE_UINT32(bpp, PL110State), | |
97 | VMSTATE_INT32(invalidate, PL110State), | |
98 | VMSTATE_UINT32_ARRAY(palette, PL110State, 256), | |
99 | VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128), | |
100 | VMSTATE_UINT32_V(mux_ctrl, PL110State, 2), | |
8c60d065 PM |
101 | VMSTATE_END_OF_LIST() |
102 | } | |
103 | }; | |
104 | ||
bdd5003a PB |
105 | static const unsigned char pl110_id[] = |
106 | { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; | |
107 | ||
4fbf5556 PM |
108 | static const unsigned char pl111_id[] = { |
109 | 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1 | |
110 | }; | |
111 | ||
031c44e4 | 112 | |
4fbf5556 PM |
113 | /* Indexed by pl110_version */ |
114 | static const unsigned char *idregs[] = { | |
115 | pl110_id, | |
031c44e4 PM |
116 | /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board |
117 | * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware | |
118 | * itself has the same ID values as a stock PL110, and guests (in | |
119 | * particular Linux) rely on this. We emulate what the hardware does, | |
120 | * rather than what the docs claim it ought to do. | |
121 | */ | |
122 | pl110_id, | |
4fbf5556 PM |
123 | pl111_id |
124 | }; | |
125 | ||
bdd5003a | 126 | #define BITS 8 |
47b43a1f | 127 | #include "pl110_template.h" |
bdd5003a | 128 | #define BITS 15 |
47b43a1f | 129 | #include "pl110_template.h" |
bdd5003a | 130 | #define BITS 16 |
47b43a1f | 131 | #include "pl110_template.h" |
bdd5003a | 132 | #define BITS 24 |
47b43a1f | 133 | #include "pl110_template.h" |
bdd5003a | 134 | #define BITS 32 |
47b43a1f | 135 | #include "pl110_template.h" |
bdd5003a | 136 | |
513960ea | 137 | static int pl110_enabled(PL110State *s) |
bdd5003a PB |
138 | { |
139 | return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); | |
140 | } | |
141 | ||
95219897 | 142 | static void pl110_update_display(void *opaque) |
bdd5003a | 143 | { |
513960ea | 144 | PL110State *s = (PL110State *)opaque; |
5d7a11e4 | 145 | SysBusDevice *sbd; |
c78f7137 | 146 | DisplaySurface *surface = qemu_console_surface(s->con); |
bdd5003a PB |
147 | drawfn* fntable; |
148 | drawfn fn; | |
bdd5003a PB |
149 | int dest_width; |
150 | int src_width; | |
e9c05b42 | 151 | int bpp_offset; |
714fa308 PB |
152 | int first; |
153 | int last; | |
bdd5003a | 154 | |
5d7a11e4 | 155 | if (!pl110_enabled(s)) { |
bdd5003a | 156 | return; |
5d7a11e4 AF |
157 | } |
158 | ||
159 | sbd = SYS_BUS_DEVICE(s); | |
3b46e624 | 160 | |
c78f7137 | 161 | switch (surface_bits_per_pixel(surface)) { |
af2f6733 PB |
162 | case 0: |
163 | return; | |
bdd5003a PB |
164 | case 8: |
165 | fntable = pl110_draw_fn_8; | |
166 | dest_width = 1; | |
167 | break; | |
168 | case 15: | |
169 | fntable = pl110_draw_fn_15; | |
170 | dest_width = 2; | |
171 | break; | |
172 | case 16: | |
173 | fntable = pl110_draw_fn_16; | |
174 | dest_width = 2; | |
175 | break; | |
176 | case 24: | |
177 | fntable = pl110_draw_fn_24; | |
178 | dest_width = 3; | |
179 | break; | |
180 | case 32: | |
181 | fntable = pl110_draw_fn_32; | |
182 | dest_width = 4; | |
183 | break; | |
184 | default: | |
af2f6733 | 185 | fprintf(stderr, "pl110: Bad color depth\n"); |
bdd5003a PB |
186 | exit(1); |
187 | } | |
e9c05b42 AZ |
188 | if (s->cr & PL110_CR_BGR) |
189 | bpp_offset = 0; | |
190 | else | |
4fbf5556 PM |
191 | bpp_offset = 24; |
192 | ||
c7bf3492 | 193 | if ((s->version != VERSION_PL111) && (s->bpp == BPP_16)) { |
4fbf5556 PM |
194 | /* The PL110's native 16 bit mode is 5551; however |
195 | * most boards with a PL110 implement an external | |
196 | * mux which allows bits to be reshuffled to give | |
197 | * 565 format. The mux is typically controlled by | |
198 | * an external system register. | |
242ea2c6 | 199 | * This is controlled by a GPIO input pin |
4fbf5556 | 200 | * so boards can wire it up to their register. |
4fbf5556 PM |
201 | * |
202 | * The PL111 straightforwardly implements both | |
203 | * 5551 and 565 under control of the bpp field | |
204 | * in the LCDControl register. | |
205 | */ | |
242ea2c6 PM |
206 | switch (s->mux_ctrl) { |
207 | case 3: /* 565 BGR */ | |
208 | bpp_offset = (BPP_16_565 - BPP_16); | |
209 | break; | |
210 | case 1: /* 5551 */ | |
211 | break; | |
212 | case 0: /* 888; also if we have loaded vmstate from an old version */ | |
213 | case 2: /* 565 RGB */ | |
214 | default: | |
215 | /* treat as 565 but honour BGR bit */ | |
216 | bpp_offset += (BPP_16_565 - BPP_16); | |
217 | break; | |
218 | } | |
4fbf5556 | 219 | } |
e9c05b42 | 220 | |
bdd5003a | 221 | if (s->cr & PL110_CR_BEBO) |
4fbf5556 | 222 | fn = fntable[s->bpp + 8 + bpp_offset]; |
bdd5003a | 223 | else if (s->cr & PL110_CR_BEPO) |
4fbf5556 | 224 | fn = fntable[s->bpp + 16 + bpp_offset]; |
bdd5003a | 225 | else |
e9c05b42 | 226 | fn = fntable[s->bpp + bpp_offset]; |
3b46e624 | 227 | |
bdd5003a PB |
228 | src_width = s->cols; |
229 | switch (s->bpp) { | |
230 | case BPP_1: | |
231 | src_width >>= 3; | |
232 | break; | |
233 | case BPP_2: | |
234 | src_width >>= 2; | |
235 | break; | |
236 | case BPP_4: | |
237 | src_width >>= 1; | |
238 | break; | |
239 | case BPP_8: | |
240 | break; | |
241 | case BPP_16: | |
4fbf5556 PM |
242 | case BPP_16_565: |
243 | case BPP_12: | |
bdd5003a PB |
244 | src_width <<= 1; |
245 | break; | |
246 | case BPP_32: | |
247 | src_width <<= 2; | |
248 | break; | |
249 | } | |
250 | dest_width *= s->cols; | |
714fa308 | 251 | first = 0; |
c1076c3e PB |
252 | if (s->invalidate) { |
253 | framebuffer_update_memory_section(&s->fbsection, | |
254 | sysbus_address_space(sbd), | |
255 | s->upbase, | |
256 | s->rows, src_width); | |
257 | } | |
258 | ||
259 | framebuffer_update_display(surface, &s->fbsection, | |
260 | s->cols, s->rows, | |
714fa308 PB |
261 | src_width, dest_width, 0, |
262 | s->invalidate, | |
6e4c0d1f | 263 | fn, s->palette, |
714fa308 | 264 | &first, &last); |
c1076c3e | 265 | |
714fa308 | 266 | if (first >= 0) { |
c78f7137 | 267 | dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); |
bdd5003a | 268 | } |
bdd5003a | 269 | s->invalidate = 0; |
bdd5003a PB |
270 | } |
271 | ||
95219897 | 272 | static void pl110_invalidate_display(void * opaque) |
bdd5003a | 273 | { |
513960ea | 274 | PL110State *s = (PL110State *)opaque; |
bdd5003a | 275 | s->invalidate = 1; |
bfdb3629 | 276 | if (pl110_enabled(s)) { |
c78f7137 | 277 | qemu_console_resize(s->con, s->cols, s->rows); |
bfdb3629 | 278 | } |
bdd5003a PB |
279 | } |
280 | ||
513960ea | 281 | static void pl110_update_palette(PL110State *s, int n) |
bdd5003a | 282 | { |
c78f7137 | 283 | DisplaySurface *surface = qemu_console_surface(s->con); |
bdd5003a PB |
284 | int i; |
285 | uint32_t raw; | |
286 | unsigned int r, g, b; | |
287 | ||
6e4c0d1f | 288 | raw = s->raw_palette[n]; |
bdd5003a PB |
289 | n <<= 1; |
290 | for (i = 0; i < 2; i++) { | |
291 | r = (raw & 0x1f) << 3; | |
292 | raw >>= 5; | |
293 | g = (raw & 0x1f) << 3; | |
294 | raw >>= 5; | |
295 | b = (raw & 0x1f) << 3; | |
296 | /* The I bit is ignored. */ | |
297 | raw >>= 6; | |
c78f7137 | 298 | switch (surface_bits_per_pixel(surface)) { |
bdd5003a | 299 | case 8: |
6e4c0d1f | 300 | s->palette[n] = rgb_to_pixel8(r, g, b); |
bdd5003a PB |
301 | break; |
302 | case 15: | |
6e4c0d1f | 303 | s->palette[n] = rgb_to_pixel15(r, g, b); |
bdd5003a PB |
304 | break; |
305 | case 16: | |
6e4c0d1f | 306 | s->palette[n] = rgb_to_pixel16(r, g, b); |
bdd5003a PB |
307 | break; |
308 | case 24: | |
309 | case 32: | |
6e4c0d1f | 310 | s->palette[n] = rgb_to_pixel32(r, g, b); |
bdd5003a PB |
311 | break; |
312 | } | |
313 | n++; | |
314 | } | |
315 | } | |
316 | ||
513960ea | 317 | static void pl110_resize(PL110State *s, int width, int height) |
bdd5003a PB |
318 | { |
319 | if (width != s->cols || height != s->rows) { | |
320 | if (pl110_enabled(s)) { | |
c78f7137 | 321 | qemu_console_resize(s->con, width, height); |
bdd5003a PB |
322 | } |
323 | } | |
324 | s->cols = width; | |
325 | s->rows = height; | |
326 | } | |
327 | ||
328 | /* Update interrupts. */ | |
513960ea | 329 | static void pl110_update(PL110State *s) |
bdd5003a | 330 | { |
24da047a LW |
331 | /* Raise IRQ if enabled and any status bit is 1 */ |
332 | if (s->int_status & s->int_mask) { | |
333 | qemu_irq_raise(s->irq); | |
334 | } else { | |
335 | qemu_irq_lower(s->irq); | |
336 | } | |
337 | } | |
338 | ||
339 | static void pl110_vblank_interrupt(void *opaque) | |
340 | { | |
341 | PL110State *s = opaque; | |
342 | ||
343 | /* Fire the vertical compare and next base IRQs and re-arm */ | |
344 | s->int_status |= (PL110_IE_NB | PL110_IE_VC); | |
345 | timer_mod(s->vblank_timer, | |
346 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
347 | NANOSECONDS_PER_SECOND / 60); | |
348 | pl110_update(s); | |
bdd5003a PB |
349 | } |
350 | ||
a8170e5e | 351 | static uint64_t pl110_read(void *opaque, hwaddr offset, |
1a6b31ce | 352 | unsigned size) |
bdd5003a | 353 | { |
513960ea | 354 | PL110State *s = (PL110State *)opaque; |
bdd5003a | 355 | |
bdd5003a | 356 | if (offset >= 0xfe0 && offset < 0x1000) { |
4fbf5556 | 357 | return idregs[s->version][(offset - 0xfe0) >> 2]; |
bdd5003a PB |
358 | } |
359 | if (offset >= 0x200 && offset < 0x400) { | |
6e4c0d1f | 360 | return s->raw_palette[(offset - 0x200) >> 2]; |
bdd5003a PB |
361 | } |
362 | switch (offset >> 2) { | |
363 | case 0: /* LCDTiming0 */ | |
364 | return s->timing[0]; | |
365 | case 1: /* LCDTiming1 */ | |
366 | return s->timing[1]; | |
367 | case 2: /* LCDTiming2 */ | |
368 | return s->timing[2]; | |
369 | case 3: /* LCDTiming3 */ | |
370 | return s->timing[3]; | |
371 | case 4: /* LCDUPBASE */ | |
372 | return s->upbase; | |
373 | case 5: /* LCDLPBASE */ | |
374 | return s->lpbase; | |
375 | case 6: /* LCDIMSC */ | |
c7bf3492 | 376 | if (s->version != VERSION_PL110) { |
4fbf5556 PM |
377 | return s->cr; |
378 | } | |
bdd5003a PB |
379 | return s->int_mask; |
380 | case 7: /* LCDControl */ | |
c7bf3492 | 381 | if (s->version != VERSION_PL110) { |
4fbf5556 PM |
382 | return s->int_mask; |
383 | } | |
bdd5003a PB |
384 | return s->cr; |
385 | case 8: /* LCDRIS */ | |
386 | return s->int_status; | |
387 | case 9: /* LCDMIS */ | |
388 | return s->int_status & s->int_mask; | |
389 | case 11: /* LCDUPCURR */ | |
390 | /* TODO: Implement vertical refresh. */ | |
391 | return s->upbase; | |
392 | case 12: /* LCDLPCURR */ | |
393 | return s->lpbase; | |
394 | default: | |
375cb560 PM |
395 | qemu_log_mask(LOG_GUEST_ERROR, |
396 | "pl110_read: Bad offset %x\n", (int)offset); | |
bdd5003a PB |
397 | return 0; |
398 | } | |
399 | } | |
400 | ||
a8170e5e | 401 | static void pl110_write(void *opaque, hwaddr offset, |
1a6b31ce | 402 | uint64_t val, unsigned size) |
bdd5003a | 403 | { |
513960ea | 404 | PL110State *s = (PL110State *)opaque; |
bdd5003a PB |
405 | int n; |
406 | ||
407 | /* For simplicity invalidate the display whenever a control register | |
66a0a2cb | 408 | is written to. */ |
bdd5003a | 409 | s->invalidate = 1; |
bdd5003a | 410 | if (offset >= 0x200 && offset < 0x400) { |
6e4c0d1f | 411 | /* Palette. */ |
bdd5003a | 412 | n = (offset - 0x200) >> 2; |
6e4c0d1f PM |
413 | s->raw_palette[(offset - 0x200) >> 2] = val; |
414 | pl110_update_palette(s, n); | |
e10c2bfb | 415 | return; |
bdd5003a PB |
416 | } |
417 | switch (offset >> 2) { | |
418 | case 0: /* LCDTiming0 */ | |
419 | s->timing[0] = val; | |
420 | n = ((val & 0xfc) + 4) * 4; | |
421 | pl110_resize(s, n, s->rows); | |
422 | break; | |
423 | case 1: /* LCDTiming1 */ | |
424 | s->timing[1] = val; | |
425 | n = (val & 0x3ff) + 1; | |
426 | pl110_resize(s, s->cols, n); | |
427 | break; | |
428 | case 2: /* LCDTiming2 */ | |
429 | s->timing[2] = val; | |
430 | break; | |
431 | case 3: /* LCDTiming3 */ | |
432 | s->timing[3] = val; | |
433 | break; | |
434 | case 4: /* LCDUPBASE */ | |
435 | s->upbase = val; | |
436 | break; | |
437 | case 5: /* LCDLPBASE */ | |
438 | s->lpbase = val; | |
439 | break; | |
440 | case 6: /* LCDIMSC */ | |
c7bf3492 | 441 | if (s->version != VERSION_PL110) { |
cdbdb648 | 442 | goto control; |
4fbf5556 | 443 | } |
cdbdb648 | 444 | imsc: |
bdd5003a PB |
445 | s->int_mask = val; |
446 | pl110_update(s); | |
447 | break; | |
448 | case 7: /* LCDControl */ | |
c7bf3492 | 449 | if (s->version != VERSION_PL110) { |
cdbdb648 | 450 | goto imsc; |
4fbf5556 | 451 | } |
cdbdb648 | 452 | control: |
bdd5003a PB |
453 | s->cr = val; |
454 | s->bpp = (val >> 1) & 7; | |
455 | if (pl110_enabled(s)) { | |
c78f7137 | 456 | qemu_console_resize(s->con, s->cols, s->rows); |
24da047a LW |
457 | timer_mod(s->vblank_timer, |
458 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
459 | NANOSECONDS_PER_SECOND / 60); | |
460 | } else { | |
461 | timer_del(s->vblank_timer); | |
bdd5003a PB |
462 | } |
463 | break; | |
464 | case 10: /* LCDICR */ | |
465 | s->int_status &= ~val; | |
466 | pl110_update(s); | |
467 | break; | |
468 | default: | |
375cb560 PM |
469 | qemu_log_mask(LOG_GUEST_ERROR, |
470 | "pl110_write: Bad offset %x\n", (int)offset); | |
bdd5003a PB |
471 | } |
472 | } | |
473 | ||
1a6b31ce AK |
474 | static const MemoryRegionOps pl110_ops = { |
475 | .read = pl110_read, | |
476 | .write = pl110_write, | |
477 | .endianness = DEVICE_NATIVE_ENDIAN, | |
bdd5003a PB |
478 | }; |
479 | ||
242ea2c6 PM |
480 | static void pl110_mux_ctrl_set(void *opaque, int line, int level) |
481 | { | |
513960ea | 482 | PL110State *s = (PL110State *)opaque; |
242ea2c6 PM |
483 | s->mux_ctrl = level; |
484 | } | |
485 | ||
128939a9 PM |
486 | static int vmstate_pl110_post_load(void *opaque, int version_id) |
487 | { | |
513960ea | 488 | PL110State *s = opaque; |
128939a9 PM |
489 | /* Make sure we redraw, and at the right size */ |
490 | pl110_invalidate_display(s); | |
491 | return 0; | |
492 | } | |
493 | ||
380cd056 GH |
494 | static const GraphicHwOps pl110_gfx_ops = { |
495 | .invalidate = pl110_invalidate_display, | |
496 | .gfx_update = pl110_update_display, | |
497 | }; | |
498 | ||
caae8032 | 499 | static void pl110_realize(DeviceState *dev, Error **errp) |
bdd5003a | 500 | { |
5d7a11e4 | 501 | PL110State *s = PL110(dev); |
caae8032 | 502 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bdd5003a | 503 | |
3eadad55 | 504 | memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); |
5d7a11e4 AF |
505 | sysbus_init_mmio(sbd, &s->iomem); |
506 | sysbus_init_irq(sbd, &s->irq); | |
24da047a LW |
507 | s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
508 | pl110_vblank_interrupt, s); | |
5d7a11e4 | 509 | qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); |
5643706a | 510 | s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s); |
bdd5003a | 511 | } |
2e9bdce5 | 512 | |
5d7a11e4 AF |
513 | static void pl110_init(Object *obj) |
514 | { | |
515 | PL110State *s = PL110(obj); | |
516 | ||
c7bf3492 | 517 | s->version = VERSION_PL110; |
5d7a11e4 AF |
518 | } |
519 | ||
520 | static void pl110_versatile_init(Object *obj) | |
2e9bdce5 | 521 | { |
5d7a11e4 AF |
522 | PL110State *s = PL110(obj); |
523 | ||
c7bf3492 | 524 | s->version = VERSION_PL110_VERSATILE; |
4fbf5556 PM |
525 | } |
526 | ||
5d7a11e4 | 527 | static void pl111_init(Object *obj) |
4fbf5556 | 528 | { |
5d7a11e4 AF |
529 | PL110State *s = PL110(obj); |
530 | ||
c7bf3492 | 531 | s->version = VERSION_PL111; |
2e9bdce5 PB |
532 | } |
533 | ||
999e12bb AL |
534 | static void pl110_class_init(ObjectClass *klass, void *data) |
535 | { | |
39bffca2 | 536 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 537 | |
125ee0ed | 538 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
39bffca2 | 539 | dc->vmsd = &vmstate_pl110; |
caae8032 | 540 | dc->realize = pl110_realize; |
999e12bb AL |
541 | } |
542 | ||
8c43a6f0 | 543 | static const TypeInfo pl110_info = { |
5d7a11e4 | 544 | .name = TYPE_PL110, |
39bffca2 | 545 | .parent = TYPE_SYS_BUS_DEVICE, |
513960ea | 546 | .instance_size = sizeof(PL110State), |
5d7a11e4 | 547 | .instance_init = pl110_init, |
39bffca2 | 548 | .class_init = pl110_class_init, |
8c60d065 PM |
549 | }; |
550 | ||
8c43a6f0 | 551 | static const TypeInfo pl110_versatile_info = { |
39bffca2 | 552 | .name = "pl110_versatile", |
5d7a11e4 AF |
553 | .parent = TYPE_PL110, |
554 | .instance_init = pl110_versatile_init, | |
8c60d065 PM |
555 | }; |
556 | ||
8c43a6f0 | 557 | static const TypeInfo pl111_info = { |
39bffca2 | 558 | .name = "pl111", |
5d7a11e4 AF |
559 | .parent = TYPE_PL110, |
560 | .instance_init = pl111_init, | |
4fbf5556 PM |
561 | }; |
562 | ||
83f7d43a | 563 | static void pl110_register_types(void) |
2e9bdce5 | 564 | { |
39bffca2 AL |
565 | type_register_static(&pl110_info); |
566 | type_register_static(&pl110_versatile_info); | |
567 | type_register_static(&pl111_info); | |
2e9bdce5 PB |
568 | } |
569 | ||
83f7d43a | 570 | type_init(pl110_register_types) |