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[thirdparty/qemu.git] / hw / display / virtio-vga.c
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9b8bfe21 1#include "qemu/osdep.h"
c5d4dac8 2#include "hw/pci/pci.h"
7ecb381f 3#include "hw/virtio/virtio-gpu.h"
d0f0c865 4#include "qapi/error.h"
0b8fa32f 5#include "qemu/module.h"
c68082c4 6#include "virtio-vga.h"
c5d4dac8 7
c68082c4 8static void virtio_vga_base_invalidate_display(void *opaque)
c5d4dac8 9{
c68082c4
MAL
10 VirtIOVGABase *vvga = opaque;
11 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 12
50d8e25e 13 if (g->enable) {
c68082c4 14 virtio_gpu_ops.invalidate(g);
c5d4dac8
GH
15 } else {
16 vvga->vga.hw_ops->invalidate(&vvga->vga);
17 }
18}
19
c68082c4 20static void virtio_vga_base_update_display(void *opaque)
c5d4dac8 21{
c68082c4
MAL
22 VirtIOVGABase *vvga = opaque;
23 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 24
50d8e25e 25 if (g->enable) {
c68082c4 26 virtio_gpu_ops.gfx_update(g);
c5d4dac8
GH
27 } else {
28 vvga->vga.hw_ops->gfx_update(&vvga->vga);
29 }
30}
31
c68082c4 32static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata)
c5d4dac8 33{
c68082c4
MAL
34 VirtIOVGABase *vvga = opaque;
35 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 36
50d8e25e 37 if (g->enable) {
c5d4dac8 38 if (virtio_gpu_ops.text_update) {
c68082c4 39 virtio_gpu_ops.text_update(g, chardata);
c5d4dac8
GH
40 }
41 } else {
42 if (vvga->vga.hw_ops->text_update) {
43 vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
44 }
45 }
46}
47
c68082c4 48static int virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
c5d4dac8 49{
c68082c4
MAL
50 VirtIOVGABase *vvga = opaque;
51 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8
GH
52
53 if (virtio_gpu_ops.ui_info) {
c68082c4 54 return virtio_gpu_ops.ui_info(g, idx, info);
c5d4dac8
GH
55 }
56 return -1;
57}
58
c68082c4 59static void virtio_vga_base_gl_block(void *opaque, bool block)
321c9adb 60{
c68082c4
MAL
61 VirtIOVGABase *vvga = opaque;
62 VirtIOGPUBase *g = vvga->vgpu;
321c9adb
GH
63
64 if (virtio_gpu_ops.gl_block) {
c68082c4 65 virtio_gpu_ops.gl_block(g, block);
321c9adb
GH
66 }
67}
68
c68082c4
MAL
69static const GraphicHwOps virtio_vga_base_ops = {
70 .invalidate = virtio_vga_base_invalidate_display,
71 .gfx_update = virtio_vga_base_update_display,
72 .text_update = virtio_vga_base_text_update,
73 .ui_info = virtio_vga_base_ui_info,
74 .gl_block = virtio_vga_base_gl_block,
c5d4dac8
GH
75};
76
c68082c4 77static const VMStateDescription vmstate_virtio_vga_base = {
0c244e50
GH
78 .name = "virtio-vga",
79 .version_id = 2,
80 .minimum_version_id = 2,
81 .fields = (VMStateField[]) {
82 /* no pci stuff here, saving the virtio device will handle that */
c68082c4
MAL
83 VMSTATE_STRUCT(vga, VirtIOVGABase, 0,
84 vmstate_vga_common, VGACommonState),
0c244e50
GH
85 VMSTATE_END_OF_LIST()
86 }
87};
88
c5d4dac8 89/* VGA device wrapper around PCI device around virtio GPU */
c68082c4 90static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
c5d4dac8 91{
c68082c4
MAL
92 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev);
93 VirtIOGPUBase *g = vvga->vgpu;
c5d4dac8 94 VGACommonState *vga = &vvga->vga;
d0f0c865 95 Error *err = NULL;
c5d4dac8 96 uint32_t offset;
e1888295 97 int i;
c5d4dac8
GH
98
99 /* init vga compat bits */
100 vga->vram_size_mb = 8;
1fcfdc43 101 vga_common_init(vga, OBJECT(vpci_dev));
c5d4dac8
GH
102 vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
103 pci_address_space_io(&vpci_dev->pci_dev), true);
104 pci_register_bar(&vpci_dev->pci_dev, 0,
105 PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
106
107 /*
108 * Configure virtio bar and regions
109 *
110 * We use bar #2 for the mmio regions, to be compatible with stdvga.
111 * virtio regions are moved to the end of bar #2, to make room for
112 * the stdvga mmio registers at the start of bar #2.
113 */
7a25126d
CF
114 vpci_dev->modern_mem_bar_idx = 2;
115 vpci_dev->msix_bar_idx = 4;
c2843e93
GH
116
117 if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
118 /*
119 * with page-per-vq=off there is no padding space we can use
120 * for the stdvga registers. Make the common and isr regions
121 * smaller then.
122 */
123 vpci_dev->common.size /= 2;
124 vpci_dev->isr.size /= 2;
125 }
126
c5d4dac8
GH
127 offset = memory_region_size(&vpci_dev->modern_bar);
128 offset -= vpci_dev->notify.size;
129 vpci_dev->notify.offset = offset;
130 offset -= vpci_dev->device.size;
131 vpci_dev->device.offset = offset;
132 offset -= vpci_dev->isr.size;
133 vpci_dev->isr.offset = offset;
134 offset -= vpci_dev->common.size;
135 vpci_dev->common.offset = offset;
136
137 /* init virtio bits */
138 qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus));
dd56040d 139 virtio_pci_force_virtio_1(vpci_dev);
d0f0c865
MAL
140 object_property_set_bool(OBJECT(g), true, "realized", &err);
141 if (err) {
142 error_propagate(errp, err);
143 return;
144 }
c5d4dac8
GH
145
146 /* add stdvga mmio regions */
93abfc88 147 pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar,
d46b40fc 148 vvga->vga_mrs, true, false);
c5d4dac8
GH
149
150 vga->con = g->scanout[0].con;
c68082c4 151 graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga);
e1888295
GH
152
153 for (i = 0; i < g->conf.max_outputs; i++) {
154 object_property_set_link(OBJECT(g->scanout[i].con),
155 OBJECT(vpci_dev),
156 "device", errp);
157 }
c5d4dac8
GH
158}
159
c68082c4 160static void virtio_vga_base_reset(DeviceState *dev)
c5d4dac8 161{
c68082c4
MAL
162 VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev);
163 VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev);
c5d4dac8 164
43e4dbe2 165 /* reset virtio-gpu */
3912e66a 166 klass->parent_reset(dev);
43e4dbe2
GH
167
168 /* reset vga */
169 vga_common_reset(&vvga->vga);
c5d4dac8
GH
170 vga_dirty_log_start(&vvga->vga);
171}
172
c68082c4 173static Property virtio_vga_base_properties[] = {
c5d4dac8
GH
174 DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
175 DEFINE_PROP_END_OF_LIST(),
176};
177
c68082c4 178static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
c5d4dac8
GH
179{
180 DeviceClass *dc = DEVICE_CLASS(klass);
181 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
c68082c4 182 VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
c5d4dac8
GH
183 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
184
185 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
c68082c4
MAL
186 dc->props = virtio_vga_base_properties;
187 dc->vmsd = &vmstate_virtio_vga_base;
c5d4dac8 188 dc->hotpluggable = false;
c68082c4 189 device_class_set_parent_reset(dc, virtio_vga_base_reset,
3912e66a 190 &v->parent_reset);
c5d4dac8 191
c68082c4 192 k->realize = virtio_vga_base_realize;
c5d4dac8
GH
193 pcidev_k->romfile = "vgabios-virtio.bin";
194 pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
195}
196
c68082c4
MAL
197static TypeInfo virtio_vga_base_info = {
198 .name = TYPE_VIRTIO_VGA_BASE,
199 .parent = TYPE_VIRTIO_PCI,
200 .instance_size = sizeof(struct VirtIOVGABase),
201 .class_size = sizeof(struct VirtIOVGABaseClass),
202 .class_init = virtio_vga_base_class_init,
203 .abstract = true,
204};
205
206#define TYPE_VIRTIO_VGA "virtio-vga"
207
208#define VIRTIO_VGA(obj) \
209 OBJECT_CHECK(VirtIOVGA, (obj), TYPE_VIRTIO_VGA)
210
211typedef struct VirtIOVGA {
212 VirtIOVGABase parent_obj;
213
214 VirtIOGPU vdev;
215} VirtIOVGA;
216
c5d4dac8
GH
217static void virtio_vga_inst_initfn(Object *obj)
218{
219 VirtIOVGA *dev = VIRTIO_VGA(obj);
b3409a31
GH
220
221 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
222 TYPE_VIRTIO_GPU);
c68082c4 223 VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev);
c5d4dac8
GH
224}
225
c68082c4 226
a4ee4c8b
EH
227static VirtioPCIDeviceTypeInfo virtio_vga_info = {
228 .generic_name = TYPE_VIRTIO_VGA,
c68082c4 229 .parent = TYPE_VIRTIO_VGA_BASE,
c5d4dac8
GH
230 .instance_size = sizeof(struct VirtIOVGA),
231 .instance_init = virtio_vga_inst_initfn,
c5d4dac8
GH
232};
233
234static void virtio_vga_register_types(void)
235{
c68082c4 236 type_register_static(&virtio_vga_base_info);
a4ee4c8b 237 virtio_pci_types_register(&virtio_vga_info);
c5d4dac8
GH
238}
239
240type_init(virtio_vga_register_types)