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[thirdparty/qemu.git] / hw / dma / i82374.c
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1/*
2 * QEMU Intel 82374 emulation (Enhanced DMA controller)
3 *
4 * Copyright (c) 2010 Hervé Poussineau
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
0430891c 25#include "qemu/osdep.h"
0d09e41a 26#include "hw/isa/isa.h"
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27
28//#define DEBUG_I82374
29
30#ifdef DEBUG_I82374
31#define DPRINTF(fmt, ...) \
32do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
33#else
34#define DPRINTF(fmt, ...) \
35do {} while (0)
36#endif
37#define BADF(fmt, ...) \
38do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
39
40typedef struct I82374State {
41 uint8_t commands[8];
848696bf 42 PortioList port_list;
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43} I82374State;
44
45static const VMStateDescription vmstate_i82374 = {
46 .name = "i82374",
47 .version_id = 0,
48 .minimum_version_id = 0,
49 .fields = (VMStateField[]) {
50 VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
51 VMSTATE_END_OF_LIST()
52 },
53};
54
55static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
56{
57 uint32_t val = 0;
58
59 BADF("%s: %08x\n", __func__, nport);
60
61 DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
62 return val;
63}
64
65static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
66{
67 DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
68
69 if (data != 0x42) {
70 /* Not Stop S/G command */
71 BADF("%s: %08x=%08x\n", __func__, nport, data);
72 }
73}
74
75static uint32_t i82374_read_status(void *opaque, uint32_t nport)
76{
77 uint32_t val = 0;
78
79 BADF("%s: %08x\n", __func__, nport);
80
81 DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
82 return val;
83}
84
85static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
86{
87 DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
88
89 BADF("%s: %08x=%08x\n", __func__, nport, data);
90}
91
92static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
93{
94 uint32_t val = 0;
95
96 BADF("%s: %08x\n", __func__, nport);
97
98 DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
99 return val;
100}
101
db895a1e 102static void i82374_realize(I82374State *s, Error **errp)
23b96cdb 103{
5039d6e2 104 DMA_init(1);
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105 memset(s->commands, 0, sizeof(s->commands));
106}
107
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108#define TYPE_I82374 "i82374"
109#define I82374(obj) OBJECT_CHECK(ISAi82374State, (obj), TYPE_I82374)
110
23b96cdb 111typedef struct ISAi82374State {
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112 ISADevice parent_obj;
113
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114 uint32_t iobase;
115 I82374State state;
116} ISAi82374State;
117
118static const VMStateDescription vmstate_isa_i82374 = {
119 .name = "isa-i82374",
120 .version_id = 0,
121 .minimum_version_id = 0,
122 .fields = (VMStateField[]) {
123 VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
124 VMSTATE_END_OF_LIST()
125 },
126};
127
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128static const MemoryRegionPortio i82374_portio_list[] = {
129 { 0x0A, 1, 1, .read = i82374_read_isr, },
130 { 0x10, 8, 1, .write = i82374_write_command, },
131 { 0x18, 8, 1, .read = i82374_read_status, },
132 { 0x20, 0x20, 1,
133 .write = i82374_write_descriptor, .read = i82374_read_descriptor, },
134 PORTIO_END_OF_LIST(),
135};
136
db895a1e 137static void i82374_isa_realize(DeviceState *dev, Error **errp)
23b96cdb 138{
eb1440e7 139 ISAi82374State *isa = I82374(dev);
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140 I82374State *s = &isa->state;
141
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142 portio_list_init(&s->port_list, OBJECT(isa), i82374_portio_list, s,
143 "i82374");
144 portio_list_add(&s->port_list, isa_address_space_io(&isa->parent_obj),
f94b64ac 145 isa->iobase);
23b96cdb 146
db895a1e 147 i82374_realize(s, errp);
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148}
149
39bffca2 150static Property i82374_properties[] = {
c7bcc85d 151 DEFINE_PROP_UINT32("iobase", ISAi82374State, iobase, 0x400),
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152 DEFINE_PROP_END_OF_LIST()
153};
154
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155static void i82374_class_init(ObjectClass *klass, void *data)
156{
39bffca2 157 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 158
db895a1e 159 dc->realize = i82374_isa_realize;
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160 dc->vmsd = &vmstate_isa_i82374;
161 dc->props = i82374_properties;
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162}
163
8c43a6f0 164static const TypeInfo i82374_isa_info = {
eb1440e7 165 .name = TYPE_I82374,
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166 .parent = TYPE_ISA_DEVICE,
167 .instance_size = sizeof(ISAi82374State),
8f04ee08 168 .class_init = i82374_class_init,
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169};
170
83f7d43a 171static void i82374_register_types(void)
23b96cdb 172{
39bffca2 173 type_register_static(&i82374_isa_info);
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174}
175
83f7d43a 176type_init(i82374_register_types)