[thirdparty/qemu.git] / hw / dma / sun4m_iommu.c

/*
 * QEMU Sun4m iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "trace.h"

/*
 * I/O MMU used by Sun4m systems
 *
 * Chipset docs:
 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
 */

#define IOMMU_NREGS         (4*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
                                          transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
                                          12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
                                          acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
                                          hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK     0xff0fffff

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK      0x801f000f

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
                                          bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
#define IOMMU_MASK_ID_MASK  0x00ffffff

#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
                                          Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define IOMMU_PAGE_SHIFT    12
#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)

#define TYPE_SUN4M_IOMMU "iommu"
#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)

typedef struct IOMMUState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t regs[IOMMU_NREGS];
    hwaddr iostart;
    qemu_irq irq;
    uint32_t version;
} IOMMUState;

static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    IOMMUState *s = opaque;
    hwaddr saddr;
    uint32_t ret;

    saddr = addr >> 2;
    switch (saddr) {
    default:
        ret = s->regs[saddr];
        break;
    case IOMMU_AFAR:
    case IOMMU_AFSR:
        ret = s->regs[saddr];
        qemu_irq_lower(s->irq);
        break;
    }
    trace_sun4m_iommu_mem_readl(saddr, ret);
    return ret;
}

static void iommu_mem_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
{
    IOMMUState *s = opaque;
    hwaddr saddr;

    saddr = addr >> 2;
    trace_sun4m_iommu_mem_writel(saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        trace_sun4m_iommu_mem_writel_tlbflush(val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        trace_sun4m_iommu_mem_writel_pgflush(val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_AFAR:
        s->regs[saddr] = val;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_AER:
        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
        break;
    case IOMMU_AFSR:
        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    case IOMMU_MASK_ID:
        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static const MemoryRegionOps iommu_mem_ops = {
    .read = iommu_mem_read,
    .write = iommu_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
    uint32_t ret;
    hwaddr iopte;
    hwaddr pa = addr;

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
    ret = ldl_be_phys(&address_space_memory, iopte);
    trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
    return ret;
}

static hwaddr iommu_translate_pa(hwaddr addr,
                                             uint32_t pte)
{
    hwaddr pa;

    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
    trace_sun4m_iommu_translate_pa(addr, pa, pte);
    return pa;
}

static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
                           int is_write)
{
    trace_sun4m_iommu_bad_addr(addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
        IOMMU_AFSR_FAV;
    if (!is_write)
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    s->regs[IOMMU_AFAR] = addr;
    qemu_irq_raise(s->irq);
}

void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    hwaddr page, phys_addr;

    while (len > 0) {
        page = addr & IOMMU_PAGE_MASK;
        l = (page + IOMMU_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID)) {
            iommu_bad_addr(opaque, page, is_write);
            return;
        }
        phys_addr = iommu_translate_pa(addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE)) {
                iommu_bad_addr(opaque, page, is_write);
                return;
            }
            cpu_physical_memory_write(phys_addr, buf, l);
        } else {
            cpu_physical_memory_read(phys_addr, buf, l);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static const VMStateDescription vmstate_iommu = {
    .name ="iommu",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
        VMSTATE_UINT64(iostart, IOMMUState),
        VMSTATE_END_OF_LIST()
    }
};

static void iommu_reset(DeviceState *d)
{
    IOMMUState *s = SUN4M_IOMMU(d);

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = s->version;
    s->regs[IOMMU_ARBEN] = IOMMU_MID;
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
}

static int iommu_init1(SysBusDevice *dev)
{
    IOMMUState *s = SUN4M_IOMMU(dev);

    sysbus_init_irq(dev, &s->irq);

    memory_region_init_io(&s->iomem, OBJECT(s), &iommu_mem_ops, s, "iommu",
                          IOMMU_NREGS * sizeof(uint32_t));
    sysbus_init_mmio(dev, &s->iomem);

    return 0;
}

static Property iommu_properties[] = {
    DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void iommu_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = iommu_init1;
    dc->reset = iommu_reset;
    dc->vmsd = &vmstate_iommu;
    dc->props = iommu_properties;
}

static const TypeInfo iommu_info = {
    .name          = TYPE_SUN4M_IOMMU,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IOMMUState),
    .class_init    = iommu_class_init,
};

static void iommu_register_types(void)
{
    type_register_static(&iommu_info);
}

type_init(iommu_register_types)
Commit	Line	Data
420557e8	1	/*
93c5a32f	2	* QEMU Sun4m iommu emulation
420557e8	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
5f750b2e	24
0d09e41a	25	#include "hw/sparc/sun4m.h"
83c9f4ca	26	#include "hw/sysbus.h"
fdfba1a2	27	#include "exec/address-spaces.h"
97bf4851	28	#include "trace.h"
420557e8	29
93c5a32f BS	30	/*
	31	* I/O MMU used by Sun4m systems
	32	*
	33	* Chipset docs:
	34	* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
	35	* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
	36	*/
	37
e5e38121	38	#define IOMMU_NREGS (4*4096/4)
4e3b1ea1	39	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	40	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	41	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	42	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	43	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	44	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	50	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	51	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	52	#define IOMMU_CTRL_MASK 0x0000001d
	53
	54	#define IOMMU_BASE (0x0004 >> 2)
	55	#define IOMMU_BASE_MASK 0x07fffc00
	56
	57	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	58	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	59
	60	#define IOMMU_PGFLUSH (0x0018 >> 2)
	61	#define IOMMU_PGFLUSH_MASK 0xffffffff
	62
225d4be7 BS	63	#define IOMMU_AFSR (0x1000 >> 2)
225d4be7 BS	64	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
5ad6bb97 BS	65	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
	66	transaction */
	67	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
	68	12.8 us. */
	69	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
	70	acknowledge */
225d4be7 BS	71	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
225d4be7 BS	72	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
5ad6bb97 BS	73	#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
5ad6bb97 BS	74	hardware */
225d4be7 BS	75	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	76	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	77	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
c52428fc	78	#define IOMMU_AFSR_MASK 0xff0fffff
225d4be7 BS	79
	80	#define IOMMU_AFAR (0x1004 >> 2)
	81
7b169687 BS	82	#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
	83	#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
	84	#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
	85	#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
	86	#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
	87	#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
	88	#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
	89	#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
	90	#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
	91	#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
	92	#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
	93	#define IOMMU_AER_MASK 0x801f000f
	94
4e3b1ea1 FB	95	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	96	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	97	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	98	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
5ad6bb97 BS	99	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
5ad6bb97 BS	100	bypass enabled */
4e3b1ea1 FB	101	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	102	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	103	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	104	produced by this device as pure
4e3b1ea1 FB	105	physical. */
	106	#define IOMMU_SBCFG_MASK 0x00010003
	107
	108	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	109	#define IOMMU_ARBEN_MASK 0x001f0000
	110	#define IOMMU_MID 0x00000008
420557e8	111
e5e38121 BS	112	#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
	113	#define IOMMU_MASK_ID_MASK 0x00ffffff
	114
	115	#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
	116	#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
	117
420557e8	118	/* The format of an iopte in the page tables */
498fbd8a	119	#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
5ad6bb97 BS	120	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
5ad6bb97 BS	121	Viking/MXCC) */
ebabb67a	122	#define IOPTE_WRITE 0x00000004 /* Writable */
420557e8 FB	123	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	124	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	125
8b0de438 BS	126	#define IOMMU_PAGE_SHIFT 12
	127	#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
	128	#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
420557e8	129
049e7d22 AF	130	#define TYPE_SUN4M_IOMMU "iommu"
	131	#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)
	132
420557e8	133	typedef struct IOMMUState {
049e7d22 AF	134	SysBusDevice parent_obj;
049e7d22 AF	135
d224136c	136	MemoryRegion iomem;
66321a11	137	uint32_t regs[IOMMU_NREGS];
a8170e5e	138	hwaddr iostart;
ff403da6	139	qemu_irq irq;
149e1ea1	140	uint32_t version;
420557e8 FB	141	} IOMMUState;
420557e8 FB	142
a8170e5e	143	static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
d224136c	144	unsigned size)
420557e8 FB	145	{
420557e8 FB	146	IOMMUState *s = opaque;
a8170e5e	147	hwaddr saddr;
ff403da6	148	uint32_t ret;
420557e8	149
8da3ff18	150	saddr = addr >> 2;
420557e8 FB	151	switch (saddr) {
420557e8 FB	152	default:
ff403da6 BS	153	ret = s->regs[saddr];
	154	break;
	155	case IOMMU_AFAR:
	156	case IOMMU_AFSR:
	157	ret = s->regs[saddr];
	158	qemu_irq_lower(s->irq);
f930d07e	159	break;
420557e8	160	}
97bf4851	161	trace_sun4m_iommu_mem_readl(saddr, ret);
ff403da6	162	return ret;
420557e8 FB	163	}
420557e8 FB	164
a8170e5e	165	static void iommu_mem_write(void *opaque, hwaddr addr,
d224136c	166	uint64_t val, unsigned size)
420557e8 FB	167	{
420557e8 FB	168	IOMMUState *s = opaque;
a8170e5e	169	hwaddr saddr;
420557e8	170
8da3ff18	171	saddr = addr >> 2;
97bf4851	172	trace_sun4m_iommu_mem_writel(saddr, val);
420557e8	173	switch (saddr) {
4e3b1ea1	174	case IOMMU_CTRL:
f930d07e BS	175	switch (val & IOMMU_CTRL_RNGE) {
	176	case IOMMU_RNGE_16MB:
	177	s->iostart = 0xffffffffff000000ULL;
	178	break;
	179	case IOMMU_RNGE_32MB:
	180	s->iostart = 0xfffffffffe000000ULL;
	181	break;
	182	case IOMMU_RNGE_64MB:
	183	s->iostart = 0xfffffffffc000000ULL;
	184	break;
	185	case IOMMU_RNGE_128MB:
	186	s->iostart = 0xfffffffff8000000ULL;
	187	break;
	188	case IOMMU_RNGE_256MB:
	189	s->iostart = 0xfffffffff0000000ULL;
	190	break;
	191	case IOMMU_RNGE_512MB:
	192	s->iostart = 0xffffffffe0000000ULL;
	193	break;
	194	case IOMMU_RNGE_1GB:
	195	s->iostart = 0xffffffffc0000000ULL;
	196	break;
	197	default:
	198	case IOMMU_RNGE_2GB:
	199	s->iostart = 0xffffffff80000000ULL;
	200	break;
	201	}
97bf4851	202	trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
7fbfb139	203	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| s->version);
f930d07e	204	break;
4e3b1ea1	205	case IOMMU_BASE:
f930d07e BS	206	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	207	break;
4e3b1ea1	208	case IOMMU_TLBFLUSH:
97bf4851	209	trace_sun4m_iommu_mem_writel_tlbflush(val);
f930d07e BS	210	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
f930d07e BS	211	break;
4e3b1ea1	212	case IOMMU_PGFLUSH:
97bf4851	213	trace_sun4m_iommu_mem_writel_pgflush(val);
f930d07e BS	214	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
f930d07e BS	215	break;
ff403da6 BS	216	case IOMMU_AFAR:
	217	s->regs[saddr] = val;
	218	qemu_irq_lower(s->irq);
	219	break;
7b169687 BS	220	case IOMMU_AER:
	221	s->regs[saddr] = (val & IOMMU_AER_MASK) \| IOMMU_AER_EN_P0_ARB;
	222	break;
c52428fc BS	223	case IOMMU_AFSR:
c52428fc BS	224	s->regs[saddr] = (val & IOMMU_AFSR_MASK) \| IOMMU_AFSR_RESV;
ff403da6	225	qemu_irq_lower(s->irq);
c52428fc	226	break;
4e3b1ea1 FB	227	case IOMMU_SBCFG0:
	228	case IOMMU_SBCFG1:
	229	case IOMMU_SBCFG2:
	230	case IOMMU_SBCFG3:
f930d07e BS	231	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	232	break;
4e3b1ea1 FB	233	case IOMMU_ARBEN:
	234	// XXX implement SBus probing: fault when reading unmapped
	235	// addresses, fault cause and address stored to MMU/IOMMU
f930d07e BS	236	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	237	break;
e5e38121 BS	238	case IOMMU_MASK_ID:
	239	s->regs[saddr] \|= val & IOMMU_MASK_ID_MASK;
	240	break;
420557e8	241	default:
f930d07e BS	242	s->regs[saddr] = val;
f930d07e BS	243	break;
420557e8 FB	244	}
	245	}
	246
d224136c AK	247	static const MemoryRegionOps iommu_mem_ops = {
	248	.read = iommu_mem_read,
	249	.write = iommu_mem_write,
	250	.endianness = DEVICE_NATIVE_ENDIAN,
	251	.valid = {
	252	.min_access_size = 4,
	253	.max_access_size = 4,
	254	},
420557e8 FB	255	};
420557e8 FB	256
a8170e5e	257	static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
420557e8	258	{
5e3b100b	259	uint32_t ret;
a8170e5e AK	260	hwaddr iopte;
a8170e5e AK	261	hwaddr pa = addr;
420557e8	262
981a2e99	263	iopte = s->regs[IOMMU_BASE] << 4;
66321a11	264	addr &= ~s->iostart;
8b0de438	265	iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
fdfba1a2	266	ret = ldl_be_phys(&address_space_memory, iopte);
97bf4851	267	trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
981a2e99	268	return ret;
a917d384 PB	269	}
a917d384 PB	270
a8170e5e	271	static hwaddr iommu_translate_pa(hwaddr addr,
5dcb6b91	272	uint32_t pte)
a917d384	273	{
a8170e5e	274	hwaddr pa;
5dcb6b91	275
8b0de438	276	pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
97bf4851	277	trace_sun4m_iommu_translate_pa(addr, pa, pte);
66321a11	278	return pa;
420557e8 FB	279	}
420557e8 FB	280
a8170e5e	281	static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
5ad6bb97	282	int is_write)
225d4be7	283	{
97bf4851	284	trace_sun4m_iommu_bad_addr(addr);
5ad6bb97	285	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| IOMMU_AFSR_RESV \|
225d4be7 BS	286	IOMMU_AFSR_FAV;
	287	if (!is_write)
	288	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
	289	s->regs[IOMMU_AFAR] = addr;
ff403da6	290	qemu_irq_raise(s->irq);
225d4be7 BS	291	}
225d4be7 BS	292
a8170e5e	293	void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
67e999be	294	uint8_t *buf, int len, int is_write)
a917d384	295	{
5dcb6b91 BS	296	int l;
5dcb6b91 BS	297	uint32_t flags;
a8170e5e	298	hwaddr page, phys_addr;
a917d384 PB	299
a917d384 PB	300	while (len > 0) {
8b0de438 BS	301	page = addr & IOMMU_PAGE_MASK;
8b0de438 BS	302	l = (page + IOMMU_PAGE_SIZE) - addr;
a917d384 PB	303	if (l > len)
	304	l = len;
	305	flags = iommu_page_get_flags(opaque, page);
225d4be7 BS	306	if (!(flags & IOPTE_VALID)) {
225d4be7 BS	307	iommu_bad_addr(opaque, page, is_write);
a917d384	308	return;
225d4be7	309	}
22548760	310	phys_addr = iommu_translate_pa(addr, flags);
a917d384	311	if (is_write) {
225d4be7 BS	312	if (!(flags & IOPTE_WRITE)) {
225d4be7 BS	313	iommu_bad_addr(opaque, page, is_write);
a917d384	314	return;
225d4be7	315	}
a5cdf952	316	cpu_physical_memory_write(phys_addr, buf, l);
a917d384	317	} else {
a5cdf952	318	cpu_physical_memory_read(phys_addr, buf, l);
a917d384 PB	319	}
	320	len -= l;
	321	buf += l;
	322	addr += l;
	323	}
	324	}
	325
db3c9e08 BS	326	static const VMStateDescription vmstate_iommu = {
	327	.name ="iommu",
	328	.version_id = 2,
	329	.minimum_version_id = 2,
	330	.minimum_version_id_old = 2,
	331	.fields = (VMStateField []) {
	332	VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
	333	VMSTATE_UINT64(iostart, IOMMUState),
	334	VMSTATE_END_OF_LIST()
	335	}
	336	};
e80cfcfc	337
1a522e8a	338	static void iommu_reset(DeviceState *d)
e80cfcfc	339	{
049e7d22	340	IOMMUState *s = SUN4M_IOMMU(d);
e80cfcfc	341
66321a11	342	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	343	s->iostart = 0;
7fbfb139 BS	344	s->regs[IOMMU_CTRL] = s->version;
7fbfb139 BS	345	s->regs[IOMMU_ARBEN] = IOMMU_MID;
5ad6bb97	346	s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
7b169687	347	s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB \| IOMMU_AER_EN_P1_ARB;
e5e38121	348	s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
e80cfcfc FB	349	}
e80cfcfc FB	350
81a322d4	351	static int iommu_init1(SysBusDevice *dev)
5f750b2e	352	{
049e7d22	353	IOMMUState *s = SUN4M_IOMMU(dev);
420557e8	354
5f750b2e	355	sysbus_init_irq(dev, &s->irq);
420557e8	356
3eadad55	357	memory_region_init_io(&s->iomem, OBJECT(s), &iommu_mem_ops, s, "iommu",
d224136c	358	IOMMU_NREGS * sizeof(uint32_t));
750ecd44	359	sysbus_init_mmio(dev, &s->iomem);
3b46e624	360
81a322d4	361	return 0;
420557e8	362	}
5f750b2e	363
999e12bb	364	static Property iommu_properties[] = {
c7bcc85d	365	DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
999e12bb AL	366	DEFINE_PROP_END_OF_LIST(),
	367	};
	368
	369	static void iommu_class_init(ObjectClass klass, void data)
	370	{
39bffca2	371	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	372	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	373
	374	k->init = iommu_init1;
39bffca2 AL	375	dc->reset = iommu_reset;
	376	dc->vmsd = &vmstate_iommu;
	377	dc->props = iommu_properties;
999e12bb AL	378	}
999e12bb AL	379
8c43a6f0	380	static const TypeInfo iommu_info = {
049e7d22	381	.name = TYPE_SUN4M_IOMMU,
39bffca2 AL	382	.parent = TYPE_SYS_BUS_DEVICE,
	383	.instance_size = sizeof(IOMMUState),
	384	.class_init = iommu_class_init,
5f750b2e BS	385	};
5f750b2e BS	386
83f7d43a	387	static void iommu_register_types(void)
5f750b2e	388	{
39bffca2	389	type_register_static(&iommu_info);
5f750b2e BS	390	}
5f750b2e BS	391
83f7d43a	392	type_init(iommu_register_types)