[thirdparty/qemu.git] / hw / input / lm832x.c

/*
 * National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
 *
 * Copyright (C) 2008 Nokia Corporation
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/i2c/i2c.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "ui/console.h"
#include "qom/object.h"

#define TYPE_LM8323 "lm8323"
typedef struct LM823KbdState LM823KbdState;
#define LM8323(obj) OBJECT_CHECK(LM823KbdState, (obj), TYPE_LM8323)

struct LM823KbdState {
    I2CSlave parent_obj;

    uint8_t i2c_dir;
    uint8_t i2c_cycle;
    uint8_t reg;

    qemu_irq nirq;
    uint16_t model;

    struct {
        qemu_irq out[2];
        int in[2][2];
    } mux;

    uint8_t config;
    uint8_t status;
    uint8_t acttime;
    uint8_t error;
    uint8_t clock;

    struct {
        uint16_t pull;
        uint16_t mask;
        uint16_t dir;
        uint16_t level;
        qemu_irq out[16];
    } gpio;

    struct {
        uint8_t dbnctime;
        uint8_t size;
        uint8_t start;
        uint8_t len;
        uint8_t fifo[16];
    } kbd;

    struct {
        uint16_t file[256];
        uint8_t faddr;
        uint8_t addr[3];
        QEMUTimer *tm[3];
    } pwm;
};

#define INT_KEYPAD		(1 << 0)
#define INT_ERROR		(1 << 3)
#define INT_NOINIT		(1 << 4)
#define INT_PWMEND(n)		(1 << (5 + n))

#define ERR_BADPAR		(1 << 0)
#define ERR_CMDUNK		(1 << 1)
#define ERR_KEYOVR		(1 << 2)
#define ERR_FIFOOVR		(1 << 6)

static void lm_kbd_irq_update(LM823KbdState *s)
{
    qemu_set_irq(s->nirq, !s->status);
}

static void lm_kbd_gpio_update(LM823KbdState *s)
{
}

static void lm_kbd_reset(DeviceState *dev)
{
    LM823KbdState *s = LM8323(dev);

    s->config = 0x80;
    s->status = INT_NOINIT;
    s->acttime = 125;
    s->kbd.dbnctime = 3;
    s->kbd.size = 0x33;
    s->clock = 0x08;

    lm_kbd_irq_update(s);
    lm_kbd_gpio_update(s);
}

static void lm_kbd_error(LM823KbdState *s, int err)
{
    s->error |= err;
    s->status |= INT_ERROR;
    lm_kbd_irq_update(s);
}

static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
{
}

static void lm_kbd_pwm_start(LM823KbdState *s, int line)
{
    lm_kbd_pwm_tick(s, line);
}

static void lm_kbd_pwm0_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 0);
}
static void lm_kbd_pwm1_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 1);
}
static void lm_kbd_pwm2_tick(void *opaque)
{
    lm_kbd_pwm_tick(opaque, 2);
}

enum {
    LM832x_CMD_READ_ID		= 0x80, /* Read chip ID. */
    LM832x_CMD_WRITE_CFG	= 0x81, /* Set configuration item. */
    LM832x_CMD_READ_INT		= 0x82, /* Get interrupt status. */
    LM832x_CMD_RESET		= 0x83, /* Reset, same as external one */
    LM823x_CMD_WRITE_PULL_DOWN	= 0x84, /* Select GPIO pull-up/down. */
    LM832x_CMD_WRITE_PORT_SEL	= 0x85, /* Select GPIO in/out. */
    LM832x_CMD_WRITE_PORT_STATE	= 0x86, /* Set GPIO pull-up/down. */
    LM832x_CMD_READ_PORT_SEL	= 0x87, /* Get GPIO in/out. */
    LM832x_CMD_READ_PORT_STATE	= 0x88, /* Get GPIO pull-up/down. */
    LM832x_CMD_READ_FIFO	= 0x89, /* Read byte from FIFO. */
    LM832x_CMD_RPT_READ_FIFO	= 0x8a, /* Read FIFO (no increment). */
    LM832x_CMD_SET_ACTIVE	= 0x8b, /* Set active time. */
    LM832x_CMD_READ_ERROR	= 0x8c, /* Get error status. */
    LM832x_CMD_READ_ROTATOR	= 0x8e, /* Read rotator status. */
    LM832x_CMD_SET_DEBOUNCE	= 0x8f, /* Set debouncing time. */
    LM832x_CMD_SET_KEY_SIZE	= 0x90, /* Set keypad size. */
    LM832x_CMD_READ_KEY_SIZE	= 0x91, /* Get keypad size. */
    LM832x_CMD_READ_CFG		= 0x92, /* Get configuration item. */
    LM832x_CMD_WRITE_CLOCK	= 0x93, /* Set clock config. */
    LM832x_CMD_READ_CLOCK	= 0x94, /* Get clock config. */
    LM832x_CMD_PWM_WRITE	= 0x95, /* Write PWM script. */
    LM832x_CMD_PWM_START	= 0x96, /* Start PWM engine. */
    LM832x_CMD_PWM_STOP		= 0x97, /* Stop PWM engine. */
    LM832x_GENERAL_ERROR	= 0xff, /* There was one error.
                                           Previously was represented by -1
                                           This is not a command */
};

#define LM832x_MAX_KPX		8
#define LM832x_MAX_KPY		12

static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
{
    int ret;

    switch (reg) {
    case LM832x_CMD_READ_ID:
        ret = 0x0400;
        break;

    case LM832x_CMD_READ_INT:
        ret = s->status;
        if (!(s->status & INT_NOINIT)) {
            s->status = 0;
            lm_kbd_irq_update(s);
        }
        break;

    case LM832x_CMD_READ_PORT_SEL:
        ret = s->gpio.dir;
        break;
    case LM832x_CMD_READ_PORT_STATE:
        ret = s->gpio.mask;
        break;

    case LM832x_CMD_READ_FIFO:
        if (s->kbd.len <= 1)
            return 0x00;

        /* Example response from the two commands after a INT_KEYPAD
         * interrupt caused by the key 0x3c being pressed:
         * RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         *     READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         * RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
         *
         * 55 is the code of the key release event serviced in the previous
         * interrupt handling.
         *
         * TODO: find out whether the FIFO is advanced a single character
         * before reading every byte or the whole size of the FIFO at the
         * last LM832x_CMD_READ_FIFO.  This affects LM832x_CMD_RPT_READ_FIFO
         * output in cases where there are more than one event in the FIFO.
         * Assume 0xbc and 0x3c events are in the FIFO:
         * RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
         *     READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
         * Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
         */
        s->kbd.start ++;
        s->kbd.start &= sizeof(s->kbd.fifo) - 1;
        s->kbd.len --;

        return s->kbd.fifo[s->kbd.start];
    case LM832x_CMD_RPT_READ_FIFO:
        if (byte >= s->kbd.len)
            return 0x00;

        return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)];

    case LM832x_CMD_READ_ERROR:
        return s->error;

    case LM832x_CMD_READ_ROTATOR:
        return 0;

    case LM832x_CMD_READ_KEY_SIZE:
        return s->kbd.size;

    case LM832x_CMD_READ_CFG:
        return s->config & 0xf;

    case LM832x_CMD_READ_CLOCK:
        return (s->clock & 0xfc) | 2;

    default:
        lm_kbd_error(s, ERR_CMDUNK);
        fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
        return 0x00;
    }

    return ret >> (byte << 3);
}

static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
{
    switch (reg) {
    case LM832x_CMD_WRITE_CFG:
        s->config = value;
        /* This must be done whenever s->mux.in is updated (never).  */
        if ((s->config >> 1) & 1)			/* MUX1EN */
            qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]);
        if ((s->config >> 3) & 1)			/* MUX2EN */
            qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]);
        /* TODO: check that this is issued only following the chip reset
         * and not in the middle of operation and that it is followed by
         * the GPIO ports re-resablishing through WRITE_PORT_SEL and
         * WRITE_PORT_STATE (using a timer perhaps) and otherwise output
         * warnings.  */
        s->status = 0;
        lm_kbd_irq_update(s);
        s->kbd.len = 0;
        s->kbd.start = 0;
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM832x_CMD_RESET:
        if (value == 0xaa)
            lm_kbd_reset(DEVICE(s));
        else
            lm_kbd_error(s, ERR_BADPAR);
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM823x_CMD_WRITE_PULL_DOWN:
        if (!byte)
            s->gpio.pull = value;
        else {
            s->gpio.pull |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_WRITE_PORT_SEL:
        if (!byte)
            s->gpio.dir = value;
        else {
            s->gpio.dir |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_WRITE_PORT_STATE:
        if (!byte)
            s->gpio.mask = value;
        else {
            s->gpio.mask |= value << 8;
            lm_kbd_gpio_update(s);
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;

    case LM832x_CMD_SET_ACTIVE:
        s->acttime = value;
        s->reg = LM832x_GENERAL_ERROR;
        break;

    case LM832x_CMD_SET_DEBOUNCE:
        s->kbd.dbnctime = value;
        s->reg = LM832x_GENERAL_ERROR;
        if (!value)
            lm_kbd_error(s, ERR_BADPAR);
        break;

    case LM832x_CMD_SET_KEY_SIZE:
        s->kbd.size = value;
        s->reg = LM832x_GENERAL_ERROR;
        if (
                        (value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY ||
                        (value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX)
            lm_kbd_error(s, ERR_BADPAR);
        break;

    case LM832x_CMD_WRITE_CLOCK:
        s->clock = value;
        s->reg = LM832x_GENERAL_ERROR;
        if ((value & 3) && (value & 3) != 3) {
            lm_kbd_error(s, ERR_BADPAR);
            fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
                            __func__);
        }
        /* TODO: Validate that the command is only issued once */
        break;

    case LM832x_CMD_PWM_WRITE:
        if (byte == 0) {
            if (!(value & 3) || (value >> 2) > 59) {
                lm_kbd_error(s, ERR_BADPAR);
                s->reg = LM832x_GENERAL_ERROR;
                break;
            }

            s->pwm.faddr = value;
            s->pwm.file[s->pwm.faddr] = 0;
        } else if (byte == 1) {
            s->pwm.file[s->pwm.faddr] |= value << 8;
        } else if (byte == 2) {
            s->pwm.file[s->pwm.faddr] |= value << 0;
            s->reg = LM832x_GENERAL_ERROR;
        }
        break;
    case LM832x_CMD_PWM_START:
        s->reg = LM832x_GENERAL_ERROR;
        if (!(value & 3) || (value >> 2) > 59) {
            lm_kbd_error(s, ERR_BADPAR);
            break;
        }

        s->pwm.addr[(value & 3) - 1] = value >> 2;
        lm_kbd_pwm_start(s, (value & 3) - 1);
        break;
    case LM832x_CMD_PWM_STOP:
        s->reg = LM832x_GENERAL_ERROR;
        if (!(value & 3)) {
            lm_kbd_error(s, ERR_BADPAR);
            break;
        }

        timer_del(s->pwm.tm[(value & 3) - 1]);
        break;

    case LM832x_GENERAL_ERROR:
        lm_kbd_error(s, ERR_BADPAR);
        break;
    default:
        lm_kbd_error(s, ERR_CMDUNK);
        fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
        break;
    }
}

static int lm_i2c_event(I2CSlave *i2c, enum i2c_event event)
{
    LM823KbdState *s = LM8323(i2c);

    switch (event) {
    case I2C_START_RECV:
    case I2C_START_SEND:
        s->i2c_cycle = 0;
        s->i2c_dir = (event == I2C_START_SEND);
        break;

    default:
        break;
    }

    return 0;
}

static uint8_t lm_i2c_rx(I2CSlave *i2c)
{
    LM823KbdState *s = LM8323(i2c);

    return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
}

static int lm_i2c_tx(I2CSlave *i2c, uint8_t data)
{
    LM823KbdState *s = LM8323(i2c);

    if (!s->i2c_cycle)
        s->reg = data;
    else
        lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
    s->i2c_cycle ++;

    return 0;
}

static int lm_kbd_post_load(void *opaque, int version_id)
{
    LM823KbdState *s = opaque;

    lm_kbd_irq_update(s);
    lm_kbd_gpio_update(s);

    return 0;
}

static const VMStateDescription vmstate_lm_kbd = {
    .name = "LM8323",
    .version_id = 0,
    .minimum_version_id = 0,
    .post_load = lm_kbd_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
        VMSTATE_UINT8(i2c_dir, LM823KbdState),
        VMSTATE_UINT8(i2c_cycle, LM823KbdState),
        VMSTATE_UINT8(reg, LM823KbdState),
        VMSTATE_UINT8(config, LM823KbdState),
        VMSTATE_UINT8(status, LM823KbdState),
        VMSTATE_UINT8(acttime, LM823KbdState),
        VMSTATE_UINT8(error, LM823KbdState),
        VMSTATE_UINT8(clock, LM823KbdState),
        VMSTATE_UINT16(gpio.pull, LM823KbdState),
        VMSTATE_UINT16(gpio.mask, LM823KbdState),
        VMSTATE_UINT16(gpio.dir, LM823KbdState),
        VMSTATE_UINT16(gpio.level, LM823KbdState),
        VMSTATE_UINT8(kbd.dbnctime, LM823KbdState),
        VMSTATE_UINT8(kbd.size, LM823KbdState),
        VMSTATE_UINT8(kbd.start, LM823KbdState),
        VMSTATE_UINT8(kbd.len, LM823KbdState),
        VMSTATE_BUFFER(kbd.fifo, LM823KbdState),
        VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
        VMSTATE_UINT8(pwm.faddr, LM823KbdState),
        VMSTATE_BUFFER(pwm.addr, LM823KbdState),
        VMSTATE_TIMER_PTR_ARRAY(pwm.tm, LM823KbdState, 3),
        VMSTATE_END_OF_LIST()
    }
};


static void lm8323_realize(DeviceState *dev, Error **errp)
{
    LM823KbdState *s = LM8323(dev);

    s->model = 0x8323;
    s->pwm.tm[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm0_tick, s);
    s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s);
    s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s);
    qdev_init_gpio_out(dev, &s->nirq, 1);
}

void lm832x_key_event(DeviceState *dev, int key, int state)
{
    LM823KbdState *s = LM8323(dev);

    if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
        return;

    if (s->kbd.len >= sizeof(s->kbd.fifo)) {
        lm_kbd_error(s, ERR_FIFOOVR);
        return;
    }

    s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] =
            key | (state << 7);

    /* We never set ERR_KEYOVR because we support multiple keys fine.  */
    s->status |= INT_KEYPAD;
    lm_kbd_irq_update(s);
}

static void lm8323_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);

    dc->reset = lm_kbd_reset;
    dc->realize = lm8323_realize;
    k->event = lm_i2c_event;
    k->recv = lm_i2c_rx;
    k->send = lm_i2c_tx;
    dc->vmsd = &vmstate_lm_kbd;
}

static const TypeInfo lm8323_info = {
    .name          = TYPE_LM8323,
    .parent        = TYPE_I2C_SLAVE,
    .instance_size = sizeof(LM823KbdState),
    .class_init    = lm8323_class_init,
};

static void lm832x_register_types(void)
{
    type_register_static(&lm8323_info);
}

type_init(lm832x_register_types)
Commit	Line	Data
1d4e547b AZ	1	/*
	2	* National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	* Written by Andrzej Zaborowski <andrew@openedhand.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 or
	10	* (at your option) version 3 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
fad6cb1a	17	* You should have received a copy of the GNU General Public License along
8167ee88	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
1d4e547b AZ	19	*/
1d4e547b AZ	20
0430891c	21	#include "qemu/osdep.h"
0d09e41a	22	#include "hw/i2c/i2c.h"
64552b6b	23	#include "hw/irq.h"
d6454270	24	#include "migration/vmstate.h"
0b8fa32f	25	#include "qemu/module.h"
1de7afc9	26	#include "qemu/timer.h"
28ecbaee	27	#include "ui/console.h"
db1015e9	28	#include "qom/object.h"
1d4e547b	29
933069eb	30	#define TYPE_LM8323 "lm8323"
db1015e9	31	typedef struct LM823KbdState LM823KbdState;
933069eb AF	32	#define LM8323(obj) OBJECT_CHECK(LM823KbdState, (obj), TYPE_LM8323)
933069eb AF	33
db1015e9	34	struct LM823KbdState {
933069eb AF	35	I2CSlave parent_obj;
933069eb AF	36
e69f0602 JQ	37	uint8_t i2c_dir;
	38	uint8_t i2c_cycle;
	39	uint8_t reg;
1d4e547b AZ	40
	41	qemu_irq nirq;
	42	uint16_t model;
	43
	44	struct {
	45	qemu_irq out[2];
	46	int in[2][2];
	47	} mux;
	48
	49	uint8_t config;
	50	uint8_t status;
	51	uint8_t acttime;
	52	uint8_t error;
	53	uint8_t clock;
	54
	55	struct {
	56	uint16_t pull;
	57	uint16_t mask;
	58	uint16_t dir;
	59	uint16_t level;
	60	qemu_irq out[16];
	61	} gpio;
	62
	63	struct {
	64	uint8_t dbnctime;
	65	uint8_t size;
e69f0602 JQ	66	uint8_t start;
e69f0602 JQ	67	uint8_t len;
1d4e547b AZ	68	uint8_t fifo[16];
	69	} kbd;
	70
	71	struct {
	72	uint16_t file[256];
7d37435b	73	uint8_t faddr;
1d4e547b AZ	74	uint8_t addr[3];
	75	QEMUTimer *tm[3];
	76	} pwm;
db1015e9	77	};
1d4e547b AZ	78
	79	#define INT_KEYPAD (1 << 0)
	80	#define INT_ERROR (1 << 3)
	81	#define INT_NOINIT (1 << 4)
	82	#define INT_PWMEND(n) (1 << (5 + n))
	83
	84	#define ERR_BADPAR (1 << 0)
	85	#define ERR_CMDUNK (1 << 1)
	86	#define ERR_KEYOVR (1 << 2)
	87	#define ERR_FIFOOVR (1 << 6)
	88
bc24a225	89	static void lm_kbd_irq_update(LM823KbdState *s)
1d4e547b AZ	90	{
	91	qemu_set_irq(s->nirq, !s->status);
	92	}
	93
bc24a225	94	static void lm_kbd_gpio_update(LM823KbdState *s)
1d4e547b AZ	95	{
	96	}
	97
f7030d00	98	static void lm_kbd_reset(DeviceState *dev)
1d4e547b	99	{
f7030d00 PMD	100	LM823KbdState *s = LM8323(dev);
f7030d00 PMD	101
1d4e547b AZ	102	s->config = 0x80;
	103	s->status = INT_NOINIT;
	104	s->acttime = 125;
	105	s->kbd.dbnctime = 3;
	106	s->kbd.size = 0x33;
	107	s->clock = 0x08;
	108
	109	lm_kbd_irq_update(s);
	110	lm_kbd_gpio_update(s);
	111	}
	112
bc24a225	113	static void lm_kbd_error(LM823KbdState *s, int err)
1d4e547b AZ	114	{
	115	s->error \|= err;
	116	s->status \|= INT_ERROR;
	117	lm_kbd_irq_update(s);
	118	}
	119
bc24a225	120	static void lm_kbd_pwm_tick(LM823KbdState *s, int line)
1d4e547b AZ	121	{
	122	}
	123
bc24a225	124	static void lm_kbd_pwm_start(LM823KbdState *s, int line)
1d4e547b AZ	125	{
	126	lm_kbd_pwm_tick(s, line);
	127	}
	128
	129	static void lm_kbd_pwm0_tick(void *opaque)
	130	{
	131	lm_kbd_pwm_tick(opaque, 0);
	132	}
	133	static void lm_kbd_pwm1_tick(void *opaque)
	134	{
	135	lm_kbd_pwm_tick(opaque, 1);
	136	}
	137	static void lm_kbd_pwm2_tick(void *opaque)
	138	{
	139	lm_kbd_pwm_tick(opaque, 2);
	140	}
	141
	142	enum {
	143	LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */
	144	LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */
	145	LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */
	146	LM832x_CMD_RESET = 0x83, /* Reset, same as external one */
	147	LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */
	148	LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */
	149	LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */
	150	LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */
	151	LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */
	152	LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */
	153	LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */
	154	LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */
	155	LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */
	156	LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */
	157	LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */
	158	LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */
	159	LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */
	160	LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */
	161	LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */
	162	LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */
	163	LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */
	164	LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */
	165	LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */
e69f0602 JQ	166	LM832x_GENERAL_ERROR = 0xff, /* There was one error.
	167	Previously was represented by -1
	168	This is not a command */
1d4e547b AZ	169	};
	170
	171	#define LM832x_MAX_KPX 8
	172	#define LM832x_MAX_KPY 12
	173
bc24a225	174	static uint8_t lm_kbd_read(LM823KbdState *s, int reg, int byte)
1d4e547b AZ	175	{
	176	int ret;
	177
	178	switch (reg) {
	179	case LM832x_CMD_READ_ID:
	180	ret = 0x0400;
	181	break;
	182
	183	case LM832x_CMD_READ_INT:
	184	ret = s->status;
	185	if (!(s->status & INT_NOINIT)) {
	186	s->status = 0;
	187	lm_kbd_irq_update(s);
	188	}
	189	break;
	190
	191	case LM832x_CMD_READ_PORT_SEL:
	192	ret = s->gpio.dir;
	193	break;
	194	case LM832x_CMD_READ_PORT_STATE:
	195	ret = s->gpio.mask;
	196	break;
	197
	198	case LM832x_CMD_READ_FIFO:
	199	if (s->kbd.len <= 1)
	200	return 0x00;
	201
	202	/* Example response from the two commands after a INT_KEYPAD
	203	* interrupt caused by the key 0x3c being pressed:
	204	* RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	205	* READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	206	* RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
	207	*
	208	* 55 is the code of the key release event serviced in the previous
	209	* interrupt handling.
	210	*
	211	* TODO: find out whether the FIFO is advanced a single character
	212	* before reading every byte or the whole size of the FIFO at the
	213	* last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO
	214	* output in cases where there are more than one event in the FIFO.
	215	* Assume 0xbc and 0x3c events are in the FIFO:
	216	* RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
	217	* READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
	218	* Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
	219	*/
	220	s->kbd.start ++;
	221	s->kbd.start &= sizeof(s->kbd.fifo) - 1;
	222	s->kbd.len --;
	223
	224	return s->kbd.fifo[s->kbd.start];
	225	case LM832x_CMD_RPT_READ_FIFO:
	226	if (byte >= s->kbd.len)
	227	return 0x00;
	228
	229	return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)];
	230
	231	case LM832x_CMD_READ_ERROR:
	232	return s->error;
	233
	234	case LM832x_CMD_READ_ROTATOR:
	235	return 0;
	236
	237	case LM832x_CMD_READ_KEY_SIZE:
	238	return s->kbd.size;
239
240	case LM832x_CMD_READ_CFG:
241	return s->config & 0xf;
242
243	case LM832x_CMD_READ_CLOCK:
244	return (s->clock & 0xfc) \| 2;
245
246	default:
247	lm_kbd_error(s, ERR_CMDUNK);
a89f364a	248	fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
1d4e547b AZ	249	return 0x00;
	250	}
	251
	252	return ret >> (byte << 3);
	253	}
	254
bc24a225	255	static void lm_kbd_write(LM823KbdState *s, int reg, int byte, uint8_t value)
1d4e547b AZ	256	{
	257	switch (reg) {
	258	case LM832x_CMD_WRITE_CFG:
	259	s->config = value;
	260	/* This must be done whenever s->mux.in is updated (never). */
	261	if ((s->config >> 1) & 1) /* MUX1EN */
	262	qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]);
	263	if ((s->config >> 3) & 1) /* MUX2EN */
	264	qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]);
	265	/* TODO: check that this is issued only following the chip reset
	266	* and not in the middle of operation and that it is followed by
	267	* the GPIO ports re-resablishing through WRITE_PORT_SEL and
	268	* WRITE_PORT_STATE (using a timer perhaps) and otherwise output
	269	* warnings. */
	270	s->status = 0;
	271	lm_kbd_irq_update(s);
	272	s->kbd.len = 0;
	273	s->kbd.start = 0;
e69f0602	274	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	275	break;
	276
	277	case LM832x_CMD_RESET:
	278	if (value == 0xaa)
f7030d00	279	lm_kbd_reset(DEVICE(s));
1d4e547b AZ	280	else
1d4e547b AZ	281	lm_kbd_error(s, ERR_BADPAR);
e69f0602	282	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	283	break;
	284
	285	case LM823x_CMD_WRITE_PULL_DOWN:
	286	if (!byte)
	287	s->gpio.pull = value;
	288	else {
	289	s->gpio.pull \|= value << 8;
	290	lm_kbd_gpio_update(s);
e69f0602	291	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	292	}
	293	break;
	294	case LM832x_CMD_WRITE_PORT_SEL:
	295	if (!byte)
	296	s->gpio.dir = value;
	297	else {
	298	s->gpio.dir \|= value << 8;
	299	lm_kbd_gpio_update(s);
e69f0602	300	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	301	}
	302	break;
	303	case LM832x_CMD_WRITE_PORT_STATE:
	304	if (!byte)
	305	s->gpio.mask = value;
	306	else {
	307	s->gpio.mask \|= value << 8;
	308	lm_kbd_gpio_update(s);
e69f0602	309	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	310	}
	311	break;
	312
	313	case LM832x_CMD_SET_ACTIVE:
	314	s->acttime = value;
e69f0602	315	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	316	break;
	317
	318	case LM832x_CMD_SET_DEBOUNCE:
	319	s->kbd.dbnctime = value;
e69f0602	320	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	321	if (!value)
	322	lm_kbd_error(s, ERR_BADPAR);
	323	break;
	324
	325	case LM832x_CMD_SET_KEY_SIZE:
	326	s->kbd.size = value;
e69f0602	327	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	328	if (
	329	(value & 0xf) < 3 \|\| (value & 0xf) > LM832x_MAX_KPY \|\|
	330	(value >> 4) < 3 \|\| (value >> 4) > LM832x_MAX_KPX)
	331	lm_kbd_error(s, ERR_BADPAR);
	332	break;
	333
	334	case LM832x_CMD_WRITE_CLOCK:
	335	s->clock = value;
e69f0602	336	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	337	if ((value & 3) && (value & 3) != 3) {
	338	lm_kbd_error(s, ERR_BADPAR);
	339	fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
a89f364a	340	__func__);
1d4e547b AZ	341	}
	342	/* TODO: Validate that the command is only issued once */
	343	break;
	344
	345	case LM832x_CMD_PWM_WRITE:
	346	if (byte == 0) {
	347	if (!(value & 3) \|\| (value >> 2) > 59) {
	348	lm_kbd_error(s, ERR_BADPAR);
e69f0602	349	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	350	break;
	351	}
	352
	353	s->pwm.faddr = value;
	354	s->pwm.file[s->pwm.faddr] = 0;
	355	} else if (byte == 1) {
	356	s->pwm.file[s->pwm.faddr] \|= value << 8;
	357	} else if (byte == 2) {
	358	s->pwm.file[s->pwm.faddr] \|= value << 0;
e69f0602	359	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	360	}
	361	break;
	362	case LM832x_CMD_PWM_START:
e69f0602	363	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	364	if (!(value & 3) \|\| (value >> 2) > 59) {
	365	lm_kbd_error(s, ERR_BADPAR);
	366	break;
	367	}
	368
	369	s->pwm.addr[(value & 3) - 1] = value >> 2;
	370	lm_kbd_pwm_start(s, (value & 3) - 1);
	371	break;
	372	case LM832x_CMD_PWM_STOP:
e69f0602	373	s->reg = LM832x_GENERAL_ERROR;
1d4e547b AZ	374	if (!(value & 3)) {
	375	lm_kbd_error(s, ERR_BADPAR);
	376	break;
	377	}
	378
bc72ad67	379	timer_del(s->pwm.tm[(value & 3) - 1]);
1d4e547b AZ	380	break;
1d4e547b AZ	381
e69f0602	382	case LM832x_GENERAL_ERROR:
1d4e547b AZ	383	lm_kbd_error(s, ERR_BADPAR);
	384	break;
	385	default:
	386	lm_kbd_error(s, ERR_CMDUNK);
a89f364a	387	fprintf(stderr, "%s: unknown command %02x\n", __func__, reg);
1d4e547b AZ	388	break;
	389	}
	390	}
	391
d307c28c	392	static int lm_i2c_event(I2CSlave *i2c, enum i2c_event event)
1d4e547b	393	{
933069eb	394	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	395
	396	switch (event) {
	397	case I2C_START_RECV:
	398	case I2C_START_SEND:
	399	s->i2c_cycle = 0;
	400	s->i2c_dir = (event == I2C_START_SEND);
	401	break;
	402
	403	default:
	404	break;
	405	}
d307c28c CM	406
d307c28c CM	407	return 0;
1d4e547b AZ	408	}
1d4e547b AZ	409
2ac4c5f4	410	static uint8_t lm_i2c_rx(I2CSlave *i2c)
1d4e547b	411	{
933069eb	412	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	413
	414	return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
	415	}
	416
9e07bdf8	417	static int lm_i2c_tx(I2CSlave *i2c, uint8_t data)
1d4e547b	418	{
933069eb	419	LM823KbdState *s = LM8323(i2c);
1d4e547b AZ	420
	421	if (!s->i2c_cycle)
	422	s->reg = data;
	423	else
	424	lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
	425	s->i2c_cycle ++;
	426
	427	return 0;
	428	}
	429
aa1e3b28	430	static int lm_kbd_post_load(void *opaque, int version_id)
1d4e547b	431	{
aa1e3b28	432	LM823KbdState *s = opaque;
1d4e547b AZ	433
	434	lm_kbd_irq_update(s);
	435	lm_kbd_gpio_update(s);
	436
	437	return 0;
	438	}
	439
aa1e3b28 JQ	440	static const VMStateDescription vmstate_lm_kbd = {
	441	.name = "LM8323",
	442	.version_id = 0,
	443	.minimum_version_id = 0,
aa1e3b28	444	.post_load = lm_kbd_post_load,
8f1e884b	445	.fields = (VMStateField[]) {
933069eb	446	VMSTATE_I2C_SLAVE(parent_obj, LM823KbdState),
aa1e3b28 JQ	447	VMSTATE_UINT8(i2c_dir, LM823KbdState),
	448	VMSTATE_UINT8(i2c_cycle, LM823KbdState),
	449	VMSTATE_UINT8(reg, LM823KbdState),
	450	VMSTATE_UINT8(config, LM823KbdState),
	451	VMSTATE_UINT8(status, LM823KbdState),
	452	VMSTATE_UINT8(acttime, LM823KbdState),
	453	VMSTATE_UINT8(error, LM823KbdState),
	454	VMSTATE_UINT8(clock, LM823KbdState),
	455	VMSTATE_UINT16(gpio.pull, LM823KbdState),
	456	VMSTATE_UINT16(gpio.mask, LM823KbdState),
	457	VMSTATE_UINT16(gpio.dir, LM823KbdState),
	458	VMSTATE_UINT16(gpio.level, LM823KbdState),
	459	VMSTATE_UINT8(kbd.dbnctime, LM823KbdState),
	460	VMSTATE_UINT8(kbd.size, LM823KbdState),
	461	VMSTATE_UINT8(kbd.start, LM823KbdState),
	462	VMSTATE_UINT8(kbd.len, LM823KbdState),
	463	VMSTATE_BUFFER(kbd.fifo, LM823KbdState),
	464	VMSTATE_UINT16_ARRAY(pwm.file, LM823KbdState, 256),
	465	VMSTATE_UINT8(pwm.faddr, LM823KbdState),
	466	VMSTATE_BUFFER(pwm.addr, LM823KbdState),
e720677e	467	VMSTATE_TIMER_PTR_ARRAY(pwm.tm, LM823KbdState, 3),
aa1e3b28 JQ	468	VMSTATE_END_OF_LIST()
	469	}
	470	};
	471
	472
c8c9e103	473	static void lm8323_realize(DeviceState dev, Error *errp)
1d4e547b	474	{
c8c9e103	475	LM823KbdState *s = LM8323(dev);
1d4e547b	476
1d4e547b	477	s->model = 0x8323;
bc72ad67 AB	478	s->pwm.tm[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm0_tick, s);
	479	s->pwm.tm[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm1_tick, s);
	480	s->pwm.tm[2] = timer_new_ns(QEMU_CLOCK_VIRTUAL, lm_kbd_pwm2_tick, s);
c8c9e103	481	qdev_init_gpio_out(dev, &s->nirq, 1);
1d4e547b AZ	482	}
1d4e547b AZ	483
c4f05c8c	484	void lm832x_key_event(DeviceState *dev, int key, int state)
1d4e547b	485	{
933069eb	486	LM823KbdState *s = LM8323(dev);
1d4e547b AZ	487
	488	if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
	489	return;
	490
7442511c BS	491	if (s->kbd.len >= sizeof(s->kbd.fifo)) {
	492	lm_kbd_error(s, ERR_FIFOOVR);
	493	return;
	494	}
1d4e547b AZ	495
	496	s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] =
	497	key \| (state << 7);
	498
	499	/* We never set ERR_KEYOVR because we support multiple keys fine. */
	500	s->status \|= INT_KEYPAD;
	501	lm_kbd_irq_update(s);
	502	}
2d9401aa	503
b5ea9327 AL	504	static void lm8323_class_init(ObjectClass klass, void data)
b5ea9327 AL	505	{
39bffca2	506	DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327 AL	507	I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
b5ea9327 AL	508
f7030d00	509	dc->reset = lm_kbd_reset;
c8c9e103	510	dc->realize = lm8323_realize;
b5ea9327 AL	511	k->event = lm_i2c_event;
	512	k->recv = lm_i2c_rx;
	513	k->send = lm_i2c_tx;
39bffca2	514	dc->vmsd = &vmstate_lm_kbd;
b5ea9327 AL	515	}
b5ea9327 AL	516
8c43a6f0	517	static const TypeInfo lm8323_info = {
933069eb	518	.name = TYPE_LM8323,
39bffca2 AL	519	.parent = TYPE_I2C_SLAVE,
	520	.instance_size = sizeof(LM823KbdState),
	521	.class_init = lm8323_class_init,
2d9401aa PB	522	};
2d9401aa PB	523
83f7d43a	524	static void lm832x_register_types(void)
2d9401aa	525	{
39bffca2	526	type_register_static(&lm8323_info);
2d9401aa PB	527	}
2d9401aa PB	528
83f7d43a	529	type_init(lm832x_register_types)