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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU PC keyboard emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
71e8a915 | 24 | |
0430891c | 25 | #include "qemu/osdep.h" |
c2e846bb | 26 | #include "qemu/log.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
0d09e41a | 28 | #include "hw/isa/isa.h" |
d6454270 | 29 | #include "migration/vmstate.h" |
0d09e41a PB |
30 | #include "hw/i386/pc.h" |
31 | #include "hw/input/ps2.h" | |
64552b6b | 32 | #include "hw/irq.h" |
47973a2d | 33 | #include "hw/input/i8042.h" |
71e8a915 | 34 | #include "sysemu/reset.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
80cabfad | 36 | |
65b182c3 | 37 | #include "trace.h" |
80cabfad | 38 | |
80cabfad FB |
39 | /* Keyboard Controller Commands */ |
40 | #define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ | |
41 | #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ | |
42 | #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ | |
43 | #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ | |
44 | #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ | |
45 | #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ | |
46 | #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ | |
47 | #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ | |
48 | #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ | |
49 | #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ | |
50 | #define KBD_CCMD_READ_INPORT 0xC0 /* read input port */ | |
51 | #define KBD_CCMD_READ_OUTPORT 0xD0 /* read output port */ | |
52 | #define KBD_CCMD_WRITE_OUTPORT 0xD1 /* write output port */ | |
53 | #define KBD_CCMD_WRITE_OBUF 0xD2 | |
54 | #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if | |
7d37435b | 55 | initiated by the auxiliary device */ |
80cabfad FB |
56 | #define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ |
57 | #define KBD_CCMD_DISABLE_A20 0xDD /* HP vectra only ? */ | |
58 | #define KBD_CCMD_ENABLE_A20 0xDF /* HP vectra only ? */ | |
5ccaa4ce BK |
59 | #define KBD_CCMD_PULSE_BITS_3_0 0xF0 /* Pulse bits 3-0 of the output port P2. */ |
60 | #define KBD_CCMD_RESET 0xFE /* Pulse bit 0 of the output port P2 = CPU reset. */ | |
61 | #define KBD_CCMD_NO_OP 0xFF /* Pulse no bits of the output port P2. */ | |
80cabfad FB |
62 | |
63 | /* Keyboard Commands */ | |
64 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ | |
65 | #define KBD_CMD_ECHO 0xEE | |
66 | #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */ | |
67 | #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ | |
68 | #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ | |
69 | #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */ | |
70 | #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */ | |
71 | #define KBD_CMD_RESET 0xFF /* Reset */ | |
72 | ||
73 | /* Keyboard Replies */ | |
74 | #define KBD_REPLY_POR 0xAA /* Power on reset */ | |
75 | #define KBD_REPLY_ACK 0xFA /* Command ACK */ | |
76 | #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ | |
77 | ||
78 | /* Status Register Bits */ | |
79 | #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ | |
80 | #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ | |
81 | #define KBD_STAT_SELFTEST 0x04 /* Self test successful */ | |
82 | #define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ | |
83 | #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ | |
84 | #define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ | |
85 | #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ | |
86 | #define KBD_STAT_PERR 0x80 /* Parity error */ | |
87 | ||
88 | /* Controller Mode Register Bits */ | |
89 | #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ | |
90 | #define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ | |
91 | #define KBD_MODE_SYS 0x04 /* The system flag (?) */ | |
92 | #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ | |
93 | #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ | |
94 | #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ | |
95 | #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ | |
96 | #define KBD_MODE_RFU 0x80 | |
97 | ||
956a3e6b BS |
98 | /* Output Port Bits */ |
99 | #define KBD_OUT_RESET 0x01 /* 1=normal mode, 0=reset */ | |
100 | #define KBD_OUT_A20 0x02 /* x86 only */ | |
101 | #define KBD_OUT_OBF 0x10 /* Keyboard output buffer full */ | |
102 | #define KBD_OUT_MOUSE_OBF 0x20 /* Mouse output buffer full */ | |
103 | ||
d13c0404 PB |
104 | /* OSes typically write 0xdd/0xdf to turn the A20 line off and on. |
105 | * We make the default value of the outport include these four bits, | |
106 | * so that the subsection is rarely necessary. | |
107 | */ | |
108 | #define KBD_OUT_ONES 0xcc | |
109 | ||
80cabfad FB |
110 | /* Mouse Commands */ |
111 | #define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */ | |
112 | #define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */ | |
113 | #define AUX_SET_RES 0xE8 /* Set resolution */ | |
114 | #define AUX_GET_SCALE 0xE9 /* Get scaling factor */ | |
115 | #define AUX_SET_STREAM 0xEA /* Set stream mode */ | |
116 | #define AUX_POLL 0xEB /* Poll */ | |
117 | #define AUX_RESET_WRAP 0xEC /* Reset wrap mode */ | |
118 | #define AUX_SET_WRAP 0xEE /* Set wrap mode */ | |
119 | #define AUX_SET_REMOTE 0xF0 /* Set remote mode */ | |
120 | #define AUX_GET_TYPE 0xF2 /* Get type */ | |
121 | #define AUX_SET_SAMPLE 0xF3 /* Set sample rate */ | |
122 | #define AUX_ENABLE_DEV 0xF4 /* Enable aux device */ | |
123 | #define AUX_DISABLE_DEV 0xF5 /* Disable aux device */ | |
124 | #define AUX_SET_DEFAULT 0xF6 | |
125 | #define AUX_RESET 0xFF /* Reset aux device */ | |
126 | #define AUX_ACK 0xFA /* Command byte ACK. */ | |
127 | ||
128 | #define MOUSE_STATUS_REMOTE 0x40 | |
129 | #define MOUSE_STATUS_ENABLED 0x20 | |
130 | #define MOUSE_STATUS_SCALE21 0x10 | |
131 | ||
daa57963 FB |
132 | #define KBD_PENDING_KBD 1 |
133 | #define KBD_PENDING_AUX 2 | |
80cabfad FB |
134 | |
135 | typedef struct KBDState { | |
80cabfad FB |
136 | uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ |
137 | uint8_t status; | |
138 | uint8_t mode; | |
956a3e6b | 139 | uint8_t outport; |
a28fe7e3 | 140 | bool outport_present; |
daa57963 | 141 | /* Bitmask of devices with data available. */ |
7783e9f0 | 142 | uint8_t pending; |
daa57963 FB |
143 | void *kbd; |
144 | void *mouse; | |
b7678d96 | 145 | |
d537cf6c PB |
146 | qemu_irq irq_kbd; |
147 | qemu_irq irq_mouse; | |
3115b9e2 | 148 | qemu_irq a20_out; |
a8170e5e | 149 | hwaddr mask; |
80cabfad FB |
150 | } KBDState; |
151 | ||
80cabfad FB |
152 | /* update irq and KBD_STAT_[MOUSE_]OBF */ |
153 | /* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be | |
154 | incorrect, but it avoids having to simulate exact delays */ | |
155 | static void kbd_update_irq(KBDState *s) | |
156 | { | |
b7678d96 | 157 | int irq_kbd_level, irq_mouse_level; |
80cabfad | 158 | |
b7678d96 TS |
159 | irq_kbd_level = 0; |
160 | irq_mouse_level = 0; | |
80cabfad | 161 | s->status &= ~(KBD_STAT_OBF | KBD_STAT_MOUSE_OBF); |
956a3e6b | 162 | s->outport &= ~(KBD_OUT_OBF | KBD_OUT_MOUSE_OBF); |
daa57963 | 163 | if (s->pending) { |
80cabfad | 164 | s->status |= KBD_STAT_OBF; |
956a3e6b | 165 | s->outport |= KBD_OUT_OBF; |
b92bb99b | 166 | /* kbd data takes priority over aux data. */ |
daa57963 | 167 | if (s->pending == KBD_PENDING_AUX) { |
80cabfad | 168 | s->status |= KBD_STAT_MOUSE_OBF; |
956a3e6b | 169 | s->outport |= KBD_OUT_MOUSE_OBF; |
80cabfad | 170 | if (s->mode & KBD_MODE_MOUSE_INT) |
b7678d96 | 171 | irq_mouse_level = 1; |
80cabfad | 172 | } else { |
5fafdf24 | 173 | if ((s->mode & KBD_MODE_KBD_INT) && |
80cabfad | 174 | !(s->mode & KBD_MODE_DISABLE_KBD)) |
b7678d96 | 175 | irq_kbd_level = 1; |
80cabfad FB |
176 | } |
177 | } | |
d537cf6c PB |
178 | qemu_set_irq(s->irq_kbd, irq_kbd_level); |
179 | qemu_set_irq(s->irq_mouse, irq_mouse_level); | |
80cabfad FB |
180 | } |
181 | ||
daa57963 | 182 | static void kbd_update_kbd_irq(void *opaque, int level) |
80cabfad | 183 | { |
daa57963 | 184 | KBDState *s = (KBDState *)opaque; |
80cabfad | 185 | |
daa57963 FB |
186 | if (level) |
187 | s->pending |= KBD_PENDING_KBD; | |
80cabfad | 188 | else |
daa57963 | 189 | s->pending &= ~KBD_PENDING_KBD; |
80cabfad FB |
190 | kbd_update_irq(s); |
191 | } | |
192 | ||
daa57963 | 193 | static void kbd_update_aux_irq(void *opaque, int level) |
80cabfad | 194 | { |
daa57963 FB |
195 | KBDState *s = (KBDState *)opaque; |
196 | ||
197 | if (level) | |
198 | s->pending |= KBD_PENDING_AUX; | |
199 | else | |
200 | s->pending &= ~KBD_PENDING_AUX; | |
201 | kbd_update_irq(s); | |
80cabfad FB |
202 | } |
203 | ||
d540bfe0 AG |
204 | static uint64_t kbd_read_status(void *opaque, hwaddr addr, |
205 | unsigned size) | |
80cabfad | 206 | { |
b41a2cd1 | 207 | KBDState *s = opaque; |
80cabfad FB |
208 | int val; |
209 | val = s->status; | |
65b182c3 | 210 | trace_pckbd_kbd_read_status(val); |
80cabfad FB |
211 | return val; |
212 | } | |
213 | ||
daa57963 FB |
214 | static void kbd_queue(KBDState *s, int b, int aux) |
215 | { | |
216 | if (aux) | |
217 | ps2_queue(s->mouse, b); | |
218 | else | |
219 | ps2_queue(s->kbd, b); | |
220 | } | |
221 | ||
4b78a802 | 222 | static void outport_write(KBDState *s, uint32_t val) |
956a3e6b | 223 | { |
65b182c3 | 224 | trace_pckbd_outport_write(val); |
956a3e6b | 225 | s->outport = val; |
3115b9e2 | 226 | qemu_set_irq(s->a20_out, (val >> 1) & 1); |
956a3e6b | 227 | if (!(val & 1)) { |
cf83f140 | 228 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
956a3e6b BS |
229 | } |
230 | } | |
231 | ||
d540bfe0 AG |
232 | static void kbd_write_command(void *opaque, hwaddr addr, |
233 | uint64_t val, unsigned size) | |
80cabfad | 234 | { |
b41a2cd1 | 235 | KBDState *s = opaque; |
80cabfad | 236 | |
65b182c3 | 237 | trace_pckbd_kbd_write_command(val); |
5ccaa4ce BK |
238 | |
239 | /* Bits 3-0 of the output port P2 of the keyboard controller may be pulsed | |
240 | * low for approximately 6 micro seconds. Bits 3-0 of the KBD_CCMD_PULSE | |
241 | * command specify the output port bits to be pulsed. | |
242 | * 0: Bit should be pulsed. 1: Bit should not be modified. | |
243 | * The only useful version of this command is pulsing bit 0, | |
244 | * which does a CPU reset. | |
245 | */ | |
246 | if((val & KBD_CCMD_PULSE_BITS_3_0) == KBD_CCMD_PULSE_BITS_3_0) { | |
247 | if(!(val & 1)) | |
248 | val = KBD_CCMD_RESET; | |
249 | else | |
250 | val = KBD_CCMD_NO_OP; | |
251 | } | |
252 | ||
80cabfad FB |
253 | switch(val) { |
254 | case KBD_CCMD_READ_MODE: | |
889bec69 | 255 | kbd_queue(s, s->mode, 0); |
80cabfad FB |
256 | break; |
257 | case KBD_CCMD_WRITE_MODE: | |
258 | case KBD_CCMD_WRITE_OBUF: | |
259 | case KBD_CCMD_WRITE_AUX_OBUF: | |
260 | case KBD_CCMD_WRITE_MOUSE: | |
261 | case KBD_CCMD_WRITE_OUTPORT: | |
262 | s->write_cmd = val; | |
263 | break; | |
264 | case KBD_CCMD_MOUSE_DISABLE: | |
265 | s->mode |= KBD_MODE_DISABLE_MOUSE; | |
266 | break; | |
267 | case KBD_CCMD_MOUSE_ENABLE: | |
268 | s->mode &= ~KBD_MODE_DISABLE_MOUSE; | |
269 | break; | |
270 | case KBD_CCMD_TEST_MOUSE: | |
271 | kbd_queue(s, 0x00, 0); | |
272 | break; | |
273 | case KBD_CCMD_SELF_TEST: | |
274 | s->status |= KBD_STAT_SELFTEST; | |
275 | kbd_queue(s, 0x55, 0); | |
276 | break; | |
277 | case KBD_CCMD_KBD_TEST: | |
278 | kbd_queue(s, 0x00, 0); | |
279 | break; | |
280 | case KBD_CCMD_KBD_DISABLE: | |
281 | s->mode |= KBD_MODE_DISABLE_KBD; | |
282 | kbd_update_irq(s); | |
283 | break; | |
284 | case KBD_CCMD_KBD_ENABLE: | |
285 | s->mode &= ~KBD_MODE_DISABLE_KBD; | |
286 | kbd_update_irq(s); | |
287 | break; | |
288 | case KBD_CCMD_READ_INPORT: | |
f1b7e0e4 | 289 | kbd_queue(s, 0x80, 0); |
80cabfad FB |
290 | break; |
291 | case KBD_CCMD_READ_OUTPORT: | |
956a3e6b | 292 | kbd_queue(s, s->outport, 0); |
80cabfad | 293 | break; |
80cabfad | 294 | case KBD_CCMD_ENABLE_A20: |
3115b9e2 | 295 | qemu_irq_raise(s->a20_out); |
956a3e6b | 296 | s->outport |= KBD_OUT_A20; |
80cabfad FB |
297 | break; |
298 | case KBD_CCMD_DISABLE_A20: | |
3115b9e2 | 299 | qemu_irq_lower(s->a20_out); |
956a3e6b | 300 | s->outport &= ~KBD_OUT_A20; |
80cabfad | 301 | break; |
80cabfad | 302 | case KBD_CCMD_RESET: |
cf83f140 | 303 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
80cabfad | 304 | break; |
5ccaa4ce BK |
305 | case KBD_CCMD_NO_OP: |
306 | /* ignore that */ | |
80cabfad FB |
307 | break; |
308 | default: | |
c2e846bb PMD |
309 | qemu_log_mask(LOG_GUEST_ERROR, |
310 | "unsupported keyboard cmd=0x%02" PRIx64 "\n", val); | |
80cabfad FB |
311 | break; |
312 | } | |
313 | } | |
314 | ||
d540bfe0 AG |
315 | static uint64_t kbd_read_data(void *opaque, hwaddr addr, |
316 | unsigned size) | |
80cabfad | 317 | { |
63066f4f | 318 | KBDState *s = opaque; |
e41c0f26 | 319 | uint32_t val; |
80cabfad | 320 | |
daa57963 | 321 | if (s->pending == KBD_PENDING_AUX) |
e41c0f26 AZ |
322 | val = ps2_read_data(s->mouse); |
323 | else | |
324 | val = ps2_read_data(s->kbd); | |
80cabfad | 325 | |
65b182c3 | 326 | trace_pckbd_kbd_read_data(val); |
e41c0f26 | 327 | return val; |
80cabfad FB |
328 | } |
329 | ||
d540bfe0 AG |
330 | static void kbd_write_data(void *opaque, hwaddr addr, |
331 | uint64_t val, unsigned size) | |
80cabfad | 332 | { |
b41a2cd1 | 333 | KBDState *s = opaque; |
80cabfad | 334 | |
65b182c3 | 335 | trace_pckbd_kbd_write_data(val); |
80cabfad FB |
336 | |
337 | switch(s->write_cmd) { | |
338 | case 0: | |
daa57963 | 339 | ps2_write_keyboard(s->kbd, val); |
80cabfad FB |
340 | break; |
341 | case KBD_CCMD_WRITE_MODE: | |
342 | s->mode = val; | |
f94f5d71 | 343 | ps2_keyboard_set_translation(s->kbd, (s->mode & KBD_MODE_KCC) != 0); |
daa57963 | 344 | /* ??? */ |
80cabfad FB |
345 | kbd_update_irq(s); |
346 | break; | |
347 | case KBD_CCMD_WRITE_OBUF: | |
348 | kbd_queue(s, val, 0); | |
349 | break; | |
350 | case KBD_CCMD_WRITE_AUX_OBUF: | |
351 | kbd_queue(s, val, 1); | |
352 | break; | |
353 | case KBD_CCMD_WRITE_OUTPORT: | |
4b78a802 | 354 | outport_write(s, val); |
80cabfad FB |
355 | break; |
356 | case KBD_CCMD_WRITE_MOUSE: | |
daa57963 | 357 | ps2_write_mouse(s->mouse, val); |
80cabfad FB |
358 | break; |
359 | default: | |
360 | break; | |
361 | } | |
362 | s->write_cmd = 0; | |
363 | } | |
364 | ||
d7d02e3c | 365 | static void kbd_reset(void *opaque) |
80cabfad | 366 | { |
d7d02e3c | 367 | KBDState *s = opaque; |
80cabfad | 368 | |
80cabfad FB |
369 | s->mode = KBD_MODE_KBD_INT | KBD_MODE_MOUSE_INT; |
370 | s->status = KBD_STAT_CMD | KBD_STAT_UNLOCKED; | |
d13c0404 | 371 | s->outport = KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES; |
a28fe7e3 PD |
372 | s->outport_present = false; |
373 | } | |
374 | ||
375 | static uint8_t kbd_outport_default(KBDState *s) | |
376 | { | |
d13c0404 | 377 | return KBD_OUT_RESET | KBD_OUT_A20 | KBD_OUT_ONES |
a28fe7e3 PD |
378 | | (s->status & KBD_STAT_OBF ? KBD_OUT_OBF : 0) |
379 | | (s->status & KBD_STAT_MOUSE_OBF ? KBD_OUT_MOUSE_OBF : 0); | |
380 | } | |
381 | ||
382 | static int kbd_outport_post_load(void *opaque, int version_id) | |
383 | { | |
384 | KBDState *s = opaque; | |
385 | s->outport_present = true; | |
386 | return 0; | |
387 | } | |
388 | ||
5cd8cada JQ |
389 | static bool kbd_outport_needed(void *opaque) |
390 | { | |
391 | KBDState *s = opaque; | |
392 | return s->outport != kbd_outport_default(s); | |
393 | } | |
394 | ||
a28fe7e3 PD |
395 | static const VMStateDescription vmstate_kbd_outport = { |
396 | .name = "pckbd_outport", | |
397 | .version_id = 1, | |
398 | .minimum_version_id = 1, | |
399 | .post_load = kbd_outport_post_load, | |
5cd8cada | 400 | .needed = kbd_outport_needed, |
a28fe7e3 PD |
401 | .fields = (VMStateField[]) { |
402 | VMSTATE_UINT8(outport, KBDState), | |
403 | VMSTATE_END_OF_LIST() | |
404 | } | |
405 | }; | |
406 | ||
a28fe7e3 PD |
407 | static int kbd_post_load(void *opaque, int version_id) |
408 | { | |
409 | KBDState *s = opaque; | |
410 | if (!s->outport_present) { | |
411 | s->outport = kbd_outport_default(s); | |
412 | } | |
413 | s->outport_present = false; | |
414 | return 0; | |
80cabfad FB |
415 | } |
416 | ||
3c619b59 JQ |
417 | static const VMStateDescription vmstate_kbd = { |
418 | .name = "pckbd", | |
419 | .version_id = 3, | |
420 | .minimum_version_id = 3, | |
a28fe7e3 | 421 | .post_load = kbd_post_load, |
d49805ae | 422 | .fields = (VMStateField[]) { |
3c619b59 JQ |
423 | VMSTATE_UINT8(write_cmd, KBDState), |
424 | VMSTATE_UINT8(status, KBDState), | |
425 | VMSTATE_UINT8(mode, KBDState), | |
426 | VMSTATE_UINT8(pending, KBDState), | |
427 | VMSTATE_END_OF_LIST() | |
a28fe7e3 | 428 | }, |
5cd8cada JQ |
429 | .subsections = (const VMStateDescription*[]) { |
430 | &vmstate_kbd_outport, | |
431 | NULL | |
3c619b59 JQ |
432 | } |
433 | }; | |
675376f2 | 434 | |
b92bb99b | 435 | /* Memory mapped interface */ |
5876503c | 436 | static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size) |
b92bb99b TS |
437 | { |
438 | KBDState *s = opaque; | |
439 | ||
4efbe58f | 440 | if (addr & s->mask) |
d540bfe0 | 441 | return kbd_read_status(s, 0, 1) & 0xff; |
4efbe58f | 442 | else |
d540bfe0 | 443 | return kbd_read_data(s, 0, 1) & 0xff; |
b92bb99b TS |
444 | } |
445 | ||
5876503c PM |
446 | static void kbd_mm_writefn(void *opaque, hwaddr addr, |
447 | uint64_t value, unsigned size) | |
b92bb99b TS |
448 | { |
449 | KBDState *s = opaque; | |
450 | ||
4efbe58f | 451 | if (addr & s->mask) |
d540bfe0 | 452 | kbd_write_command(s, 0, value & 0xff, 1); |
4efbe58f | 453 | else |
d540bfe0 | 454 | kbd_write_data(s, 0, value & 0xff, 1); |
b92bb99b TS |
455 | } |
456 | ||
5876503c | 457 | |
dbff76ac | 458 | static const MemoryRegionOps i8042_mmio_ops = { |
5876503c PM |
459 | .read = kbd_mm_readfn, |
460 | .write = kbd_mm_writefn, | |
461 | .valid.min_access_size = 1, | |
462 | .valid.max_access_size = 4, | |
dbff76ac | 463 | .endianness = DEVICE_NATIVE_ENDIAN, |
b92bb99b TS |
464 | }; |
465 | ||
71db710f | 466 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, |
dbff76ac | 467 | MemoryRegion *region, ram_addr_t size, |
a8170e5e | 468 | hwaddr mask) |
b92bb99b | 469 | { |
7267c094 | 470 | KBDState *s = g_malloc0(sizeof(KBDState)); |
b92bb99b TS |
471 | |
472 | s->irq_kbd = kbd_irq; | |
473 | s->irq_mouse = mouse_irq; | |
4efbe58f | 474 | s->mask = mask; |
b92bb99b | 475 | |
0be71e32 | 476 | vmstate_register(NULL, 0, &vmstate_kbd, s); |
dbff76ac | 477 | |
2c9b15ca | 478 | memory_region_init_io(region, NULL, &i8042_mmio_ops, s, "i8042", size); |
b92bb99b TS |
479 | |
480 | s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); | |
481 | s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); | |
a08d4367 | 482 | qemu_register_reset(kbd_reset, s); |
b92bb99b | 483 | } |
da85ccfb | 484 | |
a2e0b863 AF |
485 | #define I8042(obj) OBJECT_CHECK(ISAKBDState, (obj), TYPE_I8042) |
486 | ||
da85ccfb | 487 | typedef struct ISAKBDState { |
a2e0b863 AF |
488 | ISADevice parent_obj; |
489 | ||
dbff76ac RH |
490 | KBDState kbd; |
491 | MemoryRegion io[2]; | |
da85ccfb GH |
492 | } ISAKBDState; |
493 | ||
956a3e6b BS |
494 | void i8042_isa_mouse_fake_event(void *opaque) |
495 | { | |
496 | ISADevice *dev = opaque; | |
a2e0b863 AF |
497 | ISAKBDState *isa = I8042(dev); |
498 | KBDState *s = &isa->kbd; | |
956a3e6b BS |
499 | |
500 | ps2_mouse_fake_event(s->mouse); | |
501 | } | |
502 | ||
d80fe99d | 503 | void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out) |
956a3e6b | 504 | { |
d80fe99d | 505 | qdev_connect_gpio_out_named(DEVICE(dev), I8042_A20_LINE, 0, a20_out); |
956a3e6b BS |
506 | } |
507 | ||
d05ac8fa | 508 | static const VMStateDescription vmstate_kbd_isa = { |
be73cfe2 JQ |
509 | .name = "pckbd", |
510 | .version_id = 3, | |
511 | .minimum_version_id = 3, | |
d49805ae | 512 | .fields = (VMStateField[]) { |
be73cfe2 JQ |
513 | VMSTATE_STRUCT(kbd, ISAKBDState, 0, vmstate_kbd, KBDState), |
514 | VMSTATE_END_OF_LIST() | |
515 | } | |
516 | }; | |
517 | ||
dbff76ac | 518 | static const MemoryRegionOps i8042_data_ops = { |
d540bfe0 AG |
519 | .read = kbd_read_data, |
520 | .write = kbd_write_data, | |
521 | .impl = { | |
522 | .min_access_size = 1, | |
523 | .max_access_size = 1, | |
524 | }, | |
525 | .endianness = DEVICE_LITTLE_ENDIAN, | |
dbff76ac RH |
526 | }; |
527 | ||
528 | static const MemoryRegionOps i8042_cmd_ops = { | |
d540bfe0 AG |
529 | .read = kbd_read_status, |
530 | .write = kbd_write_command, | |
531 | .impl = { | |
532 | .min_access_size = 1, | |
533 | .max_access_size = 1, | |
534 | }, | |
535 | .endianness = DEVICE_LITTLE_ENDIAN, | |
dbff76ac RH |
536 | }; |
537 | ||
db895a1e | 538 | static void i8042_initfn(Object *obj) |
da85ccfb | 539 | { |
db895a1e | 540 | ISAKBDState *isa_s = I8042(obj); |
dbff76ac | 541 | KBDState *s = &isa_s->kbd; |
da85ccfb | 542 | |
1437c94b PB |
543 | memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s, |
544 | "i8042-data", 1); | |
545 | memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s, | |
546 | "i8042-cmd", 1); | |
3115b9e2 EV |
547 | |
548 | qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1); | |
db895a1e AF |
549 | } |
550 | ||
551 | static void i8042_realizefn(DeviceState *dev, Error **errp) | |
552 | { | |
553 | ISADevice *isadev = ISA_DEVICE(dev); | |
554 | ISAKBDState *isa_s = I8042(dev); | |
555 | KBDState *s = &isa_s->kbd; | |
556 | ||
557 | isa_init_irq(isadev, &s->irq_kbd, 1); | |
558 | isa_init_irq(isadev, &s->irq_mouse, 12); | |
559 | ||
560 | isa_register_ioport(isadev, isa_s->io + 0, 0x60); | |
561 | isa_register_ioport(isadev, isa_s->io + 1, 0x64); | |
da85ccfb GH |
562 | |
563 | s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); | |
564 | s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); | |
da85ccfb GH |
565 | qemu_register_reset(kbd_reset, s); |
566 | } | |
567 | ||
8f04ee08 AL |
568 | static void i8042_class_initfn(ObjectClass *klass, void *data) |
569 | { | |
39bffca2 | 570 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
571 | |
572 | dc->realize = i8042_realizefn; | |
39bffca2 | 573 | dc->vmsd = &vmstate_kbd_isa; |
cbe9ed73 | 574 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
8f04ee08 AL |
575 | } |
576 | ||
8c43a6f0 | 577 | static const TypeInfo i8042_info = { |
a2e0b863 | 578 | .name = TYPE_I8042, |
39bffca2 AL |
579 | .parent = TYPE_ISA_DEVICE, |
580 | .instance_size = sizeof(ISAKBDState), | |
db895a1e | 581 | .instance_init = i8042_initfn, |
39bffca2 | 582 | .class_init = i8042_class_initfn, |
da85ccfb GH |
583 | }; |
584 | ||
83f7d43a | 585 | static void i8042_register_types(void) |
da85ccfb | 586 | { |
39bffca2 | 587 | type_register_static(&i8042_info); |
da85ccfb | 588 | } |
83f7d43a AF |
589 | |
590 | type_init(i8042_register_types) |