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Commit | Line | Data |
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574bbf7b FB |
1 | /* |
2 | * APIC support | |
5fafdf24 | 3 | * |
574bbf7b FB |
4 | * Copyright (c) 2004-2005 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/> |
574bbf7b | 18 | */ |
b6a0aa05 | 19 | #include "qemu/osdep.h" |
33c11879 | 20 | #include "cpu.h" |
1de7afc9 | 21 | #include "qemu/thread.h" |
0d09e41a PB |
22 | #include "hw/i386/apic_internal.h" |
23 | #include "hw/i386/apic.h" | |
24 | #include "hw/i386/ioapic.h" | |
852c27e2 | 25 | #include "hw/intc/i8259.h" |
83c9f4ca | 26 | #include "hw/pci/msi.h" |
1de7afc9 | 27 | #include "qemu/host-utils.h" |
d8023f31 | 28 | #include "trace.h" |
0d09e41a | 29 | #include "hw/i386/apic-msidef.h" |
889211b1 | 30 | #include "qapi/error.h" |
db1015e9 | 31 | #include "qom/object.h" |
574bbf7b | 32 | |
889211b1 | 33 | #define MAX_APICS 255 |
d3e9db93 FB |
34 | #define MAX_APIC_WORDS 8 |
35 | ||
e5ad936b JK |
36 | #define SYNC_FROM_VAPIC 0x1 |
37 | #define SYNC_TO_VAPIC 0x2 | |
38 | #define SYNC_ISR_IRR_TO_VAPIC 0x4 | |
39 | ||
dae01685 | 40 | static APICCommonState *local_apics[MAX_APICS + 1]; |
73822ec8 | 41 | |
927d5a1d WL |
42 | #define TYPE_APIC "apic" |
43 | #define APIC(obj) \ | |
44 | OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC) | |
45 | ||
dae01685 JK |
46 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); |
47 | static void apic_update_irq(APICCommonState *s); | |
610626af AL |
48 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
49 | uint8_t dest, uint8_t dest_mode); | |
d592d303 | 50 | |
3b63c04e | 51 | /* Find first bit starting from msb */ |
edf9735e | 52 | static int apic_fls_bit(uint32_t value) |
3b63c04e AJ |
53 | { |
54 | return 31 - clz32(value); | |
55 | } | |
56 | ||
e95f5491 | 57 | /* Find first bit starting from lsb */ |
edf9735e | 58 | static int apic_ffs_bit(uint32_t value) |
d3e9db93 | 59 | { |
bb7e7293 | 60 | return ctz32(value); |
d3e9db93 FB |
61 | } |
62 | ||
edf9735e | 63 | static inline void apic_reset_bit(uint32_t *tab, int index) |
d3e9db93 FB |
64 | { |
65 | int i, mask; | |
66 | i = index >> 5; | |
67 | mask = 1 << (index & 0x1f); | |
68 | tab[i] &= ~mask; | |
69 | } | |
70 | ||
e5ad936b JK |
71 | /* return -1 if no bit is set */ |
72 | static int get_highest_priority_int(uint32_t *tab) | |
73 | { | |
74 | int i; | |
75 | for (i = 7; i >= 0; i--) { | |
76 | if (tab[i] != 0) { | |
edf9735e | 77 | return i * 32 + apic_fls_bit(tab[i]); |
e5ad936b JK |
78 | } |
79 | } | |
80 | return -1; | |
81 | } | |
82 | ||
83 | static void apic_sync_vapic(APICCommonState *s, int sync_type) | |
84 | { | |
85 | VAPICState vapic_state; | |
86 | size_t length; | |
87 | off_t start; | |
88 | int vector; | |
89 | ||
90 | if (!s->vapic_paddr) { | |
91 | return; | |
92 | } | |
93 | if (sync_type & SYNC_FROM_VAPIC) { | |
eb6282f2 SW |
94 | cpu_physical_memory_read(s->vapic_paddr, &vapic_state, |
95 | sizeof(vapic_state)); | |
e5ad936b JK |
96 | s->tpr = vapic_state.tpr; |
97 | } | |
98 | if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { | |
99 | start = offsetof(VAPICState, isr); | |
100 | length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); | |
101 | ||
102 | if (sync_type & SYNC_TO_VAPIC) { | |
60e82579 | 103 | assert(qemu_cpu_is_self(CPU(s->cpu))); |
e5ad936b JK |
104 | |
105 | vapic_state.tpr = s->tpr; | |
106 | vapic_state.enabled = 1; | |
107 | start = 0; | |
108 | length = sizeof(VAPICState); | |
109 | } | |
110 | ||
111 | vector = get_highest_priority_int(s->isr); | |
112 | if (vector < 0) { | |
113 | vector = 0; | |
114 | } | |
115 | vapic_state.isr = vector & 0xf0; | |
116 | ||
117 | vapic_state.zero = 0; | |
118 | ||
119 | vector = get_highest_priority_int(s->irr); | |
120 | if (vector < 0) { | |
121 | vector = 0; | |
122 | } | |
123 | vapic_state.irr = vector & 0xff; | |
124 | ||
3c8133f9 PM |
125 | address_space_write_rom(&address_space_memory, |
126 | s->vapic_paddr + start, | |
127 | MEMTXATTRS_UNSPECIFIED, | |
128 | ((void *)&vapic_state) + start, length); | |
e5ad936b JK |
129 | } |
130 | } | |
131 | ||
132 | static void apic_vapic_base_update(APICCommonState *s) | |
133 | { | |
134 | apic_sync_vapic(s, SYNC_TO_VAPIC); | |
135 | } | |
136 | ||
dae01685 | 137 | static void apic_local_deliver(APICCommonState *s, int vector) |
a5b38b51 | 138 | { |
a5b38b51 AJ |
139 | uint32_t lvt = s->lvt[vector]; |
140 | int trigger_mode; | |
141 | ||
d8023f31 BS |
142 | trace_apic_local_deliver(vector, (lvt >> 8) & 7); |
143 | ||
a5b38b51 AJ |
144 | if (lvt & APIC_LVT_MASKED) |
145 | return; | |
146 | ||
147 | switch ((lvt >> 8) & 7) { | |
148 | case APIC_DM_SMI: | |
c3affe56 | 149 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); |
a5b38b51 AJ |
150 | break; |
151 | ||
152 | case APIC_DM_NMI: | |
c3affe56 | 153 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); |
a5b38b51 AJ |
154 | break; |
155 | ||
156 | case APIC_DM_EXTINT: | |
c3affe56 | 157 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); |
a5b38b51 AJ |
158 | break; |
159 | ||
160 | case APIC_DM_FIXED: | |
161 | trigger_mode = APIC_TRIGGER_EDGE; | |
162 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && | |
163 | (lvt & APIC_LVT_LEVEL_TRIGGER)) | |
164 | trigger_mode = APIC_TRIGGER_LEVEL; | |
165 | apic_set_irq(s, lvt & 0xff, trigger_mode); | |
166 | } | |
167 | } | |
168 | ||
d3b0c9e9 | 169 | void apic_deliver_pic_intr(DeviceState *dev, int level) |
1a7de94a | 170 | { |
927d5a1d | 171 | APICCommonState *s = APIC(dev); |
92a16d7a | 172 | |
cf6d64bf BS |
173 | if (level) { |
174 | apic_local_deliver(s, APIC_LVT_LINT0); | |
175 | } else { | |
1a7de94a AJ |
176 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
177 | ||
178 | switch ((lvt >> 8) & 7) { | |
179 | case APIC_DM_FIXED: | |
180 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) | |
181 | break; | |
edf9735e | 182 | apic_reset_bit(s->irr, lvt & 0xff); |
1a7de94a AJ |
183 | /* fall through */ |
184 | case APIC_DM_EXTINT: | |
8092cb71 | 185 | apic_update_irq(s); |
1a7de94a AJ |
186 | break; |
187 | } | |
188 | } | |
189 | } | |
190 | ||
dae01685 | 191 | static void apic_external_nmi(APICCommonState *s) |
02c09195 | 192 | { |
02c09195 JK |
193 | apic_local_deliver(s, APIC_LVT_LINT1); |
194 | } | |
195 | ||
d3e9db93 FB |
196 | #define foreach_apic(apic, deliver_bitmask, code) \ |
197 | {\ | |
6d55574a | 198 | int __i, __j;\ |
d3e9db93 | 199 | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
6d55574a | 200 | uint32_t __mask = deliver_bitmask[__i];\ |
d3e9db93 FB |
201 | if (__mask) {\ |
202 | for(__j = 0; __j < 32; __j++) {\ | |
6d55574a | 203 | if (__mask & (1U << __j)) {\ |
d3e9db93 FB |
204 | apic = local_apics[__i * 32 + __j];\ |
205 | if (apic) {\ | |
206 | code;\ | |
207 | }\ | |
208 | }\ | |
209 | }\ | |
210 | }\ | |
211 | }\ | |
212 | } | |
213 | ||
5fafdf24 | 214 | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
1f6f408c | 215 | uint8_t delivery_mode, uint8_t vector_num, |
d592d303 FB |
216 | uint8_t trigger_mode) |
217 | { | |
dae01685 | 218 | APICCommonState *apic_iter; |
d592d303 FB |
219 | |
220 | switch (delivery_mode) { | |
221 | case APIC_DM_LOWPRI: | |
8dd69b8f | 222 | /* XXX: search for focus processor, arbitration */ |
d3e9db93 FB |
223 | { |
224 | int i, d; | |
225 | d = -1; | |
226 | for(i = 0; i < MAX_APIC_WORDS; i++) { | |
227 | if (deliver_bitmask[i]) { | |
edf9735e | 228 | d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); |
d3e9db93 FB |
229 | break; |
230 | } | |
231 | } | |
232 | if (d >= 0) { | |
233 | apic_iter = local_apics[d]; | |
234 | if (apic_iter) { | |
235 | apic_set_irq(apic_iter, vector_num, trigger_mode); | |
236 | } | |
237 | } | |
8dd69b8f | 238 | } |
d3e9db93 | 239 | return; |
8dd69b8f | 240 | |
d592d303 | 241 | case APIC_DM_FIXED: |
d592d303 FB |
242 | break; |
243 | ||
244 | case APIC_DM_SMI: | |
e2eb9d3e | 245 | foreach_apic(apic_iter, deliver_bitmask, |
c3affe56 | 246 | cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) |
60671e58 | 247 | ); |
e2eb9d3e AJ |
248 | return; |
249 | ||
d592d303 | 250 | case APIC_DM_NMI: |
e2eb9d3e | 251 | foreach_apic(apic_iter, deliver_bitmask, |
c3affe56 | 252 | cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) |
60671e58 | 253 | ); |
e2eb9d3e | 254 | return; |
d592d303 FB |
255 | |
256 | case APIC_DM_INIT: | |
257 | /* normal INIT IPI sent to processors */ | |
5fafdf24 | 258 | foreach_apic(apic_iter, deliver_bitmask, |
c3affe56 | 259 | cpu_interrupt(CPU(apic_iter->cpu), |
60671e58 AF |
260 | CPU_INTERRUPT_INIT) |
261 | ); | |
d592d303 | 262 | return; |
3b46e624 | 263 | |
d592d303 | 264 | case APIC_DM_EXTINT: |
b1fc0348 | 265 | /* handled in I/O APIC code */ |
d592d303 FB |
266 | break; |
267 | ||
268 | default: | |
269 | return; | |
270 | } | |
271 | ||
5fafdf24 | 272 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 273 | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
d592d303 | 274 | } |
574bbf7b | 275 | |
1f6f408c JK |
276 | void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, |
277 | uint8_t vector_num, uint8_t trigger_mode) | |
610626af AL |
278 | { |
279 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; | |
280 | ||
d8023f31 | 281 | trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, |
1f6f408c | 282 | trigger_mode); |
d8023f31 | 283 | |
610626af | 284 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
1f6f408c | 285 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
610626af AL |
286 | } |
287 | ||
dae01685 | 288 | static void apic_set_base(APICCommonState *s, uint64_t val) |
574bbf7b | 289 | { |
5fafdf24 | 290 | s->apicbase = (val & 0xfffff000) | |
574bbf7b FB |
291 | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
292 | /* if disabled, cannot be enabled again */ | |
293 | if (!(val & MSR_IA32_APICBASE_ENABLE)) { | |
294 | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; | |
60671e58 | 295 | cpu_clear_apic_feature(&s->cpu->env); |
574bbf7b FB |
296 | s->spurious_vec &= ~APIC_SV_ENABLE; |
297 | } | |
298 | } | |
299 | ||
dae01685 | 300 | static void apic_set_tpr(APICCommonState *s, uint8_t val) |
574bbf7b | 301 | { |
e5ad936b JK |
302 | /* Updates from cr8 are ignored while the VAPIC is active */ |
303 | if (!s->vapic_paddr) { | |
304 | s->tpr = val << 4; | |
305 | apic_update_irq(s); | |
306 | } | |
9230e66e FB |
307 | } |
308 | ||
2cb9f06e SAGDR |
309 | int apic_get_highest_priority_irr(DeviceState *dev) |
310 | { | |
311 | APICCommonState *s; | |
312 | ||
313 | if (!dev) { | |
314 | /* no interrupts */ | |
315 | return -1; | |
316 | } | |
317 | s = APIC_COMMON(dev); | |
318 | return get_highest_priority_int(s->irr); | |
319 | } | |
320 | ||
e5ad936b | 321 | static uint8_t apic_get_tpr(APICCommonState *s) |
d592d303 | 322 | { |
e5ad936b JK |
323 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
324 | return s->tpr >> 4; | |
d592d303 FB |
325 | } |
326 | ||
82a5e042 | 327 | int apic_get_ppr(APICCommonState *s) |
574bbf7b FB |
328 | { |
329 | int tpr, isrv, ppr; | |
330 | ||
331 | tpr = (s->tpr >> 4); | |
332 | isrv = get_highest_priority_int(s->isr); | |
333 | if (isrv < 0) | |
334 | isrv = 0; | |
335 | isrv >>= 4; | |
336 | if (tpr >= isrv) | |
337 | ppr = s->tpr; | |
338 | else | |
339 | ppr = isrv << 4; | |
340 | return ppr; | |
341 | } | |
342 | ||
dae01685 | 343 | static int apic_get_arb_pri(APICCommonState *s) |
d592d303 FB |
344 | { |
345 | /* XXX: arbitration */ | |
346 | return 0; | |
347 | } | |
348 | ||
0fbfbb59 GN |
349 | |
350 | /* | |
351 | * <0 - low prio interrupt, | |
352 | * 0 - no interrupt, | |
353 | * >0 - interrupt number | |
354 | */ | |
dae01685 | 355 | static int apic_irq_pending(APICCommonState *s) |
574bbf7b | 356 | { |
d592d303 | 357 | int irrv, ppr; |
60e68042 PB |
358 | |
359 | if (!(s->spurious_vec & APIC_SV_ENABLE)) { | |
360 | return 0; | |
361 | } | |
362 | ||
574bbf7b | 363 | irrv = get_highest_priority_int(s->irr); |
0fbfbb59 GN |
364 | if (irrv < 0) { |
365 | return 0; | |
366 | } | |
d592d303 | 367 | ppr = apic_get_ppr(s); |
0fbfbb59 GN |
368 | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { |
369 | return -1; | |
370 | } | |
371 | ||
372 | return irrv; | |
373 | } | |
374 | ||
375 | /* signal the CPU if an irq is pending */ | |
dae01685 | 376 | static void apic_update_irq(APICCommonState *s) |
0fbfbb59 | 377 | { |
c3affe56 | 378 | CPUState *cpu; |
be9f8a08 | 379 | DeviceState *dev = (DeviceState *)s; |
60e82579 | 380 | |
c3affe56 | 381 | cpu = CPU(s->cpu); |
60e82579 | 382 | if (!qemu_cpu_is_self(cpu)) { |
c3affe56 | 383 | cpu_interrupt(cpu, CPU_INTERRUPT_POLL); |
5d62c43a | 384 | } else if (apic_irq_pending(s) > 0) { |
c3affe56 | 385 | cpu_interrupt(cpu, CPU_INTERRUPT_HARD); |
be9f8a08 | 386 | } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { |
8092cb71 | 387 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); |
0fbfbb59 | 388 | } |
574bbf7b FB |
389 | } |
390 | ||
d3b0c9e9 | 391 | void apic_poll_irq(DeviceState *dev) |
e5ad936b | 392 | { |
927d5a1d | 393 | APICCommonState *s = APIC(dev); |
e5ad936b JK |
394 | |
395 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
396 | apic_update_irq(s); | |
397 | } | |
398 | ||
dae01685 | 399 | static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) |
574bbf7b | 400 | { |
edf9735e | 401 | apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); |
73822ec8 | 402 | |
edf9735e | 403 | apic_set_bit(s->irr, vector_num); |
574bbf7b | 404 | if (trigger_mode) |
edf9735e | 405 | apic_set_bit(s->tmr, vector_num); |
574bbf7b | 406 | else |
edf9735e | 407 | apic_reset_bit(s->tmr, vector_num); |
e5ad936b JK |
408 | if (s->vapic_paddr) { |
409 | apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); | |
410 | /* | |
411 | * The vcpu thread needs to see the new IRR before we pull its current | |
412 | * TPR value. That way, if we miss a lowering of the TRP, the guest | |
413 | * has the chance to notice the new IRR and poll for IRQs on its own. | |
414 | */ | |
415 | smp_wmb(); | |
416 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
417 | } | |
574bbf7b FB |
418 | apic_update_irq(s); |
419 | } | |
420 | ||
dae01685 | 421 | static void apic_eoi(APICCommonState *s) |
574bbf7b FB |
422 | { |
423 | int isrv; | |
424 | isrv = get_highest_priority_int(s->isr); | |
425 | if (isrv < 0) | |
426 | return; | |
edf9735e MT |
427 | apic_reset_bit(s->isr, isrv); |
428 | if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { | |
0280b571 JK |
429 | ioapic_eoi_broadcast(isrv); |
430 | } | |
e5ad936b | 431 | apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); |
574bbf7b FB |
432 | apic_update_irq(s); |
433 | } | |
434 | ||
678e12cc GN |
435 | static int apic_find_dest(uint8_t dest) |
436 | { | |
dae01685 | 437 | APICCommonState *apic = local_apics[dest]; |
678e12cc GN |
438 | int i; |
439 | ||
440 | if (apic && apic->id == dest) | |
1dfe3282 | 441 | return dest; /* shortcut in case apic->id == local_apics[dest]->id */ |
678e12cc GN |
442 | |
443 | for (i = 0; i < MAX_APICS; i++) { | |
444 | apic = local_apics[i]; | |
7d37435b | 445 | if (apic && apic->id == dest) |
678e12cc | 446 | return i; |
b538e53e AW |
447 | if (!apic) |
448 | break; | |
678e12cc GN |
449 | } |
450 | ||
451 | return -1; | |
452 | } | |
453 | ||
d3e9db93 FB |
454 | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
455 | uint8_t dest, uint8_t dest_mode) | |
d592d303 | 456 | { |
dae01685 | 457 | APICCommonState *apic_iter; |
d3e9db93 | 458 | int i; |
d592d303 FB |
459 | |
460 | if (dest_mode == 0) { | |
d3e9db93 FB |
461 | if (dest == 0xff) { |
462 | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); | |
463 | } else { | |
678e12cc | 464 | int idx = apic_find_dest(dest); |
d3e9db93 | 465 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
678e12cc | 466 | if (idx >= 0) |
edf9735e | 467 | apic_set_bit(deliver_bitmask, idx); |
d3e9db93 | 468 | } |
d592d303 FB |
469 | } else { |
470 | /* XXX: cluster mode */ | |
d3e9db93 FB |
471 | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
472 | for(i = 0; i < MAX_APICS; i++) { | |
473 | apic_iter = local_apics[i]; | |
474 | if (apic_iter) { | |
475 | if (apic_iter->dest_mode == 0xf) { | |
476 | if (dest & apic_iter->log_dest) | |
edf9735e | 477 | apic_set_bit(deliver_bitmask, i); |
d3e9db93 FB |
478 | } else if (apic_iter->dest_mode == 0x0) { |
479 | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && | |
480 | (dest & apic_iter->log_dest & 0x0f)) { | |
edf9735e | 481 | apic_set_bit(deliver_bitmask, i); |
d3e9db93 FB |
482 | } |
483 | } | |
b538e53e AW |
484 | } else { |
485 | break; | |
d3e9db93 | 486 | } |
d592d303 FB |
487 | } |
488 | } | |
d592d303 FB |
489 | } |
490 | ||
dae01685 | 491 | static void apic_startup(APICCommonState *s, int vector_num) |
e0fd8781 | 492 | { |
b09ea7d5 | 493 | s->sipi_vector = vector_num; |
c3affe56 | 494 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
495 | } |
496 | ||
d3b0c9e9 | 497 | void apic_sipi(DeviceState *dev) |
b09ea7d5 | 498 | { |
927d5a1d | 499 | APICCommonState *s = APIC(dev); |
92a16d7a | 500 | |
d8ed887b | 501 | cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); |
b09ea7d5 GN |
502 | |
503 | if (!s->wait_for_sipi) | |
e0fd8781 | 504 | return; |
e9f9d6b1 | 505 | cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); |
b09ea7d5 | 506 | s->wait_for_sipi = 0; |
e0fd8781 FB |
507 | } |
508 | ||
d3b0c9e9 | 509 | static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, |
d592d303 | 510 | uint8_t delivery_mode, uint8_t vector_num, |
1f6f408c | 511 | uint8_t trigger_mode) |
d592d303 | 512 | { |
927d5a1d | 513 | APICCommonState *s = APIC(dev); |
d3e9db93 | 514 | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
d592d303 | 515 | int dest_shorthand = (s->icr[0] >> 18) & 3; |
dae01685 | 516 | APICCommonState *apic_iter; |
d592d303 | 517 | |
e0fd8781 | 518 | switch (dest_shorthand) { |
d3e9db93 FB |
519 | case 0: |
520 | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); | |
521 | break; | |
522 | case 1: | |
523 | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); | |
1dfe3282 | 524 | apic_set_bit(deliver_bitmask, s->id); |
d3e9db93 FB |
525 | break; |
526 | case 2: | |
527 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
528 | break; | |
529 | case 3: | |
530 | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); | |
1dfe3282 | 531 | apic_reset_bit(deliver_bitmask, s->id); |
d3e9db93 | 532 | break; |
e0fd8781 FB |
533 | } |
534 | ||
d592d303 | 535 | switch (delivery_mode) { |
d592d303 FB |
536 | case APIC_DM_INIT: |
537 | { | |
538 | int trig_mode = (s->icr[0] >> 15) & 1; | |
539 | int level = (s->icr[0] >> 14) & 1; | |
540 | if (level == 0 && trig_mode == 1) { | |
5fafdf24 | 541 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 542 | apic_iter->arb_id = apic_iter->id ); |
d592d303 FB |
543 | return; |
544 | } | |
545 | } | |
546 | break; | |
547 | ||
548 | case APIC_DM_SIPI: | |
5fafdf24 | 549 | foreach_apic(apic_iter, deliver_bitmask, |
d3e9db93 | 550 | apic_startup(apic_iter, vector_num) ); |
d592d303 FB |
551 | return; |
552 | } | |
553 | ||
1f6f408c | 554 | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); |
d592d303 FB |
555 | } |
556 | ||
a94820dd JK |
557 | static bool apic_check_pic(APICCommonState *s) |
558 | { | |
be9f8a08 ZG |
559 | DeviceState *dev = (DeviceState *)s; |
560 | ||
561 | if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { | |
a94820dd JK |
562 | return false; |
563 | } | |
be9f8a08 | 564 | apic_deliver_pic_intr(dev, 1); |
a94820dd JK |
565 | return true; |
566 | } | |
567 | ||
d3b0c9e9 | 568 | int apic_get_interrupt(DeviceState *dev) |
574bbf7b | 569 | { |
927d5a1d | 570 | APICCommonState *s = APIC(dev); |
574bbf7b FB |
571 | int intno; |
572 | ||
573 | /* if the APIC is installed or enabled, we let the 8259 handle the | |
574 | IRQs */ | |
575 | if (!s) | |
576 | return -1; | |
577 | if (!(s->spurious_vec & APIC_SV_ENABLE)) | |
578 | return -1; | |
3b46e624 | 579 | |
e5ad936b | 580 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
0fbfbb59 GN |
581 | intno = apic_irq_pending(s); |
582 | ||
5224c88d PB |
583 | /* if there is an interrupt from the 8259, let the caller handle |
584 | * that first since ExtINT interrupts ignore the priority. | |
585 | */ | |
586 | if (intno == 0 || apic_check_pic(s)) { | |
e5ad936b | 587 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
574bbf7b | 588 | return -1; |
0fbfbb59 | 589 | } else if (intno < 0) { |
e5ad936b | 590 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 591 | return s->spurious_vec & 0xff; |
0fbfbb59 | 592 | } |
edf9735e MT |
593 | apic_reset_bit(s->irr, intno); |
594 | apic_set_bit(s->isr, intno); | |
e5ad936b | 595 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
3db3659b | 596 | |
574bbf7b | 597 | apic_update_irq(s); |
3db3659b | 598 | |
574bbf7b FB |
599 | return intno; |
600 | } | |
601 | ||
d3b0c9e9 | 602 | int apic_accept_pic_intr(DeviceState *dev) |
0e21e12b | 603 | { |
927d5a1d | 604 | APICCommonState *s = APIC(dev); |
0e21e12b TS |
605 | uint32_t lvt0; |
606 | ||
607 | if (!s) | |
608 | return -1; | |
609 | ||
610 | lvt0 = s->lvt[APIC_LVT_LINT0]; | |
611 | ||
a5b38b51 AJ |
612 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
613 | (lvt0 & APIC_LVT_MASKED) == 0) | |
78cafff8 | 614 | return isa_pic != NULL; |
0e21e12b TS |
615 | |
616 | return 0; | |
617 | } | |
618 | ||
dae01685 | 619 | static void apic_timer_update(APICCommonState *s, int64_t current_time) |
574bbf7b | 620 | { |
7a380ca3 | 621 | if (apic_next_timer(s, current_time)) { |
bc72ad67 | 622 | timer_mod(s->timer, s->next_time); |
574bbf7b | 623 | } else { |
bc72ad67 | 624 | timer_del(s->timer); |
574bbf7b FB |
625 | } |
626 | } | |
627 | ||
628 | static void apic_timer(void *opaque) | |
629 | { | |
dae01685 | 630 | APICCommonState *s = opaque; |
574bbf7b | 631 | |
cf6d64bf | 632 | apic_local_deliver(s, APIC_LVT_TIMER); |
574bbf7b FB |
633 | apic_timer_update(s, s->next_time); |
634 | } | |
635 | ||
21f80e8f | 636 | static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) |
574bbf7b | 637 | { |
d3b0c9e9 | 638 | DeviceState *dev; |
dae01685 | 639 | APICCommonState *s; |
574bbf7b FB |
640 | uint32_t val; |
641 | int index; | |
642 | ||
21f80e8f PM |
643 | if (size < 4) { |
644 | return 0; | |
645 | } | |
646 | ||
d3b0c9e9 XZ |
647 | dev = cpu_get_current_apic(); |
648 | if (!dev) { | |
574bbf7b | 649 | return 0; |
0e26b7b8 | 650 | } |
927d5a1d | 651 | s = APIC(dev); |
574bbf7b FB |
652 | |
653 | index = (addr >> 4) & 0xff; | |
654 | switch(index) { | |
655 | case 0x02: /* id */ | |
656 | val = s->id << 24; | |
657 | break; | |
658 | case 0x03: /* version */ | |
aa93200b | 659 | val = s->version | ((APIC_LVT_NB - 1) << 16); |
574bbf7b FB |
660 | break; |
661 | case 0x08: | |
e5ad936b JK |
662 | apic_sync_vapic(s, SYNC_FROM_VAPIC); |
663 | if (apic_report_tpr_access) { | |
60671e58 | 664 | cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); |
e5ad936b | 665 | } |
574bbf7b FB |
666 | val = s->tpr; |
667 | break; | |
d592d303 FB |
668 | case 0x09: |
669 | val = apic_get_arb_pri(s); | |
670 | break; | |
574bbf7b FB |
671 | case 0x0a: |
672 | /* ppr */ | |
673 | val = apic_get_ppr(s); | |
674 | break; | |
b237db36 AJ |
675 | case 0x0b: |
676 | val = 0; | |
677 | break; | |
d592d303 FB |
678 | case 0x0d: |
679 | val = s->log_dest << 24; | |
680 | break; | |
681 | case 0x0e: | |
d6c140a7 | 682 | val = (s->dest_mode << 28) | 0xfffffff; |
d592d303 | 683 | break; |
574bbf7b FB |
684 | case 0x0f: |
685 | val = s->spurious_vec; | |
686 | break; | |
687 | case 0x10 ... 0x17: | |
688 | val = s->isr[index & 7]; | |
689 | break; | |
690 | case 0x18 ... 0x1f: | |
691 | val = s->tmr[index & 7]; | |
692 | break; | |
693 | case 0x20 ... 0x27: | |
694 | val = s->irr[index & 7]; | |
695 | break; | |
696 | case 0x28: | |
697 | val = s->esr; | |
698 | break; | |
574bbf7b FB |
699 | case 0x30: |
700 | case 0x31: | |
701 | val = s->icr[index & 1]; | |
702 | break; | |
e0fd8781 FB |
703 | case 0x32 ... 0x37: |
704 | val = s->lvt[index - 0x32]; | |
705 | break; | |
574bbf7b FB |
706 | case 0x38: |
707 | val = s->initial_count; | |
708 | break; | |
709 | case 0x39: | |
710 | val = apic_get_current_count(s); | |
711 | break; | |
712 | case 0x3e: | |
713 | val = s->divide_conf; | |
714 | break; | |
715 | default: | |
a22bf99c | 716 | s->esr |= APIC_ESR_ILLEGAL_ADDRESS; |
574bbf7b FB |
717 | val = 0; |
718 | break; | |
719 | } | |
d8023f31 | 720 | trace_apic_mem_readl(addr, val); |
574bbf7b FB |
721 | return val; |
722 | } | |
723 | ||
267ee357 | 724 | static void apic_send_msi(MSIMessage *msi) |
54c96da7 | 725 | { |
267ee357 RK |
726 | uint64_t addr = msi->address; |
727 | uint32_t data = msi->data; | |
54c96da7 MT |
728 | uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
729 | uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
730 | uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; | |
731 | uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; | |
732 | uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; | |
733 | /* XXX: Ignore redirection hint. */ | |
1f6f408c | 734 | apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); |
54c96da7 MT |
735 | } |
736 | ||
21f80e8f PM |
737 | static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, |
738 | unsigned size) | |
574bbf7b | 739 | { |
d3b0c9e9 | 740 | DeviceState *dev; |
dae01685 | 741 | APICCommonState *s; |
54c96da7 | 742 | int index = (addr >> 4) & 0xff; |
21f80e8f PM |
743 | |
744 | if (size < 4) { | |
745 | return; | |
746 | } | |
747 | ||
54c96da7 MT |
748 | if (addr > 0xfff || !index) { |
749 | /* MSI and MMIO APIC are at the same memory location, | |
750 | * but actually not on the global bus: MSI is on PCI bus | |
751 | * APIC is connected directly to the CPU. | |
752 | * Mapping them on the global bus happens to work because | |
753 | * MSI registers are reserved in APIC MMIO and vice versa. */ | |
267ee357 RK |
754 | MSIMessage msi = { .address = addr, .data = val }; |
755 | apic_send_msi(&msi); | |
54c96da7 MT |
756 | return; |
757 | } | |
574bbf7b | 758 | |
d3b0c9e9 XZ |
759 | dev = cpu_get_current_apic(); |
760 | if (!dev) { | |
574bbf7b | 761 | return; |
0e26b7b8 | 762 | } |
927d5a1d | 763 | s = APIC(dev); |
574bbf7b | 764 | |
d8023f31 | 765 | trace_apic_mem_writel(addr, val); |
574bbf7b | 766 | |
574bbf7b FB |
767 | switch(index) { |
768 | case 0x02: | |
769 | s->id = (val >> 24); | |
770 | break; | |
e0fd8781 FB |
771 | case 0x03: |
772 | break; | |
574bbf7b | 773 | case 0x08: |
e5ad936b | 774 | if (apic_report_tpr_access) { |
60671e58 | 775 | cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); |
e5ad936b | 776 | } |
574bbf7b | 777 | s->tpr = val; |
e5ad936b | 778 | apic_sync_vapic(s, SYNC_TO_VAPIC); |
d592d303 | 779 | apic_update_irq(s); |
574bbf7b | 780 | break; |
e0fd8781 FB |
781 | case 0x09: |
782 | case 0x0a: | |
783 | break; | |
574bbf7b FB |
784 | case 0x0b: /* EOI */ |
785 | apic_eoi(s); | |
786 | break; | |
d592d303 FB |
787 | case 0x0d: |
788 | s->log_dest = val >> 24; | |
789 | break; | |
790 | case 0x0e: | |
791 | s->dest_mode = val >> 28; | |
792 | break; | |
574bbf7b FB |
793 | case 0x0f: |
794 | s->spurious_vec = val & 0x1ff; | |
d592d303 | 795 | apic_update_irq(s); |
574bbf7b | 796 | break; |
e0fd8781 FB |
797 | case 0x10 ... 0x17: |
798 | case 0x18 ... 0x1f: | |
799 | case 0x20 ... 0x27: | |
800 | case 0x28: | |
801 | break; | |
574bbf7b | 802 | case 0x30: |
d592d303 | 803 | s->icr[0] = val; |
d3b0c9e9 | 804 | apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
d592d303 | 805 | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
1f6f408c | 806 | (s->icr[0] >> 15) & 1); |
d592d303 | 807 | break; |
574bbf7b | 808 | case 0x31: |
d592d303 | 809 | s->icr[1] = val; |
574bbf7b FB |
810 | break; |
811 | case 0x32 ... 0x37: | |
812 | { | |
813 | int n = index - 0x32; | |
814 | s->lvt[n] = val; | |
a94820dd | 815 | if (n == APIC_LVT_TIMER) { |
bc72ad67 | 816 | apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
a94820dd JK |
817 | } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { |
818 | apic_update_irq(s); | |
819 | } | |
574bbf7b FB |
820 | } |
821 | break; | |
822 | case 0x38: | |
823 | s->initial_count = val; | |
bc72ad67 | 824 | s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
574bbf7b FB |
825 | apic_timer_update(s, s->initial_count_load_time); |
826 | break; | |
e0fd8781 FB |
827 | case 0x39: |
828 | break; | |
574bbf7b FB |
829 | case 0x3e: |
830 | { | |
831 | int v; | |
832 | s->divide_conf = val & 0xb; | |
833 | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); | |
834 | s->count_shift = (v + 1) & 7; | |
835 | } | |
836 | break; | |
837 | default: | |
a22bf99c | 838 | s->esr |= APIC_ESR_ILLEGAL_ADDRESS; |
574bbf7b FB |
839 | break; |
840 | } | |
841 | } | |
842 | ||
e5ad936b JK |
843 | static void apic_pre_save(APICCommonState *s) |
844 | { | |
845 | apic_sync_vapic(s, SYNC_FROM_VAPIC); | |
846 | } | |
847 | ||
7a380ca3 JK |
848 | static void apic_post_load(APICCommonState *s) |
849 | { | |
850 | if (s->timer_expiry != -1) { | |
bc72ad67 | 851 | timer_mod(s->timer, s->timer_expiry); |
7a380ca3 | 852 | } else { |
bc72ad67 | 853 | timer_del(s->timer); |
7a380ca3 JK |
854 | } |
855 | } | |
856 | ||
312b4234 | 857 | static const MemoryRegionOps apic_io_ops = { |
21f80e8f PM |
858 | .read = apic_mem_read, |
859 | .write = apic_mem_write, | |
860 | .impl.min_access_size = 1, | |
861 | .impl.max_access_size = 4, | |
862 | .valid.min_access_size = 1, | |
863 | .valid.max_access_size = 4, | |
312b4234 | 864 | .endianness = DEVICE_NATIVE_ENDIAN, |
574bbf7b FB |
865 | }; |
866 | ||
ff6986ce | 867 | static void apic_realize(DeviceState *dev, Error **errp) |
8546b099 | 868 | { |
927d5a1d | 869 | APICCommonState *s = APIC(dev); |
889211b1 | 870 | |
1dfe3282 IM |
871 | if (s->id >= MAX_APICS) { |
872 | error_setg(errp, "%s initialization failed. APIC ID %d is invalid", | |
873 | object_get_typename(OBJECT(dev)), s->id); | |
889211b1 IM |
874 | return; |
875 | } | |
ff6986ce | 876 | |
1437c94b | 877 | memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", |
baaeda08 | 878 | APIC_SPACE_SIZE); |
8546b099 | 879 | |
bc72ad67 | 880 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); |
1dfe3282 | 881 | local_apics[s->id] = s; |
08a82ac0 | 882 | |
226419d6 | 883 | msi_nonbroken = true; |
8546b099 BS |
884 | } |
885 | ||
b69c3c21 | 886 | static void apic_unrealize(DeviceState *dev) |
9c156f9d | 887 | { |
927d5a1d | 888 | APICCommonState *s = APIC(dev); |
9c156f9d IM |
889 | |
890 | timer_del(s->timer); | |
891 | timer_free(s->timer); | |
892 | local_apics[s->id] = NULL; | |
893 | } | |
894 | ||
999e12bb AL |
895 | static void apic_class_init(ObjectClass *klass, void *data) |
896 | { | |
897 | APICCommonClass *k = APIC_COMMON_CLASS(klass); | |
898 | ||
ff6986ce | 899 | k->realize = apic_realize; |
9c156f9d | 900 | k->unrealize = apic_unrealize; |
999e12bb AL |
901 | k->set_base = apic_set_base; |
902 | k->set_tpr = apic_set_tpr; | |
e5ad936b JK |
903 | k->get_tpr = apic_get_tpr; |
904 | k->vapic_base_update = apic_vapic_base_update; | |
999e12bb | 905 | k->external_nmi = apic_external_nmi; |
e5ad936b | 906 | k->pre_save = apic_pre_save; |
999e12bb | 907 | k->post_load = apic_post_load; |
267ee357 | 908 | k->send_msi = apic_send_msi; |
999e12bb AL |
909 | } |
910 | ||
8c43a6f0 | 911 | static const TypeInfo apic_info = { |
927d5a1d | 912 | .name = TYPE_APIC, |
39bffca2 AL |
913 | .instance_size = sizeof(APICCommonState), |
914 | .parent = TYPE_APIC_COMMON, | |
915 | .class_init = apic_class_init, | |
8546b099 BS |
916 | }; |
917 | ||
83f7d43a | 918 | static void apic_register_types(void) |
8546b099 | 919 | { |
39bffca2 | 920 | type_register_static(&apic_info); |
8546b099 BS |
921 | } |
922 | ||
83f7d43a | 923 | type_init(apic_register_types) |