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Commit | Line | Data |
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5856de80 TS |
1 | /* |
2 | * QEMU Malta board support | |
3 | * | |
4 | * Copyright (c) 2006 Aurelien Jarno | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
c684822a | 25 | #include "qemu/osdep.h" |
be01029e | 26 | #include "qemu/units.h" |
4771d756 PB |
27 | #include "qemu-common.h" |
28 | #include "cpu.h" | |
fff123b8 | 29 | #include "hw/southbridge/piix.h" |
7313b1f2 | 30 | #include "hw/isa/superio.h" |
0d09e41a | 31 | #include "hw/char/serial.h" |
1422e32d | 32 | #include "net/net.h" |
83c9f4ca | 33 | #include "hw/boards.h" |
93198b6c | 34 | #include "hw/i2c/smbus_eeprom.h" |
0d09e41a PB |
35 | #include "hw/block/flash.h" |
36 | #include "hw/mips/mips.h" | |
37 | #include "hw/mips/cpudevs.h" | |
83c9f4ca | 38 | #include "hw/pci/pci.h" |
9c17d615 PB |
39 | #include "sysemu/sysemu.h" |
40 | #include "sysemu/arch_init.h" | |
1de7afc9 | 41 | #include "qemu/log.h" |
0d09e41a | 42 | #include "hw/mips/bios.h" |
83c9f4ca | 43 | #include "hw/ide.h" |
64552b6b | 44 | #include "hw/irq.h" |
83c9f4ca | 45 | #include "hw/loader.h" |
ca20cf32 | 46 | #include "elf.h" |
022c62cb | 47 | #include "exec/address-spaces.h" |
db1015e9 | 48 | #include "qom/object.h" |
83c9f4ca | 49 | #include "hw/sysbus.h" /* SysBusDevice */ |
02bccc77 | 50 | #include "qemu/host-utils.h" |
2c57bd9b | 51 | #include "sysemu/qtest.h" |
71e8a915 | 52 | #include "sysemu/reset.h" |
54d31236 | 53 | #include "sysemu/runstate.h" |
e688df6b | 54 | #include "qapi/error.h" |
2e985fe0 | 55 | #include "qemu/error-report.h" |
6007523a | 56 | #include "hw/misc/empty_slot.h" |
b0311811 | 57 | #include "sysemu/kvm.h" |
f1672e6f | 58 | #include "hw/semihosting/semihost.h" |
bff384a4 | 59 | #include "hw/mips/cps.h" |
5856de80 | 60 | |
94818443 AM |
61 | #define ENVP_ADDR 0x80002000l |
62 | #define ENVP_NB_ENTRIES 16 | |
63 | #define ENVP_ENTRY_SIZE 256 | |
5856de80 | 64 | |
03a1a8e1 | 65 | /* Hardware addresses */ |
94818443 AM |
66 | #define FLASH_ADDRESS 0x1e000000ULL |
67 | #define FPGA_ADDRESS 0x1f000000ULL | |
68 | #define RESET_ADDRESS 0x1fc00000ULL | |
03a1a8e1 | 69 | |
94818443 | 70 | #define FLASH_SIZE 0x400000 |
03a1a8e1 | 71 | |
94818443 | 72 | #define MAX_IDE_BUS 2 |
e4bcb14c | 73 | |
5856de80 | 74 | typedef struct { |
ea85df72 AK |
75 | MemoryRegion iomem; |
76 | MemoryRegion iomem_lo; /* 0 - 0x900 */ | |
77 | MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */ | |
5856de80 TS |
78 | uint32_t leds; |
79 | uint32_t brk; | |
80 | uint32_t gpout; | |
130751ee | 81 | uint32_t i2cin; |
5856de80 TS |
82 | uint32_t i2coe; |
83 | uint32_t i2cout; | |
84 | uint32_t i2csel; | |
32a6ebec | 85 | CharBackend display; |
5856de80 | 86 | char display_text[9]; |
490a9d9b | 87 | SerialMM *uart; |
9850b05d | 88 | bool display_inited; |
5856de80 TS |
89 | } MaltaFPGAState; |
90 | ||
cba5cb67 | 91 | #define TYPE_MIPS_MALTA "mips-malta" |
8063396b | 92 | OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) |
cba5cb67 | 93 | |
db1015e9 | 94 | struct MaltaState { |
cba5cb67 AF |
95 | SysBusDevice parent_obj; |
96 | ||
2d5fac80 | 97 | MIPSCPSState cps; |
078778c5 | 98 | qemu_irq i8259[ISA_NUM_IRQS]; |
db1015e9 | 99 | }; |
e9b40fd3 | 100 | |
7df526e3 | 101 | static struct _loaderparams { |
71c199c8 | 102 | int ram_size, ram_low_size; |
7df526e3 TS |
103 | const char *kernel_filename; |
104 | const char *kernel_cmdline; | |
105 | const char *initrd_filename; | |
106 | } loaderparams; | |
107 | ||
5856de80 TS |
108 | /* Malta FPGA */ |
109 | static void malta_fpga_update_display(void *opaque) | |
110 | { | |
111 | char leds_text[9]; | |
112 | int i; | |
113 | MaltaFPGAState *s = opaque; | |
114 | ||
07cf0ba0 | 115 | for (i = 7 ; i >= 0 ; i--) { |
94818443 | 116 | if (s->leds & (1 << i)) { |
07cf0ba0 | 117 | leds_text[i] = '#'; |
94818443 | 118 | } else { |
07cf0ba0 | 119 | leds_text[i] = ' '; |
94818443 | 120 | } |
87ee1669 | 121 | } |
07cf0ba0 TS |
122 | leds_text[8] = '\0'; |
123 | ||
5345fdb4 | 124 | qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", |
32a6ebec | 125 | leds_text); |
5345fdb4 | 126 | qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", |
32a6ebec | 127 | s->display_text); |
5856de80 TS |
128 | } |
129 | ||
130751ee TS |
130 | /* |
131 | * EEPROM 24C01 / 24C02 emulation. | |
132 | * | |
133 | * Emulation for serial EEPROMs: | |
134 | * 24C01 - 1024 bit (128 x 8) | |
135 | * 24C02 - 2048 bit (256 x 8) | |
136 | * | |
137 | * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02. | |
138 | */ | |
139 | ||
130751ee | 140 | #if defined(DEBUG) |
dbd07eda FB |
141 | # define logout(fmt, ...) \ |
142 | fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__) | |
130751ee | 143 | #else |
001faf32 | 144 | # define logout(fmt, ...) ((void)0) |
130751ee TS |
145 | #endif |
146 | ||
c227f099 | 147 | struct _eeprom24c0x_t { |
130751ee TS |
148 | uint8_t tick; |
149 | uint8_t address; | |
150 | uint8_t command; | |
151 | uint8_t ack; | |
152 | uint8_t scl; | |
153 | uint8_t sda; | |
154 | uint8_t data; | |
94818443 | 155 | /* uint16_t size; */ |
130751ee TS |
156 | uint8_t contents[256]; |
157 | }; | |
158 | ||
c227f099 | 159 | typedef struct _eeprom24c0x_t eeprom24c0x_t; |
130751ee | 160 | |
35c64807 | 161 | static eeprom24c0x_t spd_eeprom = { |
284b08f1 | 162 | .contents = { |
94818443 AM |
163 | /* 00000000: */ |
164 | 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00, | |
165 | /* 00000008: */ | |
166 | 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01, | |
167 | /* 00000010: */ | |
168 | 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, | |
169 | /* 00000018: */ | |
170 | 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF, | |
171 | /* 00000020: */ | |
172 | 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, | |
173 | /* 00000028: */ | |
174 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
175 | /* 00000030: */ | |
176 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
177 | /* 00000038: */ | |
178 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0, | |
179 | /* 00000040: */ | |
180 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
181 | /* 00000048: */ | |
182 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
183 | /* 00000050: */ | |
184 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
185 | /* 00000058: */ | |
186 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
187 | /* 00000060: */ | |
188 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
189 | /* 00000068: */ | |
190 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
191 | /* 00000070: */ | |
192 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
193 | /* 00000078: */ | |
194 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4, | |
130751ee TS |
195 | }, |
196 | }; | |
197 | ||
35c64807 | 198 | static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size) |
02bccc77 PB |
199 | { |
200 | enum { SDR = 0x4, DDR2 = 0x8 } type; | |
35c64807 | 201 | uint8_t *spd = spd_eeprom.contents; |
02bccc77 PB |
202 | uint8_t nbanks = 0; |
203 | uint16_t density = 0; | |
204 | int i; | |
205 | ||
206 | /* work in terms of MB */ | |
be01029e | 207 | ram_size /= MiB; |
02bccc77 PB |
208 | |
209 | while ((ram_size >= 4) && (nbanks <= 2)) { | |
210 | int sz_log2 = MIN(31 - clz32(ram_size), 14); | |
211 | nbanks++; | |
212 | density |= 1 << (sz_log2 - 2); | |
213 | ram_size -= 1 << sz_log2; | |
214 | } | |
215 | ||
216 | /* split to 2 banks if possible */ | |
217 | if ((nbanks == 1) && (density > 1)) { | |
218 | nbanks++; | |
219 | density >>= 1; | |
220 | } | |
221 | ||
222 | if (density & 0xff00) { | |
223 | density = (density & 0xe0) | ((density >> 8) & 0x1f); | |
224 | type = DDR2; | |
225 | } else if (!(density & 0x1f)) { | |
226 | type = DDR2; | |
227 | } else { | |
228 | type = SDR; | |
229 | } | |
230 | ||
231 | if (ram_size) { | |
b62e39b4 AF |
232 | warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB" |
233 | " of SDRAM", ram_size); | |
02bccc77 PB |
234 | } |
235 | ||
236 | /* fill in SPD memory information */ | |
237 | spd[2] = type; | |
238 | spd[5] = nbanks; | |
239 | spd[31] = density; | |
240 | ||
241 | /* checksum */ | |
242 | spd[63] = 0; | |
243 | for (i = 0; i < 63; i++) { | |
244 | spd[63] += spd[i]; | |
245 | } | |
35c64807 PB |
246 | |
247 | /* copy for SMBUS */ | |
248 | memcpy(eeprom, spd, sizeof(spd_eeprom.contents)); | |
249 | } | |
250 | ||
251 | static void generate_eeprom_serial(uint8_t *eeprom) | |
252 | { | |
253 | int i, pos = 0; | |
254 | uint8_t mac[6] = { 0x00 }; | |
255 | uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 }; | |
256 | ||
257 | /* version */ | |
258 | eeprom[pos++] = 0x01; | |
259 | ||
260 | /* count */ | |
261 | eeprom[pos++] = 0x02; | |
262 | ||
263 | /* MAC address */ | |
264 | eeprom[pos++] = 0x01; /* MAC */ | |
265 | eeprom[pos++] = 0x06; /* length */ | |
266 | memcpy(&eeprom[pos], mac, sizeof(mac)); | |
267 | pos += sizeof(mac); | |
268 | ||
269 | /* serial number */ | |
270 | eeprom[pos++] = 0x02; /* serial */ | |
271 | eeprom[pos++] = 0x05; /* length */ | |
272 | memcpy(&eeprom[pos], sn, sizeof(sn)); | |
273 | pos += sizeof(sn); | |
274 | ||
275 | /* checksum */ | |
276 | eeprom[pos] = 0; | |
277 | for (i = 0; i < pos; i++) { | |
278 | eeprom[pos] += eeprom[i]; | |
279 | } | |
02bccc77 PB |
280 | } |
281 | ||
35c64807 | 282 | static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom) |
130751ee TS |
283 | { |
284 | logout("%u: scl = %u, sda = %u, data = 0x%02x\n", | |
35c64807 PB |
285 | eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data); |
286 | return eeprom->sda; | |
130751ee TS |
287 | } |
288 | ||
35c64807 | 289 | static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda) |
130751ee | 290 | { |
35c64807 | 291 | if (eeprom->scl && scl && (eeprom->sda != sda)) { |
130751ee | 292 | logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n", |
35c64807 PB |
293 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda, |
294 | sda ? "stop" : "start"); | |
130751ee | 295 | if (!sda) { |
35c64807 PB |
296 | eeprom->tick = 1; |
297 | eeprom->command = 0; | |
130751ee | 298 | } |
35c64807 | 299 | } else if (eeprom->tick == 0 && !eeprom->ack) { |
130751ee TS |
300 | /* Waiting for start. */ |
301 | logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n", | |
35c64807 PB |
302 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
303 | } else if (!eeprom->scl && scl) { | |
130751ee | 304 | logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n", |
35c64807 PB |
305 | eeprom->tick, eeprom->scl, scl, eeprom->sda, sda); |
306 | if (eeprom->ack) { | |
130751ee TS |
307 | logout("\ti2c ack bit = 0\n"); |
308 | sda = 0; | |
35c64807 PB |
309 | eeprom->ack = 0; |
310 | } else if (eeprom->sda == sda) { | |
130751ee TS |
311 | uint8_t bit = (sda != 0); |
312 | logout("\ti2c bit = %d\n", bit); | |
35c64807 PB |
313 | if (eeprom->tick < 9) { |
314 | eeprom->command <<= 1; | |
315 | eeprom->command += bit; | |
316 | eeprom->tick++; | |
317 | if (eeprom->tick == 9) { | |
318 | logout("\tcommand 0x%04x, %s\n", eeprom->command, | |
319 | bit ? "read" : "write"); | |
320 | eeprom->ack = 1; | |
130751ee | 321 | } |
35c64807 PB |
322 | } else if (eeprom->tick < 17) { |
323 | if (eeprom->command & 1) { | |
324 | sda = ((eeprom->data & 0x80) != 0); | |
130751ee | 325 | } |
35c64807 PB |
326 | eeprom->address <<= 1; |
327 | eeprom->address += bit; | |
328 | eeprom->tick++; | |
329 | eeprom->data <<= 1; | |
330 | if (eeprom->tick == 17) { | |
331 | eeprom->data = eeprom->contents[eeprom->address]; | |
332 | logout("\taddress 0x%04x, data 0x%02x\n", | |
333 | eeprom->address, eeprom->data); | |
334 | eeprom->ack = 1; | |
335 | eeprom->tick = 0; | |
130751ee | 336 | } |
35c64807 | 337 | } else if (eeprom->tick >= 17) { |
130751ee TS |
338 | sda = 0; |
339 | } | |
340 | } else { | |
341 | logout("\tsda changed with raising scl\n"); | |
342 | } | |
343 | } else { | |
35c64807 PB |
344 | logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl, |
345 | scl, eeprom->sda, sda); | |
130751ee | 346 | } |
35c64807 PB |
347 | eeprom->scl = scl; |
348 | eeprom->sda = sda; | |
130751ee TS |
349 | } |
350 | ||
a8170e5e | 351 | static uint64_t malta_fpga_read(void *opaque, hwaddr addr, |
ea85df72 | 352 | unsigned size) |
5856de80 TS |
353 | { |
354 | MaltaFPGAState *s = opaque; | |
355 | uint32_t val = 0; | |
356 | uint32_t saddr; | |
357 | ||
358 | saddr = (addr & 0xfffff); | |
359 | ||
360 | switch (saddr) { | |
361 | ||
362 | /* SWITCH Register */ | |
363 | case 0x00200: | |
94818443 | 364 | val = 0x00000000; |
593c0d10 | 365 | break; |
5856de80 TS |
366 | |
367 | /* STATUS Register */ | |
368 | case 0x00208: | |
369 | #ifdef TARGET_WORDS_BIGENDIAN | |
370 | val = 0x00000012; | |
371 | #else | |
372 | val = 0x00000010; | |
373 | #endif | |
374 | break; | |
375 | ||
376 | /* JMPRS Register */ | |
377 | case 0x00210: | |
378 | val = 0x00; | |
379 | break; | |
380 | ||
381 | /* LEDBAR Register */ | |
382 | case 0x00408: | |
383 | val = s->leds; | |
384 | break; | |
385 | ||
386 | /* BRKRES Register */ | |
387 | case 0x00508: | |
388 | val = s->brk; | |
389 | break; | |
390 | ||
b6dc7ebb | 391 | /* UART Registers are handled directly by the serial device */ |
a4bc3afc | 392 | |
5856de80 TS |
393 | /* GPOUT Register */ |
394 | case 0x00a00: | |
395 | val = s->gpout; | |
396 | break; | |
397 | ||
398 | /* XXX: implement a real I2C controller */ | |
399 | ||
400 | /* GPINP Register */ | |
401 | case 0x00a08: | |
402 | /* IN = OUT until a real I2C control is implemented */ | |
94818443 | 403 | if (s->i2csel) { |
5856de80 | 404 | val = s->i2cout; |
94818443 | 405 | } else { |
5856de80 | 406 | val = 0x00; |
94818443 | 407 | } |
5856de80 TS |
408 | break; |
409 | ||
410 | /* I2CINP Register */ | |
411 | case 0x00b00: | |
35c64807 | 412 | val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom)); |
5856de80 TS |
413 | break; |
414 | ||
415 | /* I2COE Register */ | |
416 | case 0x00b08: | |
417 | val = s->i2coe; | |
418 | break; | |
419 | ||
420 | /* I2COUT Register */ | |
421 | case 0x00b10: | |
422 | val = s->i2cout; | |
423 | break; | |
424 | ||
425 | /* I2CSEL Register */ | |
426 | case 0x00b18: | |
130751ee | 427 | val = s->i2csel; |
5856de80 TS |
428 | break; |
429 | ||
430 | default: | |
c707f06f AM |
431 | qemu_log_mask(LOG_GUEST_ERROR, |
432 | "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n", | |
433 | addr); | |
5856de80 TS |
434 | break; |
435 | } | |
436 | return val; | |
437 | } | |
438 | ||
a8170e5e | 439 | static void malta_fpga_write(void *opaque, hwaddr addr, |
ea85df72 | 440 | uint64_t val, unsigned size) |
5856de80 TS |
441 | { |
442 | MaltaFPGAState *s = opaque; | |
443 | uint32_t saddr; | |
444 | ||
445 | saddr = (addr & 0xfffff); | |
446 | ||
447 | switch (saddr) { | |
448 | ||
449 | /* SWITCH Register */ | |
450 | case 0x00200: | |
451 | break; | |
452 | ||
453 | /* JMPRS Register */ | |
454 | case 0x00210: | |
455 | break; | |
456 | ||
457 | /* LEDBAR Register */ | |
5856de80 TS |
458 | case 0x00408: |
459 | s->leds = val & 0xff; | |
1d7a1197 | 460 | malta_fpga_update_display(s); |
5856de80 TS |
461 | break; |
462 | ||
463 | /* ASCIIWORD Register */ | |
464 | case 0x00410: | |
ea85df72 | 465 | snprintf(s->display_text, 9, "%08X", (uint32_t)val); |
5856de80 TS |
466 | malta_fpga_update_display(s); |
467 | break; | |
468 | ||
469 | /* ASCIIPOS0 to ASCIIPOS7 Registers */ | |
470 | case 0x00418: | |
471 | case 0x00420: | |
472 | case 0x00428: | |
473 | case 0x00430: | |
474 | case 0x00438: | |
475 | case 0x00440: | |
476 | case 0x00448: | |
477 | case 0x00450: | |
478 | s->display_text[(saddr - 0x00418) >> 3] = (char) val; | |
479 | malta_fpga_update_display(s); | |
480 | break; | |
481 | ||
482 | /* SOFTRES Register */ | |
483 | case 0x00500: | |
94818443 | 484 | if (val == 0x42) { |
cf83f140 | 485 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
94818443 | 486 | } |
5856de80 TS |
487 | break; |
488 | ||
489 | /* BRKRES Register */ | |
490 | case 0x00508: | |
491 | s->brk = val & 0xff; | |
492 | break; | |
493 | ||
b6dc7ebb | 494 | /* UART Registers are handled directly by the serial device */ |
a4bc3afc | 495 | |
5856de80 TS |
496 | /* GPOUT Register */ |
497 | case 0x00a00: | |
498 | s->gpout = val & 0xff; | |
499 | break; | |
500 | ||
501 | /* I2COE Register */ | |
502 | case 0x00b08: | |
503 | s->i2coe = val & 0x03; | |
504 | break; | |
505 | ||
506 | /* I2COUT Register */ | |
507 | case 0x00b10: | |
35c64807 | 508 | eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01); |
130751ee | 509 | s->i2cout = val; |
5856de80 TS |
510 | break; |
511 | ||
512 | /* I2CSEL Register */ | |
513 | case 0x00b18: | |
130751ee | 514 | s->i2csel = val & 0x01; |
5856de80 TS |
515 | break; |
516 | ||
517 | default: | |
c707f06f AM |
518 | qemu_log_mask(LOG_GUEST_ERROR, |
519 | "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n", | |
520 | addr); | |
5856de80 TS |
521 | break; |
522 | } | |
523 | } | |
524 | ||
ea85df72 AK |
525 | static const MemoryRegionOps malta_fpga_ops = { |
526 | .read = malta_fpga_read, | |
527 | .write = malta_fpga_write, | |
528 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5856de80 TS |
529 | }; |
530 | ||
9596ebb7 | 531 | static void malta_fpga_reset(void *opaque) |
5856de80 TS |
532 | { |
533 | MaltaFPGAState *s = opaque; | |
534 | ||
535 | s->leds = 0x00; | |
536 | s->brk = 0x0a; | |
537 | s->gpout = 0x00; | |
130751ee | 538 | s->i2cin = 0x3; |
5856de80 TS |
539 | s->i2coe = 0x0; |
540 | s->i2cout = 0x3; | |
541 | s->i2csel = 0x1; | |
542 | ||
543 | s->display_text[8] = '\0'; | |
544 | snprintf(s->display_text, 9, " "); | |
ceecf1d1 AJ |
545 | } |
546 | ||
083b266f | 547 | static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event) |
ceecf1d1 | 548 | { |
9850b05d MAL |
549 | MaltaFPGAState *s = opaque; |
550 | ||
551 | if (event == CHR_EVENT_OPENED && !s->display_inited) { | |
5345fdb4 MAL |
552 | qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n"); |
553 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
554 | qemu_chr_fe_printf(&s->display, "+ +\r\n"); | |
555 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
556 | qemu_chr_fe_printf(&s->display, "\n"); | |
557 | qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n"); | |
558 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
559 | qemu_chr_fe_printf(&s->display, "+ +\r\n"); | |
560 | qemu_chr_fe_printf(&s->display, "+--------+\r\n"); | |
9850b05d MAL |
561 | s->display_inited = true; |
562 | } | |
5856de80 TS |
563 | } |
564 | ||
ea85df72 | 565 | static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space, |
0ec7b3e7 | 566 | hwaddr base, qemu_irq uart_irq, Chardev *uart_chr) |
5856de80 TS |
567 | { |
568 | MaltaFPGAState *s; | |
0ec7b3e7 | 569 | Chardev *chr; |
5856de80 | 570 | |
dbd07eda | 571 | s = g_new0(MaltaFPGAState, 1); |
5856de80 | 572 | |
2c9b15ca | 573 | memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s, |
ea85df72 | 574 | "malta-fpga", 0x100000); |
2c9b15ca | 575 | memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga", |
ea85df72 | 576 | &s->iomem, 0, 0x900); |
2c9b15ca | 577 | memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga", |
94818443 | 578 | &s->iomem, 0xa00, 0x10000 - 0xa00); |
a4bc3afc | 579 | |
ea85df72 AK |
580 | memory_region_add_subregion(address_space, base, &s->iomem_lo); |
581 | memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi); | |
5856de80 | 582 | |
4ad6f6cb | 583 | chr = qemu_chr_new("fpga", "vc:320x200", NULL); |
5345fdb4 MAL |
584 | qemu_chr_fe_init(&s->display, chr, NULL); |
585 | qemu_chr_fe_set_handlers(&s->display, NULL, NULL, | |
81517ba3 | 586 | malta_fgpa_display_event, NULL, s, NULL, true); |
ceecf1d1 | 587 | |
39186d8a RH |
588 | s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq, |
589 | 230400, uart_chr, DEVICE_NATIVE_ENDIAN); | |
a4bc3afc | 590 | |
5856de80 | 591 | malta_fpga_reset(s); |
a08d4367 | 592 | qemu_register_reset(malta_fpga_reset, s); |
5856de80 TS |
593 | |
594 | return s; | |
595 | } | |
596 | ||
5856de80 | 597 | /* Network support */ |
29b358f9 | 598 | static void network_init(PCIBus *pci_bus) |
5856de80 TS |
599 | { |
600 | int i; | |
5856de80 | 601 | |
94818443 | 602 | for (i = 0; i < nb_nics; i++) { |
cb457d76 | 603 | NICInfo *nd = &nd_table[i]; |
5607c388 | 604 | const char *default_devaddr = NULL; |
cb457d76 AL |
605 | |
606 | if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0)) | |
5856de80 | 607 | /* The malta board has a PCNet card using PCI SLOT 11 */ |
5607c388 | 608 | default_devaddr = "0b"; |
cb457d76 | 609 | |
29b358f9 | 610 | pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr); |
5856de80 TS |
611 | } |
612 | } | |
613 | ||
ce3940cc MF |
614 | static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, |
615 | int64_t kernel_entry) | |
616 | { | |
617 | uint16_t *p; | |
618 | ||
619 | /* Small bootloader */ | |
620 | p = (uint16_t *)base; | |
621 | ||
622 | #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f) | |
623 | #define NM_HI2(VAL) \ | |
28861af8 | 624 | (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1)) |
ce3940cc MF |
625 | #define NM_LO(VAL) ((VAL) & 0xfff) |
626 | ||
28861af8 PB |
627 | stw_p(p++, 0x2800); stw_p(p++, 0x001c); |
628 | /* bc to_here */ | |
629 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
630 | /* nop */ | |
631 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
632 | /* nop */ | |
633 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
634 | /* nop */ | |
635 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
636 | /* nop */ | |
637 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
638 | /* nop */ | |
639 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
640 | /* nop */ | |
641 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
642 | /* nop */ | |
ce3940cc MF |
643 | |
644 | /* to_here: */ | |
bf4667d0 SM |
645 | if (semihosting_get_argc()) { |
646 | /* Preserve a0 content as arguments have been passed */ | |
647 | stw_p(p++, 0x8000); stw_p(p++, 0xc000); | |
648 | /* nop */ | |
649 | } else { | |
650 | stw_p(p++, 0x0080); stw_p(p++, 0x0002); | |
28861af8 | 651 | /* li a0,2 */ |
bf4667d0 | 652 | } |
28861af8 | 653 | |
ce3940cc | 654 | stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); |
28861af8 | 655 | |
ce3940cc | 656 | stw_p(p++, NM_HI2(ENVP_ADDR - 64)); |
28861af8 PB |
657 | /* lui sp,%hi(ENVP_ADDR - 64) */ |
658 | ||
ce3940cc MF |
659 | stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); |
660 | /* ori sp,sp,%lo(ENVP_ADDR - 64) */ | |
28861af8 | 661 | |
ce3940cc | 662 | stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); |
28861af8 | 663 | |
ce3940cc | 664 | stw_p(p++, NM_HI2(ENVP_ADDR)); |
28861af8 PB |
665 | /* lui a1,%hi(ENVP_ADDR) */ |
666 | ||
ce3940cc | 667 | stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); |
28861af8 PB |
668 | /* ori a1,a1,%lo(ENVP_ADDR) */ |
669 | ||
ce3940cc | 670 | stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); |
28861af8 | 671 | |
ce3940cc | 672 | stw_p(p++, NM_HI2(ENVP_ADDR + 8)); |
28861af8 PB |
673 | /* lui a2,%hi(ENVP_ADDR + 8) */ |
674 | ||
ce3940cc MF |
675 | stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); |
676 | /* ori a2,a2,%lo(ENVP_ADDR + 8) */ | |
28861af8 | 677 | |
ce3940cc | 678 | stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); |
28861af8 | 679 | |
ce3940cc MF |
680 | stw_p(p++, NM_HI2(loaderparams.ram_low_size)); |
681 | /* lui a3,%hi(loaderparams.ram_low_size) */ | |
28861af8 | 682 | |
ce3940cc MF |
683 | stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size)); |
684 | /* ori a3,a3,%lo(loaderparams.ram_low_size) */ | |
28861af8 PB |
685 | |
686 | /* | |
687 | * Load BAR registers as done by YAMON: | |
688 | * | |
689 | * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff | |
690 | * - set up PCI0 MEM0 at 0x10000000, size 0x8000000 | |
691 | * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000 | |
692 | * | |
693 | */ | |
694 | stw_p(p++, 0xe040); stw_p(p++, 0x0681); | |
695 | /* lui t1, %hi(0xb4000000) */ | |
696 | ||
697 | #ifdef TARGET_WORDS_BIGENDIAN | |
698 | ||
699 | stw_p(p++, 0xe020); stw_p(p++, 0x0be1); | |
700 | /* lui t0, %hi(0xdf000000) */ | |
701 | ||
702 | /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */ | |
703 | stw_p(p++, 0x8422); stw_p(p++, 0x9068); | |
704 | /* sw t0, 0x68(t1) */ | |
705 | ||
706 | stw_p(p++, 0xe040); stw_p(p++, 0x077d); | |
707 | /* lui t1, %hi(0xbbe00000) */ | |
708 | ||
709 | stw_p(p++, 0xe020); stw_p(p++, 0x0801); | |
710 | /* lui t0, %hi(0xc0000000) */ | |
711 | ||
712 | /* 0x48 corresponds to GT_PCI0IOLD */ | |
713 | stw_p(p++, 0x8422); stw_p(p++, 0x9048); | |
714 | /* sw t0, 0x48(t1) */ | |
715 | ||
716 | stw_p(p++, 0xe020); stw_p(p++, 0x0800); | |
717 | /* lui t0, %hi(0x40000000) */ | |
718 | ||
719 | /* 0x50 corresponds to GT_PCI0IOHD */ | |
720 | stw_p(p++, 0x8422); stw_p(p++, 0x9050); | |
721 | /* sw t0, 0x50(t1) */ | |
722 | ||
723 | stw_p(p++, 0xe020); stw_p(p++, 0x0001); | |
724 | /* lui t0, %hi(0x80000000) */ | |
725 | ||
726 | /* 0x58 corresponds to GT_PCI0M0LD */ | |
727 | stw_p(p++, 0x8422); stw_p(p++, 0x9058); | |
728 | /* sw t0, 0x58(t1) */ | |
729 | ||
730 | stw_p(p++, 0xe020); stw_p(p++, 0x07e0); | |
731 | /* lui t0, %hi(0x3f000000) */ | |
732 | ||
733 | /* 0x60 corresponds to GT_PCI0M0HD */ | |
734 | stw_p(p++, 0x8422); stw_p(p++, 0x9060); | |
735 | /* sw t0, 0x60(t1) */ | |
736 | ||
737 | stw_p(p++, 0xe020); stw_p(p++, 0x0821); | |
738 | /* lui t0, %hi(0xc1000000) */ | |
739 | ||
740 | /* 0x80 corresponds to GT_PCI0M1LD */ | |
741 | stw_p(p++, 0x8422); stw_p(p++, 0x9080); | |
742 | /* sw t0, 0x80(t1) */ | |
743 | ||
744 | stw_p(p++, 0xe020); stw_p(p++, 0x0bc0); | |
745 | /* lui t0, %hi(0x5e000000) */ | |
746 | ||
747 | #else | |
748 | ||
749 | stw_p(p++, 0x0020); stw_p(p++, 0x00df); | |
750 | /* addiu[32] t0, $0, 0xdf */ | |
751 | ||
752 | /* 0x68 corresponds to GT_ISD */ | |
753 | stw_p(p++, 0x8422); stw_p(p++, 0x9068); | |
754 | /* sw t0, 0x68(t1) */ | |
755 | ||
756 | /* Use kseg2 remapped address 0x1be00000 */ | |
757 | stw_p(p++, 0xe040); stw_p(p++, 0x077d); | |
758 | /* lui t1, %hi(0xbbe00000) */ | |
759 | ||
760 | stw_p(p++, 0x0020); stw_p(p++, 0x00c0); | |
761 | /* addiu[32] t0, $0, 0xc0 */ | |
762 | ||
763 | /* 0x48 corresponds to GT_PCI0IOLD */ | |
764 | stw_p(p++, 0x8422); stw_p(p++, 0x9048); | |
765 | /* sw t0, 0x48(t1) */ | |
766 | ||
767 | stw_p(p++, 0x0020); stw_p(p++, 0x0040); | |
768 | /* addiu[32] t0, $0, 0x40 */ | |
769 | ||
770 | /* 0x50 corresponds to GT_PCI0IOHD */ | |
771 | stw_p(p++, 0x8422); stw_p(p++, 0x9050); | |
772 | /* sw t0, 0x50(t1) */ | |
773 | ||
774 | stw_p(p++, 0x0020); stw_p(p++, 0x0080); | |
775 | /* addiu[32] t0, $0, 0x80 */ | |
776 | ||
777 | /* 0x58 corresponds to GT_PCI0M0LD */ | |
778 | stw_p(p++, 0x8422); stw_p(p++, 0x9058); | |
779 | /* sw t0, 0x58(t1) */ | |
780 | ||
781 | stw_p(p++, 0x0020); stw_p(p++, 0x003f); | |
782 | /* addiu[32] t0, $0, 0x3f */ | |
783 | ||
784 | /* 0x60 corresponds to GT_PCI0M0HD */ | |
785 | stw_p(p++, 0x8422); stw_p(p++, 0x9060); | |
786 | /* sw t0, 0x60(t1) */ | |
787 | ||
788 | stw_p(p++, 0x0020); stw_p(p++, 0x00c1); | |
789 | /* addiu[32] t0, $0, 0xc1 */ | |
790 | ||
791 | /* 0x80 corresponds to GT_PCI0M1LD */ | |
792 | stw_p(p++, 0x8422); stw_p(p++, 0x9080); | |
793 | /* sw t0, 0x80(t1) */ | |
794 | ||
795 | stw_p(p++, 0x0020); stw_p(p++, 0x005e); | |
796 | /* addiu[32] t0, $0, 0x5e */ | |
797 | ||
798 | #endif | |
799 | ||
800 | /* 0x88 corresponds to GT_PCI0M1HD */ | |
801 | stw_p(p++, 0x8422); stw_p(p++, 0x9088); | |
802 | /* sw t0, 0x88(t1) */ | |
803 | ||
ce3940cc | 804 | stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); |
28861af8 | 805 | |
ce3940cc | 806 | stw_p(p++, NM_HI2(kernel_entry)); |
28861af8 PB |
807 | /* lui t9,%hi(kernel_entry) */ |
808 | ||
ce3940cc | 809 | stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry)); |
28861af8 PB |
810 | /* ori t9,t9,%lo(kernel_entry) */ |
811 | ||
ce3940cc | 812 | stw_p(p++, 0x4bf9); stw_p(p++, 0x0000); |
28861af8 | 813 | /* jalrc t8 */ |
ce3940cc MF |
814 | } |
815 | ||
94818443 AM |
816 | /* |
817 | * ROM and pseudo bootloader | |
818 | * | |
819 | * The following code implements a very very simple bootloader. It first | |
820 | * loads the registers a0 to a3 to the values expected by the OS, and | |
821 | * then jump at the kernel address. | |
822 | * | |
823 | * The bootloader should pass the locations of the kernel arguments and | |
824 | * environment variables tables. Those tables contain the 32-bit address | |
825 | * of NULL terminated strings. The environment variables table should be | |
826 | * terminated by a NULL address. | |
827 | * | |
828 | * For a simpler implementation, the number of kernel arguments is fixed | |
829 | * to two (the name of the kernel and the command line), and the two | |
830 | * tables are actually the same one. | |
831 | * | |
832 | * The registers a0 to a3 should contain the following values: | |
833 | * a0 - number of kernel arguments | |
834 | * a1 - 32-bit address of the kernel arguments table | |
835 | * a2 - 32-bit address of the environment variables table | |
836 | * a3 - RAM size in bytes | |
837 | */ | |
cc518af0 LA |
838 | static void write_bootloader(uint8_t *base, int64_t run_addr, |
839 | int64_t kernel_entry) | |
5856de80 TS |
840 | { |
841 | uint32_t *p; | |
842 | ||
843 | /* Small bootloader */ | |
d7585251 | 844 | p = (uint32_t *)base; |
b0311811 | 845 | |
dbd07eda | 846 | stl_p(p++, 0x08000000 | /* j 0x1fc00580 */ |
b0311811 | 847 | ((run_addr + 0x580) & 0x0fffffff) >> 2); |
dbd07eda | 848 | stl_p(p++, 0x00000000); /* nop */ |
5856de80 | 849 | |
26ea0918 | 850 | /* YAMON service vector */ |
dbd07eda FB |
851 | stl_p(base + 0x500, run_addr + 0x0580); /* start: */ |
852 | stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */ | |
853 | stl_p(base + 0x520, run_addr + 0x0580); /* start: */ | |
854 | stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ | |
855 | stl_p(base + 0x534, run_addr + 0x0808); /* print: */ | |
856 | stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ | |
857 | stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ | |
858 | stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ | |
859 | stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ | |
860 | stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */ | |
861 | stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ | |
862 | stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */ | |
863 | stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */ | |
26ea0918 TS |
864 | |
865 | ||
5856de80 | 866 | /* Second part of the bootloader */ |
d7585251 | 867 | p = (uint32_t *) (base + 0x580); |
3b3c1694 LA |
868 | |
869 | if (semihosting_get_argc()) { | |
870 | /* Preserve a0 content as arguments have been passed */ | |
dbd07eda | 871 | stl_p(p++, 0x00000000); /* nop */ |
3b3c1694 | 872 | } else { |
dbd07eda | 873 | stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ |
3b3c1694 | 874 | } |
94818443 AM |
875 | |
876 | /* lui sp, high(ENVP_ADDR) */ | |
877 | stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); | |
878 | /* ori sp, sp, low(ENVP_ADDR) */ | |
879 | stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); | |
880 | /* lui a1, high(ENVP_ADDR) */ | |
881 | stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); | |
882 | /* ori a1, a1, low(ENVP_ADDR) */ | |
883 | stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); | |
884 | /* lui a2, high(ENVP_ADDR + 8) */ | |
885 | stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); | |
886 | /* ori a2, a2, low(ENVP_ADDR + 8) */ | |
887 | stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); | |
888 | /* lui a3, high(ram_low_size) */ | |
889 | stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); | |
890 | /* ori a3, a3, low(ram_low_size) */ | |
891 | stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); | |
2802bfe3 TS |
892 | |
893 | /* Load BAR registers as done by YAMON */ | |
dbd07eda | 894 | stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ |
a0a8793e TS |
895 | |
896 | #ifdef TARGET_WORDS_BIGENDIAN | |
dbd07eda | 897 | stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ |
a0a8793e | 898 | #else |
dbd07eda | 899 | stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ |
a0a8793e | 900 | #endif |
dbd07eda | 901 | stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ |
a0a8793e | 902 | |
dbd07eda | 903 | stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ |
2802bfe3 TS |
904 | |
905 | #ifdef TARGET_WORDS_BIGENDIAN | |
dbd07eda | 906 | stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ |
2802bfe3 | 907 | #else |
dbd07eda | 908 | stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ |
2802bfe3 | 909 | #endif |
dbd07eda | 910 | stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ |
2802bfe3 | 911 | #ifdef TARGET_WORDS_BIGENDIAN |
dbd07eda | 912 | stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ |
2802bfe3 | 913 | #else |
dbd07eda | 914 | stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ |
2802bfe3 | 915 | #endif |
dbd07eda | 916 | stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ |
2802bfe3 TS |
917 | |
918 | #ifdef TARGET_WORDS_BIGENDIAN | |
dbd07eda | 919 | stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ |
2802bfe3 | 920 | #else |
dbd07eda | 921 | stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ |
2802bfe3 | 922 | #endif |
dbd07eda | 923 | stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ |
2802bfe3 | 924 | #ifdef TARGET_WORDS_BIGENDIAN |
dbd07eda | 925 | stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ |
2802bfe3 | 926 | #else |
dbd07eda | 927 | stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ |
2802bfe3 | 928 | #endif |
dbd07eda | 929 | stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ |
2802bfe3 TS |
930 | |
931 | #ifdef TARGET_WORDS_BIGENDIAN | |
dbd07eda | 932 | stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ |
2802bfe3 | 933 | #else |
dbd07eda | 934 | stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ |
2802bfe3 | 935 | #endif |
dbd07eda | 936 | stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ |
2802bfe3 | 937 | #ifdef TARGET_WORDS_BIGENDIAN |
dbd07eda | 938 | stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ |
2802bfe3 | 939 | #else |
dbd07eda | 940 | stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ |
2802bfe3 | 941 | #endif |
dbd07eda | 942 | stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ |
2802bfe3 TS |
943 | |
944 | /* Jump to kernel code */ | |
dbd07eda FB |
945 | stl_p(p++, 0x3c1f0000 | |
946 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ | |
947 | stl_p(p++, 0x37ff0000 | | |
948 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ | |
949 | stl_p(p++, 0x03e00009); /* jalr ra */ | |
950 | stl_p(p++, 0x00000000); /* nop */ | |
26ea0918 TS |
951 | |
952 | /* YAMON subroutines */ | |
d7585251 | 953 | p = (uint32_t *) (base + 0x800); |
dbd07eda FB |
954 | stl_p(p++, 0x03e00009); /* jalr ra */ |
955 | stl_p(p++, 0x24020000); /* li v0,0 */ | |
b0311811 | 956 | /* 808 YAMON print */ |
dbd07eda FB |
957 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
958 | stl_p(p++, 0x00805821); /* move t3,a0 */ | |
959 | stl_p(p++, 0x00a05021); /* move t2,a1 */ | |
960 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ | |
961 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ | |
962 | stl_p(p++, 0x10800005); /* beqz a0,834 */ | |
963 | stl_p(p++, 0x00000000); /* nop */ | |
964 | stl_p(p++, 0x0ff0021c); /* jal 870 */ | |
965 | stl_p(p++, 0x00000000); /* nop */ | |
966 | stl_p(p++, 0x1000fff9); /* b 814 */ | |
967 | stl_p(p++, 0x00000000); /* nop */ | |
968 | stl_p(p++, 0x01a00009); /* jalr t5 */ | |
969 | stl_p(p++, 0x01602021); /* move a0,t3 */ | |
26ea0918 | 970 | /* 0x83c YAMON print_count */ |
dbd07eda FB |
971 | stl_p(p++, 0x03e06821); /* move t5,ra */ |
972 | stl_p(p++, 0x00805821); /* move t3,a0 */ | |
973 | stl_p(p++, 0x00a05021); /* move t2,a1 */ | |
974 | stl_p(p++, 0x00c06021); /* move t4,a2 */ | |
975 | stl_p(p++, 0x91440000); /* lbu a0,0(t2) */ | |
976 | stl_p(p++, 0x0ff0021c); /* jal 870 */ | |
977 | stl_p(p++, 0x00000000); /* nop */ | |
978 | stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */ | |
979 | stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */ | |
980 | stl_p(p++, 0x1580fffa); /* bnez t4,84c */ | |
981 | stl_p(p++, 0x00000000); /* nop */ | |
982 | stl_p(p++, 0x01a00009); /* jalr t5 */ | |
983 | stl_p(p++, 0x01602021); /* move a0,t3 */ | |
26ea0918 | 984 | /* 0x870 */ |
dbd07eda FB |
985 | stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */ |
986 | stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */ | |
987 | stl_p(p++, 0x91090005); /* lbu t1,5(t0) */ | |
988 | stl_p(p++, 0x00000000); /* nop */ | |
989 | stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */ | |
990 | stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */ | |
991 | stl_p(p++, 0x00000000); /* nop */ | |
992 | stl_p(p++, 0x03e00009); /* jalr ra */ | |
993 | stl_p(p++, 0xa1040000); /* sb a0,0(t0) */ | |
26ea0918 | 994 | |
5856de80 TS |
995 | } |
996 | ||
94818443 | 997 | static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, |
8b7968f7 | 998 | const char *string, ...) |
5856de80 TS |
999 | { |
1000 | va_list ap; | |
3ddd0065 | 1001 | int32_t table_addr; |
5856de80 | 1002 | |
94818443 | 1003 | if (index >= ENVP_NB_ENTRIES) { |
5856de80 | 1004 | return; |
94818443 | 1005 | } |
5856de80 | 1006 | |
5856de80 | 1007 | if (string == NULL) { |
c938ada2 | 1008 | prom_buf[index] = 0; |
5856de80 TS |
1009 | return; |
1010 | } | |
1011 | ||
c938ada2 AJ |
1012 | table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; |
1013 | prom_buf[index] = tswap32(ENVP_ADDR + table_addr); | |
5856de80 TS |
1014 | |
1015 | va_start(ap, string); | |
c938ada2 | 1016 | vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); |
5856de80 TS |
1017 | va_end(ap); |
1018 | } | |
1019 | ||
1020 | /* Kernel */ | |
94818443 | 1021 | static int64_t load_kernel(void) |
5856de80 | 1022 | { |
f3839fda LZ |
1023 | int64_t kernel_entry, kernel_high, initrd_size; |
1024 | long kernel_size; | |
c227f099 | 1025 | ram_addr_t initrd_offset; |
ca20cf32 | 1026 | int big_endian; |
c938ada2 AJ |
1027 | uint32_t *prom_buf; |
1028 | long prom_size; | |
1029 | int prom_index = 0; | |
b0311811 | 1030 | uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); |
ca20cf32 BS |
1031 | |
1032 | #ifdef TARGET_WORDS_BIGENDIAN | |
1033 | big_endian = 1; | |
1034 | #else | |
1035 | big_endian = 0; | |
1036 | #endif | |
5856de80 | 1037 | |
4366e1db LM |
1038 | kernel_size = load_elf(loaderparams.kernel_filename, NULL, |
1039 | cpu_mips_kseg0_to_phys, NULL, | |
1040 | (uint64_t *)&kernel_entry, NULL, | |
6cdda0ff AM |
1041 | (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS, |
1042 | 1, 0); | |
3ee3122c | 1043 | if (kernel_size < 0) { |
bd6e1d81 | 1044 | error_report("could not load kernel '%s': %s", |
3ee3122c AJ |
1045 | loaderparams.kernel_filename, |
1046 | load_elf_strerror(kernel_size)); | |
acdf72bb | 1047 | exit(1); |
5856de80 | 1048 | } |
f7f15245 | 1049 | |
d3d93c6c JH |
1050 | /* Check where the kernel has been linked */ |
1051 | if (kernel_entry & 0x80000000ll) { | |
1052 | if (kvm_enabled()) { | |
f7f15245 JH |
1053 | error_report("KVM guest kernels must be linked in useg. " |
1054 | "Did you forget to enable CONFIG_KVM_GUEST?"); | |
1055 | exit(1); | |
1056 | } | |
1057 | ||
d3d93c6c | 1058 | xlate_to_kseg0 = cpu_mips_phys_to_kseg0; |
b0311811 | 1059 | } else { |
d3d93c6c JH |
1060 | /* if kernel entry is in useg it is probably a KVM T&E kernel */ |
1061 | mips_um_ksegs_enable(); | |
f7f15245 | 1062 | |
d3d93c6c | 1063 | xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; |
b0311811 | 1064 | } |
5856de80 TS |
1065 | |
1066 | /* load initrd */ | |
1067 | initrd_size = 0; | |
74287114 | 1068 | initrd_offset = 0; |
7df526e3 | 1069 | if (loaderparams.initrd_filename) { |
94818443 | 1070 | initrd_size = get_image_size(loaderparams.initrd_filename); |
74287114 | 1071 | if (initrd_size > 0) { |
94818443 AM |
1072 | /* |
1073 | * The kernel allocates the bootmap memory in the low memory after | |
1074 | * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB | |
1075 | * pages. | |
1076 | */ | |
be01029e PMD |
1077 | initrd_offset = (loaderparams.ram_low_size - initrd_size |
1078 | - (128 * KiB) | |
9768e2ab AJ |
1079 | - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK; |
1080 | if (kernel_high >= initrd_offset) { | |
bd6e1d81 AF |
1081 | error_report("memory too small for initial ram disk '%s'", |
1082 | loaderparams.initrd_filename); | |
74287114 TS |
1083 | exit(1); |
1084 | } | |
dcac9679 PB |
1085 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
1086 | initrd_offset, | |
1087 | ram_size - initrd_offset); | |
74287114 | 1088 | } |
5856de80 | 1089 | if (initrd_size == (target_ulong) -1) { |
bd6e1d81 AF |
1090 | error_report("could not load initial ram disk '%s'", |
1091 | loaderparams.initrd_filename); | |
5856de80 TS |
1092 | exit(1); |
1093 | } | |
1094 | } | |
1095 | ||
c938ada2 AJ |
1096 | /* Setup prom parameters. */ |
1097 | prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE); | |
7267c094 | 1098 | prom_buf = g_malloc(prom_size); |
c938ada2 | 1099 | |
f36d53ef | 1100 | prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); |
c938ada2 | 1101 | if (initrd_size > 0) { |
94818443 AM |
1102 | prom_set(prom_buf, prom_index++, |
1103 | "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s", | |
1104 | xlate_to_kseg0(NULL, initrd_offset), | |
1105 | initrd_size, loaderparams.kernel_cmdline); | |
c938ada2 | 1106 | } else { |
f36d53ef | 1107 | prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); |
c938ada2 AJ |
1108 | } |
1109 | ||
1110 | prom_set(prom_buf, prom_index++, "memsize"); | |
71c199c8 PB |
1111 | prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size); |
1112 | ||
1113 | prom_set(prom_buf, prom_index++, "ememsize"); | |
1114 | prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size); | |
b0311811 | 1115 | |
c938ada2 AJ |
1116 | prom_set(prom_buf, prom_index++, "modetty0"); |
1117 | prom_set(prom_buf, prom_index++, "38400n8r"); | |
1118 | prom_set(prom_buf, prom_index++, NULL); | |
1119 | ||
1120 | rom_add_blob_fixed("prom", prom_buf, prom_size, | |
409dbce5 | 1121 | cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); |
5856de80 | 1122 | |
3ad9fd5a | 1123 | g_free(prom_buf); |
74287114 | 1124 | return kernel_entry; |
5856de80 TS |
1125 | } |
1126 | ||
ce3960eb | 1127 | static void malta_mips_config(MIPSCPU *cpu) |
c4cb2578 | 1128 | { |
33decbd2 LX |
1129 | MachineState *ms = MACHINE(qdev_get_machine()); |
1130 | unsigned int smp_cpus = ms->smp.cpus; | |
ce3960eb AF |
1131 | CPUMIPSState *env = &cpu->env; |
1132 | CPUState *cs = CPU(cpu); | |
1133 | ||
c4cb2578 | 1134 | env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | |
ce3960eb | 1135 | ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); |
c4cb2578 EI |
1136 | } |
1137 | ||
5856de80 TS |
1138 | static void main_cpu_reset(void *opaque) |
1139 | { | |
1004ee8d AF |
1140 | MIPSCPU *cpu = opaque; |
1141 | CPUMIPSState *env = &cpu->env; | |
1142 | ||
1143 | cpu_reset(CPU(cpu)); | |
5856de80 | 1144 | |
94818443 AM |
1145 | /* |
1146 | * The bootloader does not need to be rewritten as it is located in a | |
1147 | * read only location. The kernel location and the arguments table | |
1148 | * location does not change. | |
1149 | */ | |
7df526e3 | 1150 | if (loaderparams.kernel_filename) { |
d6ca4277 | 1151 | env->CP0_Status &= ~(1 << CP0St_ERL); |
fb82fea0 | 1152 | } |
c4cb2578 | 1153 | |
ce3960eb | 1154 | malta_mips_config(cpu); |
b0311811 JH |
1155 | |
1156 | if (kvm_enabled()) { | |
1157 | /* Start running from the bootloader we wrote to end of RAM */ | |
ca2f6bbb | 1158 | env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size; |
b0311811 | 1159 | } |
5856de80 TS |
1160 | } |
1161 | ||
a0628599 | 1162 | static void create_cpu_without_cps(MachineState *ms, |
bff384a4 | 1163 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
67a54961 LA |
1164 | { |
1165 | CPUMIPSState *env; | |
1166 | MIPSCPU *cpu; | |
1167 | int i; | |
67a54961 | 1168 | |
a0628599 LX |
1169 | for (i = 0; i < ms->smp.cpus; i++) { |
1170 | cpu = MIPS_CPU(cpu_create(ms->cpu_type)); | |
67a54961 LA |
1171 | |
1172 | /* Init internal devices */ | |
5a975d43 PB |
1173 | cpu_mips_irq_init_cpu(cpu); |
1174 | cpu_mips_clock_init(cpu); | |
67a54961 LA |
1175 | qemu_register_reset(main_cpu_reset, cpu); |
1176 | } | |
1177 | ||
1178 | cpu = MIPS_CPU(first_cpu); | |
1179 | env = &cpu->env; | |
1180 | *i8259_irq = env->irq[2]; | |
1181 | *cbus_irq = env->irq[4]; | |
1182 | } | |
1183 | ||
a0628599 | 1184 | static void create_cps(MachineState *ms, MaltaState *s, |
bff384a4 LA |
1185 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
1186 | { | |
0074fce6 | 1187 | object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); |
5325cc34 | 1188 | object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, |
a729f9bc | 1189 | &error_fatal); |
5325cc34 | 1190 | object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, |
a729f9bc | 1191 | &error_fatal); |
0074fce6 | 1192 | sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); |
bff384a4 | 1193 | |
2d5fac80 | 1194 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); |
bff384a4 | 1195 | |
2d5fac80 | 1196 | *i8259_irq = get_cps_irq(&s->cps, 3); |
bff384a4 LA |
1197 | *cbus_irq = NULL; |
1198 | } | |
1199 | ||
a0628599 | 1200 | static void mips_create_cpu(MachineState *ms, MaltaState *s, |
a7519f2b | 1201 | qemu_irq *cbus_irq, qemu_irq *i8259_irq) |
bff384a4 | 1202 | { |
a0628599 LX |
1203 | if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { |
1204 | create_cps(ms, s, cbus_irq, i8259_irq); | |
bff384a4 | 1205 | } else { |
a0628599 | 1206 | create_cpu_without_cps(ms, cbus_irq, i8259_irq); |
bff384a4 LA |
1207 | } |
1208 | } | |
1209 | ||
70705261 | 1210 | static |
3ef96221 | 1211 | void mips_malta_init(MachineState *machine) |
5856de80 | 1212 | { |
3ef96221 | 1213 | ram_addr_t ram_size = machine->ram_size; |
b0311811 | 1214 | ram_addr_t ram_low_size; |
3ef96221 MA |
1215 | const char *kernel_filename = machine->kernel_filename; |
1216 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1217 | const char *initrd_filename = machine->initrd_filename; | |
5cea8590 | 1218 | char *filename; |
16434065 | 1219 | PFlashCFI01 *fl; |
cfe5f011 | 1220 | MemoryRegion *system_memory = get_system_memory(); |
94c2b6af PB |
1221 | MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); |
1222 | MemoryRegion *ram_low_postio; | |
a427338b | 1223 | MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); |
35c64807 PB |
1224 | const size_t smbus_eeprom_size = 8 * 256; |
1225 | uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); | |
b0311811 | 1226 | int64_t kernel_entry, bootloader_run_addr; |
5856de80 | 1227 | PCIBus *pci_bus; |
48a18b3c | 1228 | ISABus *isa_bus; |
67a54961 | 1229 | qemu_irq cbus_irq, i8259_irq; |
a5c82852 | 1230 | I2CBus *smbus; |
751c6a17 | 1231 | DriveInfo *dinfo; |
c8b153d7 | 1232 | int fl_idx = 0; |
01e0451a | 1233 | int be; |
5856de80 | 1234 | |
3e80f690 | 1235 | DeviceState *dev = qdev_new(TYPE_MIPS_MALTA); |
cba5cb67 | 1236 | MaltaState *s = MIPS_MALTA(dev); |
e9b40fd3 | 1237 | |
94818443 AM |
1238 | /* |
1239 | * The whole address space decoded by the GT-64120A doesn't generate | |
1240 | * exception when accessing invalid memory. Create an empty slot to | |
dbd07eda | 1241 | * emulate this feature. |
94818443 | 1242 | */ |
28c78fe8 | 1243 | empty_slot_init("GT64120", 0, 0x20000000); |
cc413a39 | 1244 | |
3c6ef471 | 1245 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9b40fd3 | 1246 | |
bff384a4 | 1247 | /* create CPU */ |
a0628599 | 1248 | mips_create_cpu(machine, s, &cbus_irq, &i8259_irq); |
5856de80 TS |
1249 | |
1250 | /* allocate RAM */ | |
be01029e PMD |
1251 | if (ram_size > 2 * GiB) { |
1252 | error_report("Too much memory for this machine: %" PRId64 "MB," | |
1253 | " maximum 2048MB", ram_size / MiB); | |
0ccff151 AJ |
1254 | exit(1); |
1255 | } | |
94c2b6af PB |
1256 | |
1257 | /* register RAM at high address where it is undisturbed by IO */ | |
3a6e6ac7 | 1258 | memory_region_add_subregion(system_memory, 0x80000000, machine->ram); |
94c2b6af PB |
1259 | |
1260 | /* alias for pre IO hole access */ | |
1261 | memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", | |
3a6e6ac7 | 1262 | machine->ram, 0, MIN(ram_size, 256 * MiB)); |
94c2b6af PB |
1263 | memory_region_add_subregion(system_memory, 0, ram_low_preio); |
1264 | ||
1265 | /* alias for post IO hole access, if there is enough RAM */ | |
be01029e | 1266 | if (ram_size > 512 * MiB) { |
94c2b6af PB |
1267 | ram_low_postio = g_new(MemoryRegion, 1); |
1268 | memory_region_init_alias(ram_low_postio, NULL, | |
1269 | "mips_malta_low_postio.ram", | |
3a6e6ac7 | 1270 | machine->ram, 512 * MiB, |
be01029e PMD |
1271 | ram_size - 512 * MiB); |
1272 | memory_region_add_subregion(system_memory, 512 * MiB, | |
1273 | ram_low_postio); | |
94c2b6af | 1274 | } |
5856de80 | 1275 | |
01e0451a AL |
1276 | #ifdef TARGET_WORDS_BIGENDIAN |
1277 | be = 1; | |
1278 | #else | |
1279 | be = 0; | |
1280 | #endif | |
7313b1f2 | 1281 | |
070ce5ed | 1282 | /* FPGA */ |
7313b1f2 | 1283 | |
68d00192 | 1284 | /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ |
9bca0edb | 1285 | malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); |
070ce5ed | 1286 | |
bb4b3358 SW |
1287 | /* Load firmware in flash / BIOS. */ |
1288 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); | |
940d5b13 | 1289 | fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", |
7ebfece5 | 1290 | FLASH_SIZE, |
4be74634 | 1291 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 1292 | 65536, |
bb4b3358 SW |
1293 | 4, 0x0000, 0x0000, 0x0000, 0x0000, be); |
1294 | bios = pflash_cfi01_get_memory(fl); | |
1295 | fl_idx++; | |
c8b153d7 | 1296 | if (kernel_filename) { |
be01029e | 1297 | ram_low_size = MIN(ram_size, 256 * MiB); |
fbdb1d95 | 1298 | /* For KVM we reserve 1MB of RAM for running bootloader */ |
b0311811 JH |
1299 | if (kvm_enabled()) { |
1300 | ram_low_size -= 0x100000; | |
1301 | bootloader_run_addr = 0x40000000 + ram_low_size; | |
1302 | } else { | |
1303 | bootloader_run_addr = 0xbfc00000; | |
1304 | } | |
1305 | ||
c8b153d7 | 1306 | /* Write a small bootloader to the flash location. */ |
71c199c8 PB |
1307 | loaderparams.ram_size = ram_size; |
1308 | loaderparams.ram_low_size = ram_low_size; | |
c8b153d7 TS |
1309 | loaderparams.kernel_filename = kernel_filename; |
1310 | loaderparams.kernel_cmdline = kernel_cmdline; | |
1311 | loaderparams.initrd_filename = initrd_filename; | |
e16ad5b0 | 1312 | kernel_entry = load_kernel(); |
b0311811 | 1313 | |
ce3940cc MF |
1314 | if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { |
1315 | write_bootloader(memory_region_get_ram_ptr(bios), | |
1316 | bootloader_run_addr, kernel_entry); | |
1317 | } else { | |
1318 | write_bootloader_nanomips(memory_region_get_ram_ptr(bios), | |
1319 | bootloader_run_addr, kernel_entry); | |
1320 | } | |
b0311811 JH |
1321 | if (kvm_enabled()) { |
1322 | /* Write the bootloader code @ the end of RAM, 1MB reserved */ | |
cc518af0 | 1323 | write_bootloader(memory_region_get_ram_ptr(ram_low_preio) + |
b0311811 JH |
1324 | ram_low_size, |
1325 | bootloader_run_addr, kernel_entry); | |
1326 | } | |
c8b153d7 | 1327 | } else { |
74c02ebd | 1328 | target_long bios_size = FLASH_SIZE; |
fbdb1d95 | 1329 | /* The flash region isn't executable from a KVM guest */ |
3c5d0be5 JH |
1330 | if (kvm_enabled()) { |
1331 | error_report("KVM enabled but no -kernel argument was specified. " | |
fbdb1d95 | 1332 | "Booting from flash is not supported with KVM."); |
3c5d0be5 JH |
1333 | exit(1); |
1334 | } | |
bb4b3358 SW |
1335 | /* Load firmware from flash. */ |
1336 | if (!dinfo) { | |
c8b153d7 | 1337 | /* Load a BIOS image. */ |
bb4b3358 | 1338 | if (bios_name == NULL) { |
c8b153d7 | 1339 | bios_name = BIOS_FILENAME; |
bb4b3358 | 1340 | } |
5cea8590 PB |
1341 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1342 | if (filename) { | |
03a1a8e1 | 1343 | bios_size = load_image_targphys(filename, FLASH_ADDRESS, |
5cea8590 | 1344 | BIOS_SIZE); |
7267c094 | 1345 | g_free(filename); |
5cea8590 PB |
1346 | } else { |
1347 | bios_size = -1; | |
1348 | } | |
2c57bd9b AF |
1349 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && |
1350 | !kernel_filename && !qtest_enabled()) { | |
2e985fe0 AJ |
1351 | error_report("Could not load MIPS bios '%s', and no " |
1352 | "-kernel argument was specified", bios_name); | |
1353 | exit(1); | |
c8b153d7 | 1354 | } |
070ce5ed | 1355 | } |
94818443 AM |
1356 | /* |
1357 | * In little endian mode the 32bit words in the bios are swapped, | |
1358 | * a neat trick which allows bi-endian firmware. | |
1359 | */ | |
3187ef03 TS |
1360 | #ifndef TARGET_WORDS_BIGENDIAN |
1361 | { | |
0f0f8b61 TH |
1362 | uint32_t *end, *addr; |
1363 | const size_t swapsize = MIN(bios_size, 0x3e0000); | |
1364 | addr = rom_ptr(FLASH_ADDRESS, swapsize); | |
a2b8813d PB |
1365 | if (!addr) { |
1366 | addr = memory_region_get_ram_ptr(bios); | |
1367 | } | |
0f0f8b61 | 1368 | end = (void *)addr + swapsize; |
d7585251 PB |
1369 | while (addr < end) { |
1370 | bswap32s(addr); | |
a30cfee5 | 1371 | addr++; |
3187ef03 TS |
1372 | } |
1373 | } | |
1374 | #endif | |
070ce5ed TS |
1375 | } |
1376 | ||
a427338b PB |
1377 | /* |
1378 | * Map the BIOS at a 2nd physical location, as on the real board. | |
1379 | * Copy it so that we can patch in the MIPS revision, which cannot be | |
1380 | * handled by an overlapping region as the resulting ROM code subpage | |
1381 | * regions are not executable. | |
1382 | */ | |
917b77f5 | 1383 | memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, |
f8ed85ac | 1384 | &error_fatal); |
a427338b | 1385 | if (!rom_copy(memory_region_get_ram_ptr(bios_copy), |
f05d4d94 | 1386 | FLASH_ADDRESS, BIOS_SIZE)) { |
a427338b | 1387 | memcpy(memory_region_get_ram_ptr(bios_copy), |
f05d4d94 | 1388 | memory_region_get_ram_ptr(bios), BIOS_SIZE); |
a427338b PB |
1389 | } |
1390 | memory_region_set_readonly(bios_copy, true); | |
1391 | memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy); | |
82a9807b | 1392 | |
a427338b PB |
1393 | /* Board ID = 0x420 (Malta Board with CoreLV) */ |
1394 | stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); | |
5856de80 | 1395 | |
5856de80 | 1396 | /* Northbridge */ |
078778c5 | 1397 | pci_bus = gt64120_register(s->i8259); |
5856de80 TS |
1398 | |
1399 | /* Southbridge */ | |
be1765f3 | 1400 | dev = piix4_create(pci_bus, &isa_bus, &smbus); |
5632ae46 | 1401 | |
078778c5 HP |
1402 | /* Interrupt controller */ |
1403 | qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); | |
1404 | for (int i = 0; i < ISA_NUM_IRQS; i++) { | |
1405 | s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); | |
1406 | } | |
5632ae46 | 1407 | |
78f16256 PMD |
1408 | /* generate SPD EEPROM data */ |
1409 | generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); | |
1410 | generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); | |
1411 | smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); | |
1412 | g_free(smbus_eeprom_buf); | |
5856de80 | 1413 | |
7313b1f2 PMD |
1414 | /* Super I/O: SMS FDC37M817 */ |
1415 | isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); | |
5856de80 | 1416 | |
5856de80 | 1417 | /* Network card */ |
29b358f9 | 1418 | network_init(pci_bus); |
11f29511 TS |
1419 | |
1420 | /* Optional PCI video card */ | |
9c59864d | 1421 | pci_vga_init(pci_bus); |
5856de80 TS |
1422 | } |
1423 | ||
8c43a6f0 | 1424 | static const TypeInfo mips_malta_device = { |
cba5cb67 | 1425 | .name = TYPE_MIPS_MALTA, |
39bffca2 AL |
1426 | .parent = TYPE_SYS_BUS_DEVICE, |
1427 | .instance_size = sizeof(MaltaState), | |
e9b40fd3 SW |
1428 | }; |
1429 | ||
e264d29d | 1430 | static void mips_malta_machine_init(MachineClass *mc) |
e9b40fd3 | 1431 | { |
e264d29d EH |
1432 | mc->desc = "MIPS Malta Core LV"; |
1433 | mc->init = mips_malta_init; | |
2059839b | 1434 | mc->block_default_type = IF_IDE; |
e264d29d | 1435 | mc->max_cpus = 16; |
ea0ac7f6 | 1436 | mc->is_default = true; |
a7519f2b IM |
1437 | #ifdef TARGET_MIPS64 |
1438 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc"); | |
1439 | #else | |
1440 | mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); | |
1441 | #endif | |
3a6e6ac7 | 1442 | mc->default_ram_id = "mips_malta.ram"; |
e9b40fd3 SW |
1443 | } |
1444 | ||
e264d29d EH |
1445 | DEFINE_MACHINE("malta", mips_malta_machine_init) |
1446 | ||
1447 | static void mips_malta_register_types(void) | |
f80f9ec9 | 1448 | { |
e264d29d | 1449 | type_register_static(&mips_malta_device); |
f80f9ec9 AL |
1450 | } |
1451 | ||
83f7d43a | 1452 | type_init(mips_malta_register_types) |