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1 | /* |
2 | * ARM SSE-200 CPU_IDENTITY register block | |
3 | * | |
4 | * Copyright (c) 2019 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This is a model of the "CPU_IDENTITY" register block which is part of the | |
14 | * Arm SSE-200 and documented in | |
15 | * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | |
16 | * | |
17 | * It consists of one read-only CPUID register (set by QOM property), plus the | |
18 | * usual ID registers. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "qemu/log.h" | |
0b8fa32f | 23 | #include "qemu/module.h" |
5aeb3689 PM |
24 | #include "trace.h" |
25 | #include "qapi/error.h" | |
26 | #include "sysemu/sysemu.h" | |
27 | #include "hw/sysbus.h" | |
28 | #include "hw/registerfields.h" | |
29 | #include "hw/misc/armsse-cpuid.h" | |
a27bd6c7 | 30 | #include "hw/qdev-properties.h" |
5aeb3689 PM |
31 | |
32 | REG32(CPUID, 0x0) | |
33 | REG32(PID4, 0xfd0) | |
34 | REG32(PID5, 0xfd4) | |
35 | REG32(PID6, 0xfd8) | |
36 | REG32(PID7, 0xfdc) | |
37 | REG32(PID0, 0xfe0) | |
38 | REG32(PID1, 0xfe4) | |
39 | REG32(PID2, 0xfe8) | |
40 | REG32(PID3, 0xfec) | |
41 | REG32(CID0, 0xff0) | |
42 | REG32(CID1, 0xff4) | |
43 | REG32(CID2, 0xff8) | |
44 | REG32(CID3, 0xffc) | |
45 | ||
46 | /* PID/CID values */ | |
47 | static const int sysinfo_id[] = { | |
48 | 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ | |
49 | 0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ | |
50 | 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | |
51 | }; | |
52 | ||
53 | static uint64_t armsse_cpuid_read(void *opaque, hwaddr offset, | |
54 | unsigned size) | |
55 | { | |
56 | ARMSSECPUID *s = ARMSSE_CPUID(opaque); | |
57 | uint64_t r; | |
58 | ||
59 | switch (offset) { | |
60 | case A_CPUID: | |
61 | r = s->cpuid; | |
62 | break; | |
63 | case A_PID4 ... A_CID3: | |
64 | r = sysinfo_id[(offset - A_PID4) / 4]; | |
65 | break; | |
66 | default: | |
67 | qemu_log_mask(LOG_GUEST_ERROR, | |
68 | "SSE CPU_IDENTITY read: bad offset 0x%x\n", (int)offset); | |
69 | r = 0; | |
70 | break; | |
71 | } | |
72 | trace_armsse_cpuid_read(offset, r, size); | |
73 | return r; | |
74 | } | |
75 | ||
76 | static void armsse_cpuid_write(void *opaque, hwaddr offset, | |
77 | uint64_t value, unsigned size) | |
78 | { | |
79 | trace_armsse_cpuid_write(offset, value, size); | |
80 | ||
81 | qemu_log_mask(LOG_GUEST_ERROR, | |
82 | "SSE CPU_IDENTITY: write to RO offset 0x%x\n", (int)offset); | |
83 | } | |
84 | ||
85 | static const MemoryRegionOps armsse_cpuid_ops = { | |
86 | .read = armsse_cpuid_read, | |
87 | .write = armsse_cpuid_write, | |
88 | .endianness = DEVICE_LITTLE_ENDIAN, | |
89 | /* byte/halfword accesses are just zero-padded on reads and writes */ | |
90 | .impl.min_access_size = 4, | |
91 | .impl.max_access_size = 4, | |
92 | .valid.min_access_size = 1, | |
93 | .valid.max_access_size = 4, | |
94 | }; | |
95 | ||
96 | static Property armsse_cpuid_props[] = { | |
97 | DEFINE_PROP_UINT32("CPUID", ARMSSECPUID, cpuid, 0), | |
98 | DEFINE_PROP_END_OF_LIST() | |
99 | }; | |
100 | ||
101 | static void armsse_cpuid_init(Object *obj) | |
102 | { | |
103 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
104 | ARMSSECPUID *s = ARMSSE_CPUID(obj); | |
105 | ||
106 | memory_region_init_io(&s->iomem, obj, &armsse_cpuid_ops, | |
107 | s, "armsse-cpuid", 0x1000); | |
108 | sysbus_init_mmio(sbd, &s->iomem); | |
109 | } | |
110 | ||
111 | static void armsse_cpuid_class_init(ObjectClass *klass, void *data) | |
112 | { | |
113 | DeviceClass *dc = DEVICE_CLASS(klass); | |
114 | ||
115 | /* | |
116 | * This device has no guest-modifiable state and so it | |
117 | * does not need a reset function or VMState. | |
118 | */ | |
119 | ||
120 | dc->props = armsse_cpuid_props; | |
121 | } | |
122 | ||
123 | static const TypeInfo armsse_cpuid_info = { | |
124 | .name = TYPE_ARMSSE_CPUID, | |
125 | .parent = TYPE_SYS_BUS_DEVICE, | |
126 | .instance_size = sizeof(ARMSSECPUID), | |
127 | .instance_init = armsse_cpuid_init, | |
128 | .class_init = armsse_cpuid_class_init, | |
129 | }; | |
130 | ||
131 | static void armsse_cpuid_register_types(void) | |
132 | { | |
133 | type_register_static(&armsse_cpuid_info); | |
134 | } | |
135 | ||
136 | type_init(armsse_cpuid_register_types); |