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7eb0c8e8 BS |
1 | /* |
2 | * QEMU Sparc Sun4m ECC memory controller emulation | |
3 | * | |
4 | * Copyright (c) 2007 Robert Reif | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
49e66373 | 24 | |
0d1c9782 | 25 | #include "qemu/osdep.h" |
64552b6b | 26 | #include "hw/irq.h" |
a27bd6c7 | 27 | #include "hw/qdev-properties.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
d6454270 | 29 | #include "migration/vmstate.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
97bf4851 | 31 | #include "trace.h" |
db1015e9 | 32 | #include "qom/object.h" |
7eb0c8e8 BS |
33 | |
34 | /* There are 3 versions of this chip used in SMP sun4m systems: | |
35 | * MCC (version 0, implementation 0) SS-600MP | |
36 | * EMC (version 0, implementation 1) SS-10 | |
37 | * SMC (version 0, implementation 2) SS-10SX and SS-20 | |
5ac574c4 BS |
38 | * |
39 | * Chipset docs: | |
40 | * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, | |
41 | * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf | |
7eb0c8e8 BS |
42 | */ |
43 | ||
0bb3602c BS |
44 | #define ECC_MCC 0x00000000 |
45 | #define ECC_EMC 0x10000000 | |
46 | #define ECC_SMC 0x20000000 | |
47 | ||
8f2ad0a3 BS |
48 | /* Register indexes */ |
49 | #define ECC_MER 0 /* Memory Enable Register */ | |
50 | #define ECC_MDR 1 /* Memory Delay Register */ | |
51 | #define ECC_MFSR 2 /* Memory Fault Status Register */ | |
52 | #define ECC_VCR 3 /* Video Configuration Register */ | |
53 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ | |
54 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ | |
55 | #define ECC_DR 6 /* Diagnostic Register */ | |
56 | #define ECC_ECR0 7 /* Event Count Register 0 */ | |
57 | #define ECC_ECR1 8 /* Event Count Register 1 */ | |
7eb0c8e8 BS |
58 | |
59 | /* ECC fault control register */ | |
dd53ded3 | 60 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
77f193da BS |
61 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
62 | correctable errors */ | |
dd53ded3 BS |
63 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
64 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ | |
65 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ | |
66 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ | |
67 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ | |
68 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ | |
69 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ | |
70 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ | |
0bb3602c | 71 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
dd53ded3 | 72 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
0bb3602c | 73 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
77f193da | 74 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
dd53ded3 BS |
75 | #define ECC_MER_VER 0x0f000000 /* Version */ |
76 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ | |
0bb3602c BS |
77 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
78 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ | |
79 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ | |
dd53ded3 BS |
80 | |
81 | /* ECC memory delay register */ | |
82 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ | |
83 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ | |
84 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ | |
85 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ | |
86 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ | |
87 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ | |
88 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ | |
89 | #define ECC_MDR_MASK 0x7fffffff | |
7eb0c8e8 BS |
90 | |
91 | /* ECC fault status register */ | |
dd53ded3 BS |
92 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
93 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ | |
94 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ | |
95 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ | |
96 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ | |
97 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ | |
98 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ | |
99 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ | |
7eb0c8e8 BS |
100 | |
101 | /* ECC fault address register 0 */ | |
dd53ded3 BS |
102 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
103 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ | |
104 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ | |
105 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ | |
106 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ | |
107 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ | |
108 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ | |
109 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ | |
110 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ | |
7eb0c8e8 BS |
111 | |
112 | /* ECC diagnostic register */ | |
dd53ded3 BS |
113 | #define ECC_DR_CBX 0x00000001 |
114 | #define ECC_DR_CB0 0x00000002 | |
115 | #define ECC_DR_CB1 0x00000004 | |
116 | #define ECC_DR_CB2 0x00000008 | |
117 | #define ECC_DR_CB4 0x00000010 | |
118 | #define ECC_DR_CB8 0x00000020 | |
119 | #define ECC_DR_CB16 0x00000040 | |
120 | #define ECC_DR_CB32 0x00000080 | |
121 | #define ECC_DR_DMODE 0x00000c00 | |
122 | ||
123 | #define ECC_NREGS 9 | |
7eb0c8e8 | 124 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
dd53ded3 BS |
125 | |
126 | #define ECC_DIAG_SIZE 4 | |
127 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) | |
7eb0c8e8 | 128 | |
100bb15c | 129 | #define TYPE_ECC_MEMCTL "eccmemctl" |
db1015e9 | 130 | typedef struct ECCState ECCState; |
100bb15c AF |
131 | #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL) |
132 | ||
db1015e9 | 133 | struct ECCState { |
100bb15c AF |
134 | SysBusDevice parent_obj; |
135 | ||
7ef57cca | 136 | MemoryRegion iomem, iomem_diag; |
e42c20b4 | 137 | qemu_irq irq; |
7eb0c8e8 | 138 | uint32_t regs[ECC_NREGS]; |
dd53ded3 | 139 | uint8_t diag[ECC_DIAG_SIZE]; |
0bb3602c | 140 | uint32_t version; |
db1015e9 | 141 | }; |
7eb0c8e8 | 142 | |
a8170e5e | 143 | static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, |
7ef57cca | 144 | unsigned size) |
7eb0c8e8 BS |
145 | { |
146 | ECCState *s = opaque; | |
147 | ||
e64d7d59 | 148 | switch (addr >> 2) { |
dd53ded3 | 149 | case ECC_MER: |
0bb3602c BS |
150 | if (s->version == ECC_MCC) |
151 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); | |
152 | else if (s->version == ECC_EMC) | |
153 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); | |
154 | else if (s->version == ECC_SMC) | |
155 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); | |
97bf4851 | 156 | trace_ecc_mem_writel_mer(val); |
7eb0c8e8 | 157 | break; |
dd53ded3 | 158 | case ECC_MDR: |
8f2ad0a3 | 159 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
97bf4851 | 160 | trace_ecc_mem_writel_mdr(val); |
7eb0c8e8 | 161 | break; |
dd53ded3 | 162 | case ECC_MFSR: |
8f2ad0a3 | 163 | s->regs[ECC_MFSR] = val; |
0bb3602c | 164 | qemu_irq_lower(s->irq); |
97bf4851 | 165 | trace_ecc_mem_writel_mfsr(val); |
7eb0c8e8 | 166 | break; |
dd53ded3 | 167 | case ECC_VCR: |
8f2ad0a3 | 168 | s->regs[ECC_VCR] = val; |
97bf4851 | 169 | trace_ecc_mem_writel_vcr(val); |
7eb0c8e8 | 170 | break; |
dd53ded3 | 171 | case ECC_DR: |
8f2ad0a3 | 172 | s->regs[ECC_DR] = val; |
97bf4851 | 173 | trace_ecc_mem_writel_dr(val); |
dd53ded3 BS |
174 | break; |
175 | case ECC_ECR0: | |
8f2ad0a3 | 176 | s->regs[ECC_ECR0] = val; |
97bf4851 | 177 | trace_ecc_mem_writel_ecr0(val); |
7eb0c8e8 | 178 | break; |
dd53ded3 | 179 | case ECC_ECR1: |
8f2ad0a3 | 180 | s->regs[ECC_ECR0] = val; |
97bf4851 | 181 | trace_ecc_mem_writel_ecr1(val); |
7eb0c8e8 BS |
182 | break; |
183 | } | |
184 | } | |
185 | ||
a8170e5e | 186 | static uint64_t ecc_mem_read(void *opaque, hwaddr addr, |
7ef57cca | 187 | unsigned size) |
7eb0c8e8 BS |
188 | { |
189 | ECCState *s = opaque; | |
190 | uint32_t ret = 0; | |
191 | ||
e64d7d59 | 192 | switch (addr >> 2) { |
dd53ded3 | 193 | case ECC_MER: |
8f2ad0a3 | 194 | ret = s->regs[ECC_MER]; |
97bf4851 | 195 | trace_ecc_mem_readl_mer(ret); |
7eb0c8e8 | 196 | break; |
dd53ded3 | 197 | case ECC_MDR: |
8f2ad0a3 | 198 | ret = s->regs[ECC_MDR]; |
97bf4851 | 199 | trace_ecc_mem_readl_mdr(ret); |
7eb0c8e8 | 200 | break; |
dd53ded3 | 201 | case ECC_MFSR: |
8f2ad0a3 | 202 | ret = s->regs[ECC_MFSR]; |
97bf4851 | 203 | trace_ecc_mem_readl_mfsr(ret); |
7eb0c8e8 | 204 | break; |
dd53ded3 | 205 | case ECC_VCR: |
8f2ad0a3 | 206 | ret = s->regs[ECC_VCR]; |
97bf4851 | 207 | trace_ecc_mem_readl_vcr(ret); |
7eb0c8e8 | 208 | break; |
dd53ded3 | 209 | case ECC_MFAR0: |
8f2ad0a3 | 210 | ret = s->regs[ECC_MFAR0]; |
97bf4851 | 211 | trace_ecc_mem_readl_mfar0(ret); |
7eb0c8e8 | 212 | break; |
dd53ded3 | 213 | case ECC_MFAR1: |
8f2ad0a3 | 214 | ret = s->regs[ECC_MFAR1]; |
97bf4851 | 215 | trace_ecc_mem_readl_mfar1(ret); |
7eb0c8e8 | 216 | break; |
dd53ded3 | 217 | case ECC_DR: |
8f2ad0a3 | 218 | ret = s->regs[ECC_DR]; |
97bf4851 | 219 | trace_ecc_mem_readl_dr(ret); |
7eb0c8e8 | 220 | break; |
dd53ded3 | 221 | case ECC_ECR0: |
8f2ad0a3 | 222 | ret = s->regs[ECC_ECR0]; |
97bf4851 | 223 | trace_ecc_mem_readl_ecr0(ret); |
dd53ded3 BS |
224 | break; |
225 | case ECC_ECR1: | |
8f2ad0a3 | 226 | ret = s->regs[ECC_ECR0]; |
97bf4851 | 227 | trace_ecc_mem_readl_ecr1(ret); |
7eb0c8e8 BS |
228 | break; |
229 | } | |
230 | return ret; | |
231 | } | |
232 | ||
7ef57cca AK |
233 | static const MemoryRegionOps ecc_mem_ops = { |
234 | .read = ecc_mem_read, | |
235 | .write = ecc_mem_write, | |
236 | .endianness = DEVICE_NATIVE_ENDIAN, | |
237 | .valid = { | |
238 | .min_access_size = 4, | |
239 | .max_access_size = 4, | |
240 | }, | |
7eb0c8e8 BS |
241 | }; |
242 | ||
a8170e5e | 243 | static void ecc_diag_mem_write(void *opaque, hwaddr addr, |
7ef57cca | 244 | uint64_t val, unsigned size) |
dd53ded3 BS |
245 | { |
246 | ECCState *s = opaque; | |
247 | ||
97bf4851 | 248 | trace_ecc_diag_mem_writeb(addr, val); |
dd53ded3 BS |
249 | s->diag[addr & ECC_DIAG_MASK] = val; |
250 | } | |
251 | ||
a8170e5e | 252 | static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, |
7ef57cca | 253 | unsigned size) |
dd53ded3 BS |
254 | { |
255 | ECCState *s = opaque; | |
e64d7d59 BS |
256 | uint32_t ret = s->diag[(int)addr]; |
257 | ||
97bf4851 | 258 | trace_ecc_diag_mem_readb(addr, ret); |
dd53ded3 BS |
259 | return ret; |
260 | } | |
261 | ||
7ef57cca AK |
262 | static const MemoryRegionOps ecc_diag_mem_ops = { |
263 | .read = ecc_diag_mem_read, | |
264 | .write = ecc_diag_mem_write, | |
265 | .endianness = DEVICE_NATIVE_ENDIAN, | |
266 | .valid = { | |
267 | .min_access_size = 1, | |
268 | .max_access_size = 1, | |
269 | }, | |
dd53ded3 BS |
270 | }; |
271 | ||
c21011a9 BS |
272 | static const VMStateDescription vmstate_ecc = { |
273 | .name ="ECC", | |
274 | .version_id = 3, | |
275 | .minimum_version_id = 3, | |
35d08458 | 276 | .fields = (VMStateField[]) { |
c21011a9 BS |
277 | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), |
278 | VMSTATE_BUFFER(diag, ECCState), | |
279 | VMSTATE_UINT32(version, ECCState), | |
280 | VMSTATE_END_OF_LIST() | |
281 | } | |
282 | }; | |
7eb0c8e8 | 283 | |
0284dc54 | 284 | static void ecc_reset(DeviceState *d) |
7eb0c8e8 | 285 | { |
100bb15c | 286 | ECCState *s = ECC_MEMCTL(d); |
7eb0c8e8 | 287 | |
100bb15c | 288 | if (s->version == ECC_MCC) { |
0bb3602c | 289 | s->regs[ECC_MER] &= ECC_MER_REU; |
100bb15c | 290 | } else { |
0bb3602c BS |
291 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
292 | ECC_MER_DCI); | |
100bb15c | 293 | } |
dd53ded3 BS |
294 | s->regs[ECC_MDR] = 0x20; |
295 | s->regs[ECC_MFSR] = 0; | |
296 | s->regs[ECC_VCR] = 0; | |
297 | s->regs[ECC_MFAR0] = 0x07c00000; | |
298 | s->regs[ECC_MFAR1] = 0; | |
299 | s->regs[ECC_DR] = 0; | |
300 | s->regs[ECC_ECR0] = 0; | |
301 | s->regs[ECC_ECR1] = 0; | |
7eb0c8e8 BS |
302 | } |
303 | ||
b229a576 | 304 | static void ecc_init(Object *obj) |
7eb0c8e8 | 305 | { |
b229a576 XZ |
306 | ECCState *s = ECC_MEMCTL(obj); |
307 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
7eb0c8e8 | 308 | |
49e66373 | 309 | sysbus_init_irq(dev, &s->irq); |
b229a576 XZ |
310 | |
311 | memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE); | |
750ecd44 | 312 | sysbus_init_mmio(dev, &s->iomem); |
b229a576 XZ |
313 | } |
314 | ||
315 | static void ecc_realize(DeviceState *dev, Error **errp) | |
316 | { | |
317 | ECCState *s = ECC_MEMCTL(dev); | |
318 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
319 | ||
320 | s->regs[0] = s->version; | |
49e66373 BS |
321 | |
322 | if (s->version == ECC_MCC) { // SS-600MP only | |
3c161542 | 323 | memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, |
7ef57cca | 324 | "ecc.diag", ECC_DIAG_SIZE); |
b229a576 | 325 | sysbus_init_mmio(sbd, &s->iomem_diag); |
dd53ded3 | 326 | } |
7eb0c8e8 | 327 | } |
49e66373 | 328 | |
999e12bb | 329 | static Property ecc_properties[] = { |
c7bcc85d | 330 | DEFINE_PROP_UINT32("version", ECCState, version, -1), |
999e12bb AL |
331 | DEFINE_PROP_END_OF_LIST(), |
332 | }; | |
333 | ||
334 | static void ecc_class_init(ObjectClass *klass, void *data) | |
335 | { | |
39bffca2 | 336 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 337 | |
b229a576 | 338 | dc->realize = ecc_realize; |
39bffca2 AL |
339 | dc->reset = ecc_reset; |
340 | dc->vmsd = &vmstate_ecc; | |
4f67d30b | 341 | device_class_set_props(dc, ecc_properties); |
999e12bb AL |
342 | } |
343 | ||
8c43a6f0 | 344 | static const TypeInfo ecc_info = { |
100bb15c | 345 | .name = TYPE_ECC_MEMCTL, |
39bffca2 AL |
346 | .parent = TYPE_SYS_BUS_DEVICE, |
347 | .instance_size = sizeof(ECCState), | |
b229a576 | 348 | .instance_init = ecc_init, |
39bffca2 | 349 | .class_init = ecc_class_init, |
ee6847d1 GH |
350 | }; |
351 | ||
352 | ||
83f7d43a | 353 | static void ecc_register_types(void) |
49e66373 | 354 | { |
39bffca2 | 355 | type_register_static(&ecc_info); |
49e66373 BS |
356 | } |
357 | ||
83f7d43a | 358 | type_init(ecc_register_types) |