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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <cam@cs.ualberta.ca> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0b8fa32f | 19 | |
0d1c9782 | 20 | #include "qemu/osdep.h" |
519abcdf | 21 | #include "qemu/units.h" |
da34e65c | 22 | #include "qapi/error.h" |
f348b6d1 | 23 | #include "qemu/cutils.h" |
83c9f4ca | 24 | #include "hw/pci/pci.h" |
a27bd6c7 | 25 | #include "hw/qdev-properties.h" |
660c97ee | 26 | #include "hw/pci/msi.h" |
83c9f4ca | 27 | #include "hw/pci/msix.h" |
9c17d615 | 28 | #include "sysemu/kvm.h" |
795c40b8 | 29 | #include "migration/blocker.h" |
d6454270 | 30 | #include "migration/vmstate.h" |
d49b6836 | 31 | #include "qemu/error-report.h" |
1de7afc9 | 32 | #include "qemu/event_notifier.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
5503e285 | 34 | #include "qom/object_interfaces.h" |
4d43a603 | 35 | #include "chardev/char-fe.h" |
d9453c93 | 36 | #include "sysemu/hostmem.h" |
5400c02b | 37 | #include "sysemu/qtest.h" |
d9453c93 | 38 | #include "qapi/visitor.h" |
6cbf4c8c | 39 | |
5105b1d8 DM |
40 | #include "hw/misc/ivshmem.h" |
41 | ||
b8ef62a9 PB |
42 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
43 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
44 | ||
cd9953f7 | 45 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
46 | #define IVSHMEM_IOEVENTFD 0 |
47 | #define IVSHMEM_MSI 1 | |
48 | ||
6cbf4c8c CM |
49 | #define IVSHMEM_REG_BAR_SIZE 0x100 |
50 | ||
a4fa93bf MA |
51 | #define IVSHMEM_DEBUG 0 |
52 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
53 | do { \ | |
54 | if (IVSHMEM_DEBUG) { \ | |
55 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
56 | } \ | |
57 | } while (0) | |
6cbf4c8c | 58 | |
5400c02b MA |
59 | #define TYPE_IVSHMEM_COMMON "ivshmem-common" |
60 | #define IVSHMEM_COMMON(obj) \ | |
61 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON) | |
62 | ||
63 | #define TYPE_IVSHMEM_PLAIN "ivshmem-plain" | |
64 | #define IVSHMEM_PLAIN(obj) \ | |
65 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN) | |
66 | ||
67 | #define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell" | |
68 | #define IVSHMEM_DOORBELL(obj) \ | |
69 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL) | |
70 | ||
eb3fedf3 PC |
71 | #define TYPE_IVSHMEM "ivshmem" |
72 | #define IVSHMEM(obj) \ | |
73 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
74 | ||
6cbf4c8c CM |
75 | typedef struct Peer { |
76 | int nb_eventfds; | |
563027cc | 77 | EventNotifier *eventfds; |
6cbf4c8c CM |
78 | } Peer; |
79 | ||
0f57350e | 80 | typedef struct MSIVector { |
6cbf4c8c | 81 | PCIDevice *pdev; |
660c97ee | 82 | int virq; |
089fd803 | 83 | bool unmasked; |
0f57350e | 84 | } MSIVector; |
6cbf4c8c CM |
85 | |
86 | typedef struct IVShmemState { | |
b7578eaa AF |
87 | /*< private >*/ |
88 | PCIDevice parent_obj; | |
89 | /*< public >*/ | |
90 | ||
ddc85284 MA |
91 | uint32_t features; |
92 | ||
93 | /* exactly one of these two may be set */ | |
94 | HostMemoryBackend *hostmem; /* with interrupts */ | |
becdfa00 | 95 | CharBackend server_chr; /* without interrupts */ |
ddc85284 MA |
96 | |
97 | /* registers */ | |
6cbf4c8c CM |
98 | uint32_t intrmask; |
99 | uint32_t intrstatus; | |
ddc85284 | 100 | int vm_id; |
6cbf4c8c | 101 | |
ddc85284 MA |
102 | /* BARs */ |
103 | MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */ | |
c2d8019c MA |
104 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
105 | MemoryRegion server_bar2; /* used with server_chr */ | |
6cbf4c8c | 106 | |
ddc85284 | 107 | /* interrupt support */ |
6cbf4c8c | 108 | Peer *peers; |
cd9953f7 | 109 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c | 110 | uint32_t vectors; |
0f57350e | 111 | MSIVector *msi_vectors; |
ee276391 MA |
112 | uint64_t msg_buf; /* buffer for receiving server messages */ |
113 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 114 | |
ddc85284 | 115 | /* migration stuff */ |
2a845da7 | 116 | OnOffAuto master; |
38e0735e | 117 | Error *migration_blocker; |
6cbf4c8c CM |
118 | } IVShmemState; |
119 | ||
120 | /* registers for the Inter-VM shared memory device */ | |
121 | enum ivshmem_registers { | |
122 | INTRMASK = 0, | |
123 | INTRSTATUS = 4, | |
124 | IVPOSITION = 8, | |
125 | DOORBELL = 12, | |
126 | }; | |
127 | ||
128 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
129 | unsigned int feature) { | |
130 | return (ivs->features & (1 << feature)); | |
131 | } | |
132 | ||
2a845da7 MA |
133 | static inline bool ivshmem_is_master(IVShmemState *s) |
134 | { | |
135 | assert(s->master != ON_OFF_AUTO_AUTO); | |
136 | return s->master == ON_OFF_AUTO_ON; | |
137 | } | |
138 | ||
d8a5da07 | 139 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 140 | { |
b7578eaa | 141 | PCIDevice *d = PCI_DEVICE(s); |
434ad76d | 142 | uint32_t isr = s->intrstatus & s->intrmask; |
6cbf4c8c | 143 | |
5400c02b MA |
144 | /* |
145 | * Do nothing unless the device actually uses INTx. Here's how | |
146 | * the device variants signal interrupts, what they put in PCI | |
147 | * config space: | |
148 | * Device variant Interrupt Interrupt Pin MSI-X cap. | |
149 | * ivshmem-plain none 0 no | |
150 | * ivshmem-doorbell MSI-X 1 yes(1) | |
151 | * ivshmem,msi=off INTx 1 no | |
152 | * ivshmem,msi=on MSI-X 1(2) yes(1) | |
153 | * (1) if guest enabled MSI-X | |
154 | * (2) the device lies | |
155 | * Leads to the condition for doing nothing: | |
156 | */ | |
157 | if (ivshmem_has_feature(s, IVSHMEM_MSI) | |
158 | || !d->config[PCI_INTERRUPT_PIN]) { | |
2d1d422d MA |
159 | return; |
160 | } | |
161 | ||
6cbf4c8c CM |
162 | /* don't print ISR resets */ |
163 | if (isr) { | |
164 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 165 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
166 | } |
167 | ||
434ad76d | 168 | pci_set_irq(d, isr != 0); |
6cbf4c8c CM |
169 | } |
170 | ||
171 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
172 | { | |
173 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
174 | ||
175 | s->intrmask = val; | |
d8a5da07 | 176 | ivshmem_update_irq(s); |
6cbf4c8c CM |
177 | } |
178 | ||
179 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
180 | { | |
181 | uint32_t ret = s->intrmask; | |
182 | ||
183 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
184 | return ret; |
185 | } | |
186 | ||
187 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
188 | { | |
189 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
190 | ||
191 | s->intrstatus = val; | |
d8a5da07 | 192 | ivshmem_update_irq(s); |
6cbf4c8c CM |
193 | } |
194 | ||
195 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
196 | { | |
197 | uint32_t ret = s->intrstatus; | |
198 | ||
199 | /* reading ISR clears all interrupts */ | |
200 | s->intrstatus = 0; | |
d8a5da07 | 201 | ivshmem_update_irq(s); |
6cbf4c8c CM |
202 | return ret; |
203 | } | |
204 | ||
a8170e5e | 205 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 206 | uint64_t val, unsigned size) |
6cbf4c8c CM |
207 | { |
208 | IVShmemState *s = opaque; | |
209 | ||
6cbf4c8c CM |
210 | uint16_t dest = val >> 16; |
211 | uint16_t vector = val & 0xff; | |
212 | ||
213 | addr &= 0xfc; | |
214 | ||
215 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
216 | switch (addr) | |
217 | { | |
218 | case INTRMASK: | |
219 | ivshmem_IntrMask_write(s, val); | |
220 | break; | |
221 | ||
222 | case INTRSTATUS: | |
223 | ivshmem_IntrStatus_write(s, val); | |
224 | break; | |
225 | ||
226 | case DOORBELL: | |
227 | /* check that dest VM ID is reasonable */ | |
95c8425c | 228 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
229 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
230 | break; | |
231 | } | |
232 | ||
233 | /* check doorbell range */ | |
1b27d7a1 | 234 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
235 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
236 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
237 | } else { |
238 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
239 | vector, dest); | |
6cbf4c8c CM |
240 | } |
241 | break; | |
242 | default: | |
f59bb378 | 243 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
244 | } |
245 | } | |
246 | ||
a8170e5e | 247 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 248 | unsigned size) |
6cbf4c8c CM |
249 | { |
250 | ||
251 | IVShmemState *s = opaque; | |
252 | uint32_t ret; | |
253 | ||
254 | switch (addr) | |
255 | { | |
256 | case INTRMASK: | |
257 | ret = ivshmem_IntrMask_read(s); | |
258 | break; | |
259 | ||
260 | case INTRSTATUS: | |
261 | ret = ivshmem_IntrStatus_read(s); | |
262 | break; | |
263 | ||
264 | case IVPOSITION: | |
1309cf44 | 265 | ret = s->vm_id; |
6cbf4c8c CM |
266 | break; |
267 | ||
268 | default: | |
269 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
270 | ret = 0; | |
271 | } | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
cb06608e AK |
276 | static const MemoryRegionOps ivshmem_mmio_ops = { |
277 | .read = ivshmem_io_read, | |
278 | .write = ivshmem_io_write, | |
279 | .endianness = DEVICE_NATIVE_ENDIAN, | |
280 | .impl = { | |
281 | .min_access_size = 4, | |
282 | .max_access_size = 4, | |
283 | }, | |
6cbf4c8c CM |
284 | }; |
285 | ||
9940c323 MAL |
286 | static void ivshmem_vector_notify(void *opaque) |
287 | { | |
0f57350e | 288 | MSIVector *entry = opaque; |
6cbf4c8c | 289 | PCIDevice *pdev = entry->pdev; |
5400c02b | 290 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
0f57350e | 291 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
292 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
293 | ||
294 | if (!event_notifier_test_and_clear(n)) { | |
295 | return; | |
296 | } | |
6cbf4c8c | 297 | |
d160f3f7 | 298 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 299 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
300 | if (msix_enabled(pdev)) { |
301 | msix_notify(pdev, vector); | |
302 | } | |
9940c323 MAL |
303 | } else { |
304 | ivshmem_IntrStatus_write(s, 1); | |
305 | } | |
6cbf4c8c CM |
306 | } |
307 | ||
660c97ee MAL |
308 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
309 | MSIMessage msg) | |
310 | { | |
5400c02b | 311 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
312 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
313 | MSIVector *v = &s->msi_vectors[vector]; | |
314 | int ret; | |
315 | ||
316 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
e6a354be LP |
317 | if (!v->pdev) { |
318 | error_report("ivshmem: vector %d route does not exist", vector); | |
319 | return -EINVAL; | |
320 | } | |
089fd803 | 321 | assert(!v->unmasked); |
660c97ee MAL |
322 | |
323 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
324 | if (ret < 0) { | |
325 | return ret; | |
326 | } | |
3f1fea0f | 327 | kvm_irqchip_commit_routes(kvm_state); |
660c97ee | 328 | |
089fd803 LP |
329 | ret = kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); |
330 | if (ret < 0) { | |
331 | return ret; | |
332 | } | |
333 | v->unmasked = true; | |
334 | ||
335 | return 0; | |
660c97ee MAL |
336 | } |
337 | ||
338 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
339 | { | |
5400c02b | 340 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee | 341 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
e6a354be | 342 | MSIVector *v = &s->msi_vectors[vector]; |
660c97ee MAL |
343 | int ret; |
344 | ||
345 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
e6a354be LP |
346 | if (!v->pdev) { |
347 | error_report("ivshmem: vector %d route does not exist", vector); | |
348 | return; | |
349 | } | |
089fd803 | 350 | assert(v->unmasked); |
660c97ee | 351 | |
e6a354be | 352 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, v->virq); |
089fd803 | 353 | if (ret < 0) { |
660c97ee | 354 | error_report("remove_irqfd_notifier_gsi failed"); |
089fd803 | 355 | return; |
660c97ee | 356 | } |
089fd803 | 357 | v->unmasked = false; |
660c97ee MAL |
358 | } |
359 | ||
360 | static void ivshmem_vector_poll(PCIDevice *dev, | |
361 | unsigned int vector_start, | |
362 | unsigned int vector_end) | |
363 | { | |
5400c02b | 364 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
365 | unsigned int vector; |
366 | ||
367 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
368 | ||
369 | vector_end = MIN(vector_end, s->vectors); | |
370 | ||
371 | for (vector = vector_start; vector < vector_end; vector++) { | |
372 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
373 | ||
374 | if (!msix_is_masked(dev, vector)) { | |
375 | continue; | |
376 | } | |
377 | ||
378 | if (event_notifier_test_and_clear(notifier)) { | |
379 | msix_set_pending(dev, vector); | |
380 | } | |
381 | } | |
382 | } | |
383 | ||
9940c323 MAL |
384 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
385 | int vector) | |
6cbf4c8c | 386 | { |
563027cc | 387 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 388 | |
3c27969b | 389 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 390 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 391 | |
9940c323 MAL |
392 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
393 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
394 | } |
395 | ||
563027cc PB |
396 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
397 | { | |
398 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
399 | DOORBELL, | |
400 | 4, | |
401 | true, | |
402 | (posn << 16) | i, | |
753d5e14 | 403 | &s->peers[posn].eventfds[i]); |
563027cc PB |
404 | } |
405 | ||
406 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
407 | { | |
408 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
409 | DOORBELL, | |
410 | 4, | |
411 | true, | |
412 | (posn << 16) | i, | |
753d5e14 | 413 | &s->peers[posn].eventfds[i]); |
563027cc PB |
414 | } |
415 | ||
f456179f | 416 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 417 | { |
f456179f | 418 | int i, n; |
6cbf4c8c | 419 | |
9db51b4d | 420 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 421 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 422 | |
9db51b4d MA |
423 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
424 | memory_region_transaction_begin(); | |
425 | for (i = 0; i < n; i++) { | |
426 | ivshmem_del_eventfd(s, posn, i); | |
427 | } | |
428 | memory_region_transaction_commit(); | |
b6a1f3a5 | 429 | } |
9db51b4d | 430 | |
f456179f | 431 | for (i = 0; i < n; i++) { |
563027cc | 432 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
433 | } |
434 | ||
7267c094 | 435 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
436 | s->peers[posn].nb_eventfds = 0; |
437 | } | |
438 | ||
cd9953f7 | 439 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 440 | { |
cd9953f7 MA |
441 | int old_nb_peers = s->nb_peers; |
442 | int i; | |
6cbf4c8c | 443 | |
cd9953f7 MA |
444 | assert(nb_peers > old_nb_peers); |
445 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 446 | |
cd9953f7 MA |
447 | s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer)); |
448 | s->nb_peers = nb_peers; | |
1300b273 | 449 | |
cd9953f7 MA |
450 | for (i = old_nb_peers; i < nb_peers; i++) { |
451 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
452 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
453 | } |
454 | } | |
455 | ||
1309cf44 MA |
456 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
457 | Error **errp) | |
660c97ee MAL |
458 | { |
459 | PCIDevice *pdev = PCI_DEVICE(s); | |
660c97ee MAL |
460 | int ret; |
461 | ||
462 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 463 | assert(!s->msi_vectors[vector].pdev); |
660c97ee | 464 | |
d1f6af6a | 465 | ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev); |
660c97ee | 466 | if (ret < 0) { |
1309cf44 MA |
467 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
468 | return; | |
660c97ee MAL |
469 | } |
470 | ||
471 | s->msi_vectors[vector].virq = ret; | |
472 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
473 | } |
474 | ||
1309cf44 | 475 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
476 | { |
477 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
478 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
479 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
480 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 481 | Error *err = NULL; |
660c97ee MAL |
482 | |
483 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
484 | ||
485 | if (!with_irqfd) { | |
97553976 | 486 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 487 | watch_vector_notifier(s, n, vector); |
660c97ee | 488 | } else if (msix_enabled(pdev)) { |
97553976 | 489 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
490 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
491 | if (err) { | |
492 | error_propagate(errp, err); | |
660c97ee MAL |
493 | return; |
494 | } | |
495 | ||
496 | if (!msix_is_masked(pdev, vector)) { | |
497 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
498 | s->msi_vectors[vector].virq); | |
1309cf44 | 499 | /* TODO handle error */ |
660c97ee MAL |
500 | } |
501 | } else { | |
502 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 503 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
504 | } |
505 | } | |
506 | ||
1309cf44 | 507 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 508 | { |
8381d89b | 509 | Error *local_err = NULL; |
8baeb22b | 510 | struct stat buf; |
5400c02b | 511 | size_t size; |
6cbf4c8c | 512 | |
c2d8019c | 513 | if (s->ivshmem_bar2) { |
1309cf44 | 514 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 515 | close(fd); |
0f14fd71 | 516 | return; |
a2e9011b SH |
517 | } |
518 | ||
8baeb22b MA |
519 | if (fstat(fd, &buf) < 0) { |
520 | error_setg_errno(errp, errno, | |
521 | "can't determine size of shared memory sent by server"); | |
522 | close(fd); | |
523 | return; | |
524 | } | |
525 | ||
5400c02b MA |
526 | size = buf.st_size; |
527 | ||
ca0b7566 | 528 | /* mmap the region and map into the BAR2 */ |
8381d89b MAL |
529 | memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s), |
530 | "ivshmem.bar2", size, true, fd, &local_err); | |
531 | if (local_err) { | |
532 | error_propagate(errp, local_err); | |
ca0b7566 | 533 | return; |
6cbf4c8c | 534 | } |
8381d89b | 535 | |
c2d8019c | 536 | s->ivshmem_bar2 = &s->server_bar2; |
ca0b7566 MA |
537 | } |
538 | ||
1309cf44 MA |
539 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
540 | Error **errp) | |
ca0b7566 MA |
541 | { |
542 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 543 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 544 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
545 | return; |
546 | } | |
ca0b7566 MA |
547 | close_peer_eventfds(s, posn); |
548 | } | |
6cbf4c8c | 549 | |
1309cf44 MA |
550 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
551 | Error **errp) | |
ca0b7566 MA |
552 | { |
553 | Peer *peer = &s->peers[posn]; | |
554 | int vector; | |
9a2f0e64 | 555 | |
ca0b7566 MA |
556 | /* |
557 | * The N-th connect message for this peer comes with the file | |
558 | * descriptor for vector N-1. Count messages to find the vector. | |
559 | */ | |
560 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
561 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
562 | s->vectors); | |
ca0b7566 | 563 | close(fd); |
6f8a16d5 | 564 | return; |
6cbf4c8c | 565 | } |
ca0b7566 | 566 | vector = peer->nb_eventfds++; |
6cbf4c8c | 567 | |
ca0b7566 MA |
568 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
569 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
570 | fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */ | |
945001a1 | 571 | |
ca0b7566 | 572 | if (posn == s->vm_id) { |
1309cf44 MA |
573 | setup_interrupt(s, vector, errp); |
574 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 575 | } |
6cbf4c8c | 576 | |
ca0b7566 MA |
577 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
578 | ivshmem_add_eventfd(s, posn, vector); | |
579 | } | |
580 | } | |
6cbf4c8c | 581 | |
1309cf44 | 582 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
583 | { |
584 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 585 | |
ca0b7566 | 586 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 587 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 588 | close(fd); |
6cbf4c8c CM |
589 | return; |
590 | } | |
591 | ||
ca0b7566 | 592 | if (msg == -1) { |
1309cf44 | 593 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
594 | return; |
595 | } | |
596 | ||
ca0b7566 MA |
597 | if (msg >= s->nb_peers) { |
598 | resize_peers(s, msg + 1); | |
599 | } | |
6cbf4c8c | 600 | |
ca0b7566 | 601 | if (fd >= 0) { |
1309cf44 | 602 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 603 | } else { |
1309cf44 | 604 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 605 | } |
ca0b7566 | 606 | } |
6cbf4c8c | 607 | |
ee276391 MA |
608 | static int ivshmem_can_receive(void *opaque) |
609 | { | |
610 | IVShmemState *s = opaque; | |
611 | ||
612 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
613 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
614 | } | |
615 | ||
ca0b7566 MA |
616 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
617 | { | |
618 | IVShmemState *s = opaque; | |
1309cf44 | 619 | Error *err = NULL; |
ca0b7566 MA |
620 | int fd; |
621 | int64_t msg; | |
622 | ||
ee276391 MA |
623 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
624 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
625 | s->msg_buffered_bytes += size; | |
626 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 627 | return; |
6cbf4c8c | 628 | } |
ee276391 MA |
629 | msg = le64_to_cpu(s->msg_buf); |
630 | s->msg_buffered_bytes = 0; | |
ca0b7566 | 631 | |
5345fdb4 | 632 | fd = qemu_chr_fe_get_msgfd(&s->server_chr); |
ca0b7566 | 633 | |
1309cf44 MA |
634 | process_msg(s, msg, fd, &err); |
635 | if (err) { | |
636 | error_report_err(err); | |
637 | } | |
6cbf4c8c CM |
638 | } |
639 | ||
1309cf44 | 640 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 641 | { |
3a55fc0f MA |
642 | int64_t msg; |
643 | int n, ret; | |
644 | ||
645 | n = 0; | |
646 | do { | |
5345fdb4 MAL |
647 | ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n, |
648 | sizeof(msg) - n); | |
b7b1e9dd PMD |
649 | if (ret < 0) { |
650 | if (ret == -EINTR) { | |
651 | continue; | |
652 | } | |
1309cf44 | 653 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
654 | return INT64_MIN; |
655 | } | |
656 | n += ret; | |
657 | } while (n < sizeof(msg)); | |
5105b1d8 | 658 | |
5345fdb4 | 659 | *pfd = qemu_chr_fe_get_msgfd(&s->server_chr); |
51af0ec9 | 660 | return le64_to_cpu(msg); |
3a55fc0f | 661 | } |
5105b1d8 | 662 | |
1309cf44 | 663 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 664 | { |
1309cf44 | 665 | Error *err = NULL; |
3a55fc0f MA |
666 | int64_t msg; |
667 | int fd; | |
668 | ||
1309cf44 MA |
669 | msg = ivshmem_recv_msg(s, &fd, &err); |
670 | if (err) { | |
671 | error_propagate(errp, err); | |
672 | return; | |
673 | } | |
674 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
675 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
676 | msg, IVSHMEM_PROTOCOL_VERSION); | |
677 | return; | |
678 | } | |
679 | if (fd != -1) { | |
680 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
681 | return; |
682 | } | |
683 | ||
a3feb086 MA |
684 | /* |
685 | * ivshmem-server sends the remaining initial messages in a fixed | |
686 | * order, but the device has always accepted them in any order. | |
687 | * Stay as compatible as practical, just in case people use | |
688 | * servers that behave differently. | |
689 | */ | |
690 | ||
691 | /* | |
692 | * ivshmem_device_spec.txt has always required the ID message | |
693 | * right here, and ivshmem-server has always complied. However, | |
694 | * older versions of the device accepted it out of order, but | |
695 | * broke when an interrupt setup message arrived before it. | |
696 | */ | |
697 | msg = ivshmem_recv_msg(s, &fd, &err); | |
698 | if (err) { | |
699 | error_propagate(errp, err); | |
700 | return; | |
701 | } | |
702 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
703 | error_setg(errp, "server sent invalid ID message"); | |
704 | return; | |
705 | } | |
706 | s->vm_id = msg; | |
707 | ||
3a55fc0f MA |
708 | /* |
709 | * Receive more messages until we got shared memory. | |
710 | */ | |
711 | do { | |
1309cf44 MA |
712 | msg = ivshmem_recv_msg(s, &fd, &err); |
713 | if (err) { | |
714 | error_propagate(errp, err); | |
715 | return; | |
716 | } | |
717 | process_msg(s, msg, fd, &err); | |
718 | if (err) { | |
719 | error_propagate(errp, err); | |
720 | return; | |
721 | } | |
3a55fc0f | 722 | } while (msg != -1); |
1309cf44 MA |
723 | |
724 | /* | |
725 | * This function must either map the shared memory or fail. The | |
726 | * loop above ensures that: it terminates normally only after it | |
727 | * successfully processed the server's shared memory message. | |
728 | * Assert that actually mapped the shared memory: | |
729 | */ | |
c2d8019c | 730 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
731 | } |
732 | ||
4490c711 MT |
733 | /* Select the MSI-X vectors used by device. |
734 | * ivshmem maps events to vectors statically, so | |
735 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 736 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 737 | { |
b7578eaa | 738 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
739 | int i; |
740 | ||
4490c711 | 741 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 742 | msix_vector_use(d, i); |
4490c711 MT |
743 | } |
744 | } | |
745 | ||
a4022791 LP |
746 | static void ivshmem_disable_irqfd(IVShmemState *s); |
747 | ||
6cbf4c8c CM |
748 | static void ivshmem_reset(DeviceState *d) |
749 | { | |
5400c02b | 750 | IVShmemState *s = IVSHMEM_COMMON(d); |
6cbf4c8c | 751 | |
a4022791 LP |
752 | ivshmem_disable_irqfd(s); |
753 | ||
6cbf4c8c | 754 | s->intrstatus = 0; |
972ad215 | 755 | s->intrmask = 0; |
082751e8 MA |
756 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
757 | ivshmem_msix_vector_use(s); | |
758 | } | |
6cbf4c8c CM |
759 | } |
760 | ||
ee640c62 | 761 | static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp) |
4490c711 | 762 | { |
fd47bfe5 MAL |
763 | /* allocate QEMU callback data for receiving interrupts */ |
764 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 765 | |
fd47bfe5 | 766 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
ee640c62 | 767 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) { |
fd47bfe5 MAL |
768 | return -1; |
769 | } | |
1116b539 | 770 | |
fd47bfe5 | 771 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 772 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 773 | } |
4490c711 | 774 | |
d58d7e84 | 775 | return 0; |
6cbf4c8c CM |
776 | } |
777 | ||
0b88dd94 LP |
778 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) |
779 | { | |
780 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
781 | ||
782 | if (s->msi_vectors[vector].pdev == NULL) { | |
783 | return; | |
784 | } | |
785 | ||
786 | /* it was cleaned when masked in the frontend. */ | |
787 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
788 | ||
789 | s->msi_vectors[vector].pdev = NULL; | |
790 | } | |
791 | ||
660c97ee MAL |
792 | static void ivshmem_enable_irqfd(IVShmemState *s) |
793 | { | |
794 | PCIDevice *pdev = PCI_DEVICE(s); | |
795 | int i; | |
796 | ||
797 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
798 | Error *err = NULL; |
799 | ||
800 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
801 | if (err) { | |
802 | error_report_err(err); | |
0b88dd94 | 803 | goto undo; |
1309cf44 | 804 | } |
660c97ee MAL |
805 | } |
806 | ||
807 | if (msix_set_vector_notifiers(pdev, | |
808 | ivshmem_vector_unmask, | |
809 | ivshmem_vector_mask, | |
810 | ivshmem_vector_poll)) { | |
811 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
0b88dd94 | 812 | goto undo; |
660c97ee | 813 | } |
0b88dd94 | 814 | return; |
660c97ee | 815 | |
0b88dd94 LP |
816 | undo: |
817 | while (--i >= 0) { | |
818 | ivshmem_remove_kvm_msi_virq(s, i); | |
660c97ee | 819 | } |
660c97ee MAL |
820 | } |
821 | ||
822 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
823 | { | |
824 | PCIDevice *pdev = PCI_DEVICE(s); | |
825 | int i; | |
826 | ||
0b88dd94 LP |
827 | if (!pdev->msix_vector_use_notifier) { |
828 | return; | |
829 | } | |
830 | ||
089fd803 LP |
831 | msix_unset_vector_notifiers(pdev); |
832 | ||
660c97ee | 833 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { |
089fd803 LP |
834 | /* |
835 | * MSI-X is already disabled here so msix_unset_vector_notifiers() | |
836 | * didn't call our release notifier. Do it now to keep our masks and | |
837 | * unmasks balanced. | |
838 | */ | |
839 | if (s->msi_vectors[i].unmasked) { | |
840 | ivshmem_vector_mask(pdev, i); | |
841 | } | |
660c97ee MAL |
842 | ivshmem_remove_kvm_msi_virq(s, i); |
843 | } | |
844 | ||
660c97ee MAL |
845 | } |
846 | ||
847 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 848 | uint32_t val, int len) |
4490c711 | 849 | { |
5400c02b | 850 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
660c97ee MAL |
851 | int is_enabled, was_enabled = msix_enabled(pdev); |
852 | ||
853 | pci_default_write_config(pdev, address, val, len); | |
854 | is_enabled = msix_enabled(pdev); | |
855 | ||
1309cf44 | 856 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
857 | if (!was_enabled && is_enabled) { |
858 | ivshmem_enable_irqfd(s); | |
859 | } else if (was_enabled && !is_enabled) { | |
860 | ivshmem_disable_irqfd(s); | |
861 | } | |
862 | } | |
4490c711 MT |
863 | } |
864 | ||
5400c02b | 865 | static void ivshmem_common_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 866 | { |
5400c02b | 867 | IVShmemState *s = IVSHMEM_COMMON(dev); |
d855e275 | 868 | Error *err = NULL; |
6cbf4c8c | 869 | uint8_t *pci_conf; |
fe44dc91 | 870 | Error *local_err = NULL; |
6cbf4c8c | 871 | |
6cbf4c8c CM |
872 | /* IRQFD requires MSI */ |
873 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
874 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
875 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
876 | return; | |
6cbf4c8c CM |
877 | } |
878 | ||
b7578eaa | 879 | pci_conf = dev->config; |
6cbf4c8c | 880 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 881 | |
3c161542 | 882 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
883 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
884 | ||
6cbf4c8c | 885 | /* region for registers*/ |
b7578eaa | 886 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 887 | &s->ivshmem_mmio); |
cb06608e | 888 | |
d9453c93 | 889 | if (s->hostmem != NULL) { |
d9453c93 MAL |
890 | IVSHMEM_DPRINTF("using hostmem\n"); |
891 | ||
7943e97b | 892 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem); |
b266f1d1 | 893 | host_memory_backend_set_mapped(s->hostmem, true); |
5503e285 | 894 | } else { |
0ec7b3e7 | 895 | Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr); |
5345fdb4 | 896 | assert(chr); |
6dc64780 | 897 | |
6cbf4c8c | 898 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
5345fdb4 | 899 | chr->filename); |
6cbf4c8c | 900 | |
f456179f | 901 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 902 | resize_peers(s, 16); |
6cbf4c8c | 903 | |
3a55fc0f MA |
904 | /* |
905 | * Receive setup messages from server synchronously. | |
906 | * Older versions did it asynchronously, but that creates a | |
907 | * number of entertaining race conditions. | |
3a55fc0f | 908 | */ |
1309cf44 MA |
909 | ivshmem_recv_setup(s, &err); |
910 | if (err) { | |
911 | error_propagate(errp, err); | |
912 | return; | |
3a55fc0f MA |
913 | } |
914 | ||
62a830b6 MA |
915 | if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) { |
916 | error_setg(errp, | |
917 | "master must connect to the server before any peers"); | |
918 | return; | |
919 | } | |
920 | ||
5345fdb4 | 921 | qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive, |
81517ba3 | 922 | ivshmem_read, NULL, NULL, s, NULL, true); |
1309cf44 | 923 | |
ee640c62 C |
924 | if (ivshmem_setup_interrupts(s, errp) < 0) { |
925 | error_prepend(errp, "Failed to initialize interrupts: "); | |
3a55fc0f MA |
926 | return; |
927 | } | |
d855e275 MA |
928 | } |
929 | ||
2a845da7 MA |
930 | if (s->master == ON_OFF_AUTO_AUTO) { |
931 | s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
932 | } | |
933 | ||
934 | if (!ivshmem_is_master(s)) { | |
d855e275 MA |
935 | error_setg(&s->migration_blocker, |
936 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
fe44dc91 AA |
937 | migrate_add_blocker(s->migration_blocker, &local_err); |
938 | if (local_err) { | |
939 | error_propagate(errp, local_err); | |
940 | error_free(s->migration_blocker); | |
941 | return; | |
942 | } | |
6cbf4c8c | 943 | } |
fe44dc91 AA |
944 | |
945 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); | |
5a0e75f0 TH |
946 | pci_register_bar(PCI_DEVICE(s), 2, |
947 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
948 | PCI_BASE_ADDRESS_MEM_PREFETCH | | |
949 | PCI_BASE_ADDRESS_MEM_TYPE_64, | |
950 | s->ivshmem_bar2); | |
6cbf4c8c CM |
951 | } |
952 | ||
5400c02b MA |
953 | static void ivshmem_exit(PCIDevice *dev) |
954 | { | |
955 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
f64a078d MAL |
956 | int i; |
957 | ||
38e0735e AL |
958 | if (s->migration_blocker) { |
959 | migrate_del_blocker(s->migration_blocker); | |
960 | error_free(s->migration_blocker); | |
961 | } | |
962 | ||
c2d8019c | 963 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 964 | if (!s->hostmem) { |
c2d8019c | 965 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 966 | int fd; |
d9453c93 | 967 | |
5400c02b | 968 | if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) { |
d9453c93 MAL |
969 | error_report("Failed to munmap shared memory %s", |
970 | strerror(errno)); | |
971 | } | |
56a571d9 | 972 | |
4ff87573 | 973 | fd = memory_region_get_fd(s->ivshmem_bar2); |
c2d8019c | 974 | close(fd); |
d9453c93 | 975 | } |
f64a078d | 976 | |
c2d8019c | 977 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
978 | } |
979 | ||
b266f1d1 MA |
980 | if (s->hostmem) { |
981 | host_memory_backend_set_mapped(s->hostmem, false); | |
982 | } | |
983 | ||
f64a078d MAL |
984 | if (s->peers) { |
985 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 986 | close_peer_eventfds(s, i); |
f64a078d MAL |
987 | } |
988 | g_free(s->peers); | |
989 | } | |
990 | ||
991 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
992 | msix_uninit_exclusive_bar(dev); | |
993 | } | |
994 | ||
0f57350e | 995 | g_free(s->msi_vectors); |
6cbf4c8c CM |
996 | } |
997 | ||
1f8552df MAL |
998 | static int ivshmem_pre_load(void *opaque) |
999 | { | |
1000 | IVShmemState *s = opaque; | |
1001 | ||
2a845da7 | 1002 | if (!ivshmem_is_master(s)) { |
1f8552df MAL |
1003 | error_report("'peer' devices are not migratable"); |
1004 | return -EINVAL; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static int ivshmem_post_load(void *opaque, int version_id) | |
1011 | { | |
1012 | IVShmemState *s = opaque; | |
1013 | ||
1014 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 1015 | ivshmem_msix_vector_use(s); |
1f8552df | 1016 | } |
1f8552df MAL |
1017 | return 0; |
1018 | } | |
1019 | ||
5400c02b | 1020 | static void ivshmem_common_class_init(ObjectClass *klass, void *data) |
40021f08 | 1021 | { |
39bffca2 | 1022 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1023 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1024 | ||
5400c02b MA |
1025 | k->realize = ivshmem_common_realize; |
1026 | k->exit = ivshmem_exit; | |
d58d7e84 | 1027 | k->config_write = ivshmem_write_config; |
b8ef62a9 PB |
1028 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
1029 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 1030 | k->class_id = PCI_CLASS_MEMORY_RAM; |
5400c02b | 1031 | k->revision = 1; |
39bffca2 | 1032 | dc->reset = ivshmem_reset; |
125ee0ed | 1033 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1034 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1035 | } |
1036 | ||
ddc85284 MA |
1037 | static const TypeInfo ivshmem_common_info = { |
1038 | .name = TYPE_IVSHMEM_COMMON, | |
1039 | .parent = TYPE_PCI_DEVICE, | |
1040 | .instance_size = sizeof(IVShmemState), | |
1041 | .abstract = true, | |
1042 | .class_init = ivshmem_common_class_init, | |
fd3b02c8 EH |
1043 | .interfaces = (InterfaceInfo[]) { |
1044 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1045 | { }, | |
1046 | }, | |
ddc85284 | 1047 | }; |
5400c02b | 1048 | |
5400c02b MA |
1049 | static const VMStateDescription ivshmem_plain_vmsd = { |
1050 | .name = TYPE_IVSHMEM_PLAIN, | |
1051 | .version_id = 0, | |
1052 | .minimum_version_id = 0, | |
1053 | .pre_load = ivshmem_pre_load, | |
1054 | .post_load = ivshmem_post_load, | |
1055 | .fields = (VMStateField[]) { | |
1056 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1057 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1058 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1059 | VMSTATE_END_OF_LIST() | |
1060 | }, | |
1061 | }; | |
1062 | ||
1063 | static Property ivshmem_plain_properties[] = { | |
1064 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
e9cb190a FZ |
1065 | DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND, |
1066 | HostMemoryBackend *), | |
5400c02b MA |
1067 | DEFINE_PROP_END_OF_LIST(), |
1068 | }; | |
1069 | ||
6dc64780 MAL |
1070 | static void ivshmem_plain_realize(PCIDevice *dev, Error **errp) |
1071 | { | |
1072 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1073 | ||
1074 | if (!s->hostmem) { | |
1075 | error_setg(errp, "You must specify a 'memdev'"); | |
1076 | return; | |
e9cb190a FZ |
1077 | } else if (host_memory_backend_is_mapped(s->hostmem)) { |
1078 | char *path = object_get_canonical_path_component(OBJECT(s->hostmem)); | |
1079 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1080 | g_free(path); | |
1081 | return; | |
6dc64780 MAL |
1082 | } |
1083 | ||
1084 | ivshmem_common_realize(dev, errp); | |
1085 | } | |
1086 | ||
5400c02b MA |
1087 | static void ivshmem_plain_class_init(ObjectClass *klass, void *data) |
1088 | { | |
1089 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1090 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1091 | |
6dc64780 | 1092 | k->realize = ivshmem_plain_realize; |
5400c02b MA |
1093 | dc->props = ivshmem_plain_properties; |
1094 | dc->vmsd = &ivshmem_plain_vmsd; | |
1095 | } | |
1096 | ||
1097 | static const TypeInfo ivshmem_plain_info = { | |
1098 | .name = TYPE_IVSHMEM_PLAIN, | |
1099 | .parent = TYPE_IVSHMEM_COMMON, | |
1100 | .instance_size = sizeof(IVShmemState), | |
5400c02b MA |
1101 | .class_init = ivshmem_plain_class_init, |
1102 | }; | |
1103 | ||
1104 | static const VMStateDescription ivshmem_doorbell_vmsd = { | |
1105 | .name = TYPE_IVSHMEM_DOORBELL, | |
1106 | .version_id = 0, | |
1107 | .minimum_version_id = 0, | |
1108 | .pre_load = ivshmem_pre_load, | |
1109 | .post_load = ivshmem_post_load, | |
1110 | .fields = (VMStateField[]) { | |
1111 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1112 | VMSTATE_MSIX(parent_obj, IVShmemState), | |
1113 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1114 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1115 | VMSTATE_END_OF_LIST() | |
1116 | }, | |
1117 | }; | |
1118 | ||
1119 | static Property ivshmem_doorbell_properties[] = { | |
1120 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1121 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1122 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1123 | true), | |
1124 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1125 | DEFINE_PROP_END_OF_LIST(), | |
1126 | }; | |
1127 | ||
1128 | static void ivshmem_doorbell_init(Object *obj) | |
1129 | { | |
1130 | IVShmemState *s = IVSHMEM_DOORBELL(obj); | |
1131 | ||
1132 | s->features |= (1 << IVSHMEM_MSI); | |
5400c02b MA |
1133 | } |
1134 | ||
6dc64780 MAL |
1135 | static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp) |
1136 | { | |
1137 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
1138 | ||
30650701 | 1139 | if (!qemu_chr_fe_backend_connected(&s->server_chr)) { |
6dc64780 MAL |
1140 | error_setg(errp, "You must specify a 'chardev'"); |
1141 | return; | |
1142 | } | |
1143 | ||
1144 | ivshmem_common_realize(dev, errp); | |
1145 | } | |
1146 | ||
5400c02b MA |
1147 | static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data) |
1148 | { | |
1149 | DeviceClass *dc = DEVICE_CLASS(klass); | |
6dc64780 | 1150 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
5400c02b | 1151 | |
6dc64780 | 1152 | k->realize = ivshmem_doorbell_realize; |
5400c02b MA |
1153 | dc->props = ivshmem_doorbell_properties; |
1154 | dc->vmsd = &ivshmem_doorbell_vmsd; | |
1155 | } | |
1156 | ||
1157 | static const TypeInfo ivshmem_doorbell_info = { | |
1158 | .name = TYPE_IVSHMEM_DOORBELL, | |
1159 | .parent = TYPE_IVSHMEM_COMMON, | |
1160 | .instance_size = sizeof(IVShmemState), | |
1161 | .instance_init = ivshmem_doorbell_init, | |
1162 | .class_init = ivshmem_doorbell_class_init, | |
1163 | }; | |
1164 | ||
83f7d43a | 1165 | static void ivshmem_register_types(void) |
6cbf4c8c | 1166 | { |
5400c02b MA |
1167 | type_register_static(&ivshmem_common_info); |
1168 | type_register_static(&ivshmem_plain_info); | |
1169 | type_register_static(&ivshmem_doorbell_info); | |
6cbf4c8c CM |
1170 | } |
1171 | ||
83f7d43a | 1172 | type_init(ivshmem_register_types) |