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Commit | Line | Data |
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3475187d FB |
1 | /* |
2 | * QEMU Sparc SLAVIO aux io port emulation | |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
2582cfa0 | 24 | |
0d1c9782 | 25 | #include "qemu/osdep.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
64552b6b | 27 | #include "hw/irq.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
0b8fa32f | 29 | #include "qemu/module.h" |
97bf4851 | 30 | #include "trace.h" |
3475187d FB |
31 | |
32 | /* | |
33 | * This is the auxio port, chip control and system control part of | |
34 | * chip STP2001 (Slave I/O), also produced as NCR89C105. See | |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
36 | * | |
37 | * This also includes the PMC CPU idle controller. | |
38 | */ | |
39 | ||
95eb2084 AF |
40 | #define TYPE_SLAVIO_MISC "slavio_misc" |
41 | #define SLAVIO_MISC(obj) OBJECT_CHECK(MiscState, (obj), TYPE_SLAVIO_MISC) | |
42 | ||
3475187d | 43 | typedef struct MiscState { |
95eb2084 AF |
44 | SysBusDevice parent_obj; |
45 | ||
dd703aae | 46 | MemoryRegion cfg_iomem; |
96891e59 | 47 | MemoryRegion diag_iomem; |
2e66ac3d | 48 | MemoryRegion mdm_iomem; |
aca23c71 | 49 | MemoryRegion led_iomem; |
cd64a524 | 50 | MemoryRegion sysctrl_iomem; |
cccd43c5 | 51 | MemoryRegion aux1_iomem; |
40ce02fc | 52 | MemoryRegion aux2_iomem; |
d537cf6c | 53 | qemu_irq irq; |
97bbb109 | 54 | qemu_irq fdc_tc; |
d37adb09 | 55 | uint32_t dummy; |
3475187d FB |
56 | uint8_t config; |
57 | uint8_t aux1, aux2; | |
bfa30a38 | 58 | uint8_t diag, mctrl; |
d37adb09 | 59 | uint8_t sysctrl; |
6a3b9cc9 | 60 | uint16_t leds; |
3475187d FB |
61 | } MiscState; |
62 | ||
f1a0a79f AF |
63 | #define TYPE_APC "apc" |
64 | #define APC(obj) OBJECT_CHECK(APCState, (obj), TYPE_APC) | |
65 | ||
2582cfa0 | 66 | typedef struct APCState { |
f1a0a79f AF |
67 | SysBusDevice parent_obj; |
68 | ||
9c48dee6 | 69 | MemoryRegion iomem; |
2582cfa0 BS |
70 | qemu_irq cpu_halt; |
71 | } APCState; | |
72 | ||
5aca8c3b | 73 | #define MISC_SIZE 1 |
0e1cd657 | 74 | #define LED_SIZE 2 |
a8f48dcc | 75 | #define SYSCTRL_SIZE 4 |
3475187d | 76 | |
2be17ebd BS |
77 | #define AUX1_TC 0x02 |
78 | ||
7debeb82 BS |
79 | #define AUX2_PWROFF 0x01 |
80 | #define AUX2_PWRINTCLR 0x02 | |
81 | #define AUX2_PWRFAIL 0x20 | |
82 | ||
83 | #define CFG_PWRINTEN 0x08 | |
84 | ||
85 | #define SYS_RESET 0x01 | |
86 | #define SYS_RESETSTAT 0x02 | |
87 | ||
3475187d FB |
88 | static void slavio_misc_update_irq(void *opaque) |
89 | { | |
90 | MiscState *s = opaque; | |
91 | ||
7debeb82 | 92 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) { |
97bf4851 | 93 | trace_slavio_misc_update_irq_raise(); |
d537cf6c | 94 | qemu_irq_raise(s->irq); |
3475187d | 95 | } else { |
97bf4851 | 96 | trace_slavio_misc_update_irq_lower(); |
d537cf6c | 97 | qemu_irq_lower(s->irq); |
3475187d FB |
98 | } |
99 | } | |
100 | ||
1795057a | 101 | static void slavio_misc_reset(DeviceState *d) |
3475187d | 102 | { |
95eb2084 | 103 | MiscState *s = SLAVIO_MISC(d); |
3475187d | 104 | |
4e3b1ea1 | 105 | // Diagnostic and system control registers not cleared in reset |
3475187d FB |
106 | s->config = s->aux1 = s->aux2 = s->mctrl = 0; |
107 | } | |
108 | ||
b2b6f6ec | 109 | static void slavio_set_power_fail(void *opaque, int irq, int power_failing) |
3475187d FB |
110 | { |
111 | MiscState *s = opaque; | |
112 | ||
97bf4851 | 113 | trace_slavio_set_power_fail(power_failing, s->config); |
7debeb82 BS |
114 | if (power_failing && (s->config & CFG_PWRINTEN)) { |
115 | s->aux2 |= AUX2_PWRFAIL; | |
3475187d | 116 | } else { |
7debeb82 | 117 | s->aux2 &= ~AUX2_PWRFAIL; |
3475187d FB |
118 | } |
119 | slavio_misc_update_irq(s); | |
120 | } | |
121 | ||
a8170e5e | 122 | static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr, |
dd703aae | 123 | uint64_t val, unsigned size) |
a8f48dcc BS |
124 | { |
125 | MiscState *s = opaque; | |
126 | ||
97bf4851 | 127 | trace_slavio_cfg_mem_writeb(val & 0xff); |
a8f48dcc BS |
128 | s->config = val & 0xff; |
129 | slavio_misc_update_irq(s); | |
130 | } | |
131 | ||
a8170e5e | 132 | static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr, |
dd703aae | 133 | unsigned size) |
a8f48dcc BS |
134 | { |
135 | MiscState *s = opaque; | |
136 | uint32_t ret = 0; | |
137 | ||
138 | ret = s->config; | |
97bf4851 | 139 | trace_slavio_cfg_mem_readb(ret); |
a8f48dcc BS |
140 | return ret; |
141 | } | |
142 | ||
dd703aae BC |
143 | static const MemoryRegionOps slavio_cfg_mem_ops = { |
144 | .read = slavio_cfg_mem_readb, | |
145 | .write = slavio_cfg_mem_writeb, | |
146 | .endianness = DEVICE_NATIVE_ENDIAN, | |
147 | .valid = { | |
148 | .min_access_size = 1, | |
149 | .max_access_size = 1, | |
150 | }, | |
a8f48dcc BS |
151 | }; |
152 | ||
a8170e5e | 153 | static void slavio_diag_mem_writeb(void *opaque, hwaddr addr, |
96891e59 | 154 | uint64_t val, unsigned size) |
3475187d FB |
155 | { |
156 | MiscState *s = opaque; | |
157 | ||
97bf4851 | 158 | trace_slavio_diag_mem_writeb(val & 0xff); |
a8f48dcc | 159 | s->diag = val & 0xff; |
3475187d FB |
160 | } |
161 | ||
a8170e5e | 162 | static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr, |
96891e59 | 163 | unsigned size) |
3475187d FB |
164 | { |
165 | MiscState *s = opaque; | |
166 | uint32_t ret = 0; | |
167 | ||
a8f48dcc | 168 | ret = s->diag; |
97bf4851 | 169 | trace_slavio_diag_mem_readb(ret); |
a8f48dcc BS |
170 | return ret; |
171 | } | |
172 | ||
96891e59 BC |
173 | static const MemoryRegionOps slavio_diag_mem_ops = { |
174 | .read = slavio_diag_mem_readb, | |
175 | .write = slavio_diag_mem_writeb, | |
176 | .endianness = DEVICE_NATIVE_ENDIAN, | |
177 | .valid = { | |
178 | .min_access_size = 1, | |
179 | .max_access_size = 1, | |
180 | }, | |
a8f48dcc BS |
181 | }; |
182 | ||
a8170e5e | 183 | static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr, |
2e66ac3d | 184 | uint64_t val, unsigned size) |
a8f48dcc BS |
185 | { |
186 | MiscState *s = opaque; | |
187 | ||
97bf4851 | 188 | trace_slavio_mdm_mem_writeb(val & 0xff); |
a8f48dcc BS |
189 | s->mctrl = val & 0xff; |
190 | } | |
191 | ||
a8170e5e | 192 | static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr, |
2e66ac3d | 193 | unsigned size) |
a8f48dcc BS |
194 | { |
195 | MiscState *s = opaque; | |
196 | uint32_t ret = 0; | |
197 | ||
198 | ret = s->mctrl; | |
97bf4851 | 199 | trace_slavio_mdm_mem_readb(ret); |
3475187d FB |
200 | return ret; |
201 | } | |
202 | ||
2e66ac3d BC |
203 | static const MemoryRegionOps slavio_mdm_mem_ops = { |
204 | .read = slavio_mdm_mem_readb, | |
205 | .write = slavio_mdm_mem_writeb, | |
206 | .endianness = DEVICE_NATIVE_ENDIAN, | |
207 | .valid = { | |
208 | .min_access_size = 1, | |
209 | .max_access_size = 1, | |
210 | }, | |
3475187d FB |
211 | }; |
212 | ||
a8170e5e | 213 | static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr, |
cccd43c5 | 214 | uint64_t val, unsigned size) |
0019ad53 BS |
215 | { |
216 | MiscState *s = opaque; | |
217 | ||
97bf4851 | 218 | trace_slavio_aux1_mem_writeb(val & 0xff); |
2be17ebd BS |
219 | if (val & AUX1_TC) { |
220 | // Send a pulse to floppy terminal count line | |
221 | if (s->fdc_tc) { | |
222 | qemu_irq_raise(s->fdc_tc); | |
223 | qemu_irq_lower(s->fdc_tc); | |
224 | } | |
225 | val &= ~AUX1_TC; | |
226 | } | |
0019ad53 BS |
227 | s->aux1 = val & 0xff; |
228 | } | |
229 | ||
a8170e5e | 230 | static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr, |
cccd43c5 | 231 | unsigned size) |
0019ad53 BS |
232 | { |
233 | MiscState *s = opaque; | |
234 | uint32_t ret = 0; | |
235 | ||
236 | ret = s->aux1; | |
97bf4851 | 237 | trace_slavio_aux1_mem_readb(ret); |
0019ad53 BS |
238 | return ret; |
239 | } | |
240 | ||
cccd43c5 BC |
241 | static const MemoryRegionOps slavio_aux1_mem_ops = { |
242 | .read = slavio_aux1_mem_readb, | |
243 | .write = slavio_aux1_mem_writeb, | |
244 | .endianness = DEVICE_NATIVE_ENDIAN, | |
245 | .valid = { | |
246 | .min_access_size = 1, | |
247 | .max_access_size = 1, | |
248 | }, | |
0019ad53 BS |
249 | }; |
250 | ||
a8170e5e | 251 | static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr, |
40ce02fc | 252 | uint64_t val, unsigned size) |
0019ad53 BS |
253 | { |
254 | MiscState *s = opaque; | |
255 | ||
256 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; | |
97bf4851 | 257 | trace_slavio_aux2_mem_writeb(val & 0xff); |
0019ad53 BS |
258 | val |= s->aux2 & AUX2_PWRFAIL; |
259 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int | |
260 | val &= AUX2_PWROFF; | |
261 | s->aux2 = val; | |
262 | if (val & AUX2_PWROFF) | |
cf83f140 | 263 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
0019ad53 BS |
264 | slavio_misc_update_irq(s); |
265 | } | |
266 | ||
a8170e5e | 267 | static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr, |
40ce02fc | 268 | unsigned size) |
0019ad53 BS |
269 | { |
270 | MiscState *s = opaque; | |
271 | uint32_t ret = 0; | |
272 | ||
273 | ret = s->aux2; | |
97bf4851 | 274 | trace_slavio_aux2_mem_readb(ret); |
0019ad53 BS |
275 | return ret; |
276 | } | |
277 | ||
40ce02fc BC |
278 | static const MemoryRegionOps slavio_aux2_mem_ops = { |
279 | .read = slavio_aux2_mem_readb, | |
280 | .write = slavio_aux2_mem_writeb, | |
281 | .endianness = DEVICE_NATIVE_ENDIAN, | |
282 | .valid = { | |
283 | .min_access_size = 1, | |
284 | .max_access_size = 1, | |
285 | }, | |
0019ad53 BS |
286 | }; |
287 | ||
a8170e5e | 288 | static void apc_mem_writeb(void *opaque, hwaddr addr, |
9c48dee6 | 289 | uint64_t val, unsigned size) |
0019ad53 | 290 | { |
2582cfa0 | 291 | APCState *s = opaque; |
0019ad53 | 292 | |
97bf4851 | 293 | trace_apc_mem_writeb(val & 0xff); |
6d0c293d | 294 | qemu_irq_raise(s->cpu_halt); |
0019ad53 BS |
295 | } |
296 | ||
a8170e5e | 297 | static uint64_t apc_mem_readb(void *opaque, hwaddr addr, |
9c48dee6 | 298 | unsigned size) |
0019ad53 BS |
299 | { |
300 | uint32_t ret = 0; | |
301 | ||
97bf4851 | 302 | trace_apc_mem_readb(ret); |
0019ad53 BS |
303 | return ret; |
304 | } | |
305 | ||
9c48dee6 BC |
306 | static const MemoryRegionOps apc_mem_ops = { |
307 | .read = apc_mem_readb, | |
308 | .write = apc_mem_writeb, | |
309 | .endianness = DEVICE_NATIVE_ENDIAN, | |
310 | .valid = { | |
311 | .min_access_size = 1, | |
312 | .max_access_size = 1, | |
313 | } | |
0019ad53 BS |
314 | }; |
315 | ||
a8170e5e | 316 | static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr, |
cd64a524 | 317 | unsigned size) |
bfa30a38 BS |
318 | { |
319 | MiscState *s = opaque; | |
a8f48dcc | 320 | uint32_t ret = 0; |
bfa30a38 | 321 | |
a8f48dcc | 322 | switch (addr) { |
bfa30a38 BS |
323 | case 0: |
324 | ret = s->sysctrl; | |
325 | break; | |
326 | default: | |
327 | break; | |
328 | } | |
97bf4851 | 329 | trace_slavio_sysctrl_mem_readl(ret); |
bfa30a38 BS |
330 | return ret; |
331 | } | |
332 | ||
a8170e5e | 333 | static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr, |
cd64a524 | 334 | uint64_t val, unsigned size) |
bfa30a38 BS |
335 | { |
336 | MiscState *s = opaque; | |
bfa30a38 | 337 | |
97bf4851 | 338 | trace_slavio_sysctrl_mem_writel(val); |
a8f48dcc | 339 | switch (addr) { |
bfa30a38 | 340 | case 0: |
7debeb82 BS |
341 | if (val & SYS_RESET) { |
342 | s->sysctrl = SYS_RESETSTAT; | |
cf83f140 | 343 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
bfa30a38 BS |
344 | } |
345 | break; | |
346 | default: | |
347 | break; | |
348 | } | |
349 | } | |
350 | ||
cd64a524 BC |
351 | static const MemoryRegionOps slavio_sysctrl_mem_ops = { |
352 | .read = slavio_sysctrl_mem_readl, | |
353 | .write = slavio_sysctrl_mem_writel, | |
354 | .endianness = DEVICE_NATIVE_ENDIAN, | |
355 | .valid = { | |
356 | .min_access_size = 4, | |
357 | .max_access_size = 4, | |
358 | }, | |
bfa30a38 BS |
359 | }; |
360 | ||
a8170e5e | 361 | static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr, |
aca23c71 | 362 | unsigned size) |
6a3b9cc9 BS |
363 | { |
364 | MiscState *s = opaque; | |
a8f48dcc | 365 | uint32_t ret = 0; |
6a3b9cc9 | 366 | |
a8f48dcc | 367 | switch (addr) { |
6a3b9cc9 BS |
368 | case 0: |
369 | ret = s->leds; | |
370 | break; | |
371 | default: | |
372 | break; | |
373 | } | |
97bf4851 | 374 | trace_slavio_led_mem_readw(ret); |
6a3b9cc9 BS |
375 | return ret; |
376 | } | |
377 | ||
a8170e5e | 378 | static void slavio_led_mem_writew(void *opaque, hwaddr addr, |
aca23c71 | 379 | uint64_t val, unsigned size) |
6a3b9cc9 BS |
380 | { |
381 | MiscState *s = opaque; | |
6a3b9cc9 | 382 | |
f3a64b8c | 383 | trace_slavio_led_mem_writew(val & 0xffff); |
a8f48dcc | 384 | switch (addr) { |
6a3b9cc9 | 385 | case 0: |
d5296cb5 | 386 | s->leds = val; |
6a3b9cc9 BS |
387 | break; |
388 | default: | |
389 | break; | |
390 | } | |
391 | } | |
392 | ||
aca23c71 BC |
393 | static const MemoryRegionOps slavio_led_mem_ops = { |
394 | .read = slavio_led_mem_readw, | |
395 | .write = slavio_led_mem_writew, | |
396 | .endianness = DEVICE_NATIVE_ENDIAN, | |
397 | .valid = { | |
398 | .min_access_size = 2, | |
399 | .max_access_size = 2, | |
400 | }, | |
6a3b9cc9 BS |
401 | }; |
402 | ||
d37adb09 BS |
403 | static const VMStateDescription vmstate_misc = { |
404 | .name ="slavio_misc", | |
405 | .version_id = 1, | |
406 | .minimum_version_id = 1, | |
35d08458 | 407 | .fields = (VMStateField[]) { |
d37adb09 BS |
408 | VMSTATE_UINT32(dummy, MiscState), |
409 | VMSTATE_UINT8(config, MiscState), | |
410 | VMSTATE_UINT8(aux1, MiscState), | |
411 | VMSTATE_UINT8(aux2, MiscState), | |
412 | VMSTATE_UINT8(diag, MiscState), | |
413 | VMSTATE_UINT8(mctrl, MiscState), | |
414 | VMSTATE_UINT8(sysctrl, MiscState), | |
415 | VMSTATE_END_OF_LIST() | |
416 | } | |
417 | }; | |
3475187d | 418 | |
46eedc0e | 419 | static void apc_init(Object *obj) |
2582cfa0 | 420 | { |
46eedc0e XZ |
421 | APCState *s = APC(obj); |
422 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
3475187d | 423 | |
2582cfa0 BS |
424 | sysbus_init_irq(dev, &s->cpu_halt); |
425 | ||
426 | /* Power management (APC) XXX: not a Slavio device */ | |
46eedc0e | 427 | memory_region_init_io(&s->iomem, obj, &apc_mem_ops, s, |
9c48dee6 | 428 | "apc", MISC_SIZE); |
750ecd44 | 429 | sysbus_init_mmio(dev, &s->iomem); |
2582cfa0 BS |
430 | } |
431 | ||
46eedc0e | 432 | static void slavio_misc_init(Object *obj) |
2582cfa0 | 433 | { |
46eedc0e XZ |
434 | DeviceState *dev = DEVICE(obj); |
435 | MiscState *s = SLAVIO_MISC(obj); | |
436 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
2582cfa0 | 437 | |
95eb2084 AF |
438 | sysbus_init_irq(sbd, &s->irq); |
439 | sysbus_init_irq(sbd, &s->fdc_tc); | |
2582cfa0 BS |
440 | |
441 | /* 8 bit registers */ | |
442 | /* Slavio control */ | |
46eedc0e | 443 | memory_region_init_io(&s->cfg_iomem, obj, &slavio_cfg_mem_ops, s, |
dd703aae | 444 | "configuration", MISC_SIZE); |
95eb2084 | 445 | sysbus_init_mmio(sbd, &s->cfg_iomem); |
2582cfa0 BS |
446 | |
447 | /* Diagnostics */ | |
46eedc0e | 448 | memory_region_init_io(&s->diag_iomem, obj, &slavio_diag_mem_ops, s, |
96891e59 | 449 | "diagnostic", MISC_SIZE); |
95eb2084 | 450 | sysbus_init_mmio(sbd, &s->diag_iomem); |
2582cfa0 BS |
451 | |
452 | /* Modem control */ | |
46eedc0e | 453 | memory_region_init_io(&s->mdm_iomem, obj, &slavio_mdm_mem_ops, s, |
2e66ac3d | 454 | "modem", MISC_SIZE); |
95eb2084 | 455 | sysbus_init_mmio(sbd, &s->mdm_iomem); |
2582cfa0 BS |
456 | |
457 | /* 16 bit registers */ | |
458 | /* ss600mp diag LEDs */ | |
46eedc0e | 459 | memory_region_init_io(&s->led_iomem, obj, &slavio_led_mem_ops, s, |
0e1cd657 | 460 | "leds", LED_SIZE); |
95eb2084 | 461 | sysbus_init_mmio(sbd, &s->led_iomem); |
2582cfa0 BS |
462 | |
463 | /* 32 bit registers */ | |
464 | /* System control */ | |
46eedc0e | 465 | memory_region_init_io(&s->sysctrl_iomem, obj, &slavio_sysctrl_mem_ops, s, |
0e1cd657 | 466 | "system-control", SYSCTRL_SIZE); |
95eb2084 | 467 | sysbus_init_mmio(sbd, &s->sysctrl_iomem); |
2582cfa0 BS |
468 | |
469 | /* AUX 1 (Misc System Functions) */ | |
46eedc0e | 470 | memory_region_init_io(&s->aux1_iomem, obj, &slavio_aux1_mem_ops, s, |
cccd43c5 | 471 | "misc-system-functions", MISC_SIZE); |
95eb2084 | 472 | sysbus_init_mmio(sbd, &s->aux1_iomem); |
2582cfa0 BS |
473 | |
474 | /* AUX 2 (Software Powerdown Control) */ | |
46eedc0e | 475 | memory_region_init_io(&s->aux2_iomem, obj, &slavio_aux2_mem_ops, s, |
40ce02fc | 476 | "software-powerdown-control", MISC_SIZE); |
95eb2084 | 477 | sysbus_init_mmio(sbd, &s->aux2_iomem); |
2582cfa0 | 478 | |
95eb2084 | 479 | qdev_init_gpio_in(dev, slavio_set_power_fail, 1); |
2582cfa0 | 480 | } |
0019ad53 | 481 | |
999e12bb AL |
482 | static void slavio_misc_class_init(ObjectClass *klass, void *data) |
483 | { | |
39bffca2 | 484 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 485 | |
39bffca2 AL |
486 | dc->reset = slavio_misc_reset; |
487 | dc->vmsd = &vmstate_misc; | |
999e12bb AL |
488 | } |
489 | ||
8c43a6f0 | 490 | static const TypeInfo slavio_misc_info = { |
95eb2084 | 491 | .name = TYPE_SLAVIO_MISC, |
39bffca2 AL |
492 | .parent = TYPE_SYS_BUS_DEVICE, |
493 | .instance_size = sizeof(MiscState), | |
46eedc0e | 494 | .instance_init = slavio_misc_init, |
39bffca2 | 495 | .class_init = slavio_misc_class_init, |
2582cfa0 BS |
496 | }; |
497 | ||
8c43a6f0 | 498 | static const TypeInfo apc_info = { |
f1a0a79f | 499 | .name = TYPE_APC, |
39bffca2 AL |
500 | .parent = TYPE_SYS_BUS_DEVICE, |
501 | .instance_size = sizeof(MiscState), | |
46eedc0e | 502 | .instance_init = apc_init, |
2582cfa0 BS |
503 | }; |
504 | ||
83f7d43a | 505 | static void slavio_misc_register_types(void) |
2582cfa0 | 506 | { |
39bffca2 AL |
507 | type_register_static(&slavio_misc_info); |
508 | type_register_static(&apc_info); | |
3475187d | 509 | } |
2582cfa0 | 510 | |
83f7d43a | 511 | type_init(slavio_misc_register_types) |