]> git.ipfire.org Git - thirdparty/qemu.git/blame - hw/net/vmxnet3.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: Transmit zero UDP checksum as 0xFFFF
[thirdparty/qemu.git] / hw / net / vmxnet3.c
CommitLineData
786fd2b0
DF		 1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
e8d40465 18#include "qemu/osdep.h"
0d09e41a
PB		 19#include "hw/hw.h"
20#include "hw/pci/pci.h"
786fd2b0 21#include "net/net.h"
786fd2b0
DF		 22#include "net/tap.h"
23#include "net/checksum.h"
24#include "sysemu/sysemu.h"
25#include "qemu-common.h"
26#include "qemu/bswap.h"
0d09e41a
PB		 27#include "hw/pci/msix.h"
28#include "hw/pci/msi.h"
f2a8f0a6 29#include "migration/register.h"
786fd2b0
DF		 30
31#include "vmxnet3.h"
32#include "vmxnet_debug.h"
33#include "vmware_utils.h"
605d52e6
DF		 34#include "net_tx_pkt.h"
35#include "net_rx_pkt.h"
786fd2b0
DF		 36
37#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
38#define VMXNET3_MSIX_BAR_SIZE 0x2000
40a87c6c 39#define MIN_BUF_SIZE 60
786fd2b0 40
cb8d4c8f 41/* Compatibility flags for migration */
f9262dae
SL		 42#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
43#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
44 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
f713d4d2
SL		 45#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
46#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
47 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
f9262dae 48
f713d4d2 49#define VMXNET3_EXP_EP_OFFSET (0x48)
f9262dae
SL		 50#define VMXNET3_MSI_OFFSET(s) \
51 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
52#define VMXNET3_MSIX_OFFSET(s) \
53 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
3509866a 54#define VMXNET3_DSN_OFFSET (0x100)
f9262dae 55
786fd2b0
DF		 56#define VMXNET3_BAR0_IDX (0)
57#define VMXNET3_BAR1_IDX (1)
58#define VMXNET3_MSIX_BAR_IDX (2)
59
60#define VMXNET3_OFF_MSIX_TABLE (0x000)
9c087a05
SL		 61#define VMXNET3_OFF_MSIX_PBA(s) \
62 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
786fd2b0
DF		 63
64/* Link speed in Mbps should be shifted by 16 */
65#define VMXNET3_LINK_SPEED (1000 << 16)
66
67/* Link status: 1 - up, 0 - down. */
68#define VMXNET3_LINK_STATUS_UP 0x1
69
70/* Least significant bit should be set for revision and version */
c12d82ef 71#define VMXNET3_UPT_REVISION 0x1
786fd2b0
DF		 72#define VMXNET3_DEVICE_REVISION 0x1
73
8c6c0478
DF		 74/* Number of interrupt vectors for non-MSIx modes */
75#define VMXNET3_MAX_NMSIX_INTRS (1)
76
786fd2b0 77/* Macros for rings descriptors access */
c5082773
KA		 78#define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
79 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 80
c5082773
KA		 81#define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
82 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
786fd2b0 83
c5082773
KA		 84#define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
85 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 86
c5082773
KA		 87#define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
88 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
786fd2b0 89
c5082773
KA		 90#define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
91 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 92
c5082773
KA		 93#define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
94 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
786fd2b0 95
c5082773
KA		 96#define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
97 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
786fd2b0 98
c5082773
KA		 99#define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
100 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
786fd2b0 101
c5082773
KA		 102#define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
103 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
786fd2b0 104
c5082773
KA		 105#define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
106 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
786fd2b0
DF		 107
108/* Macros for guest driver shared area access */
c5082773
KA		 109#define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
110 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 111
c5082773
KA		 112#define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
113 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 114
c5082773
KA		 115#define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
116 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
786fd2b0 117
c5082773
KA		 118#define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
119 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 120
c5082773
KA		 121#define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
122 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 123
c5082773
KA		 124#define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
125 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
786fd2b0
DF		 126
127#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
128
b79f17a9
SL		 129typedef struct VMXNET3Class {
130 PCIDeviceClass parent_class;
f713d4d2 131 DeviceRealize parent_dc_realize;
b79f17a9
SL		 132} VMXNET3Class;
133
786fd2b0
DF		 134#define TYPE_VMXNET3 "vmxnet3"
135#define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
136
b79f17a9
SL		 137#define VMXNET3_DEVICE_CLASS(klass) \
138 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
139#define VMXNET3_DEVICE_GET_CLASS(obj) \
140 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
141
786fd2b0
DF		 142/* Cyclic ring abstraction */
143typedef struct {
144 hwaddr pa;
5504bba1
DDAG		 145 uint32_t size;
146 uint32_t cell_size;
147 uint32_t next;
786fd2b0
DF		 148 uint8_t gen;
149} Vmxnet3Ring;
150
c5082773
KA		 151static inline void vmxnet3_ring_init(PCIDevice *d,
152 Vmxnet3Ring *ring,
786fd2b0 153 hwaddr pa,
5504bba1
DDAG		 154 uint32_t size,
155 uint32_t cell_size,
786fd2b0
DF		 156 bool zero_region)
157{
158 ring->pa = pa;
159 ring->size = size;
160 ring->cell_size = cell_size;
161 ring->gen = VMXNET3_INIT_GEN;
162 ring->next = 0;
163
164 if (zero_region) {
c5082773 165 vmw_shmem_set(d, pa, 0, size * cell_size);
786fd2b0
DF		 166 }
167}
168
169#define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
5504bba1 170 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
786fd2b0
DF		 171 (ring_name), (ridx), \
172 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
173
174static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
175{
176 if (++ring->next >= ring->size) {
177 ring->next = 0;
178 ring->gen ^= 1;
179 }
180}
181
182static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
183{
184 if (ring->next-- == 0) {
185 ring->next = ring->size - 1;
186 ring->gen ^= 1;
187 }
188}
189
190static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
191{
192 return ring->pa + ring->next * ring->cell_size;
193}
194
c5082773
KA		 195static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
196 void *buff)
786fd2b0 197{
c5082773 198 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
786fd2b0
DF		 199}
200
c5082773
KA		 201static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
202 void *buff)
786fd2b0 203{
c5082773 204 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
786fd2b0
DF		 205}
206
207static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
208{
209 return ring->next;
210}
211
212static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
213{
214 return ring->gen;
215}
216
217/* Debug trace-related functions */
218static inline void
219vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
220{
221 VMW_PKPRN("TX DESCR: "
222 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
223 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
224 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
225 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
226 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
227 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
228}
229
230static inline void
231vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
232{
233 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
234 "csum_start: %d, csum_offset: %d",
235 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
236 vhdr->csum_start, vhdr->csum_offset);
237}
238
239static inline void
240vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
241{
242 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
243 "dtype: %d, ext1: %d, btype: %d",
244 le64_to_cpu(descr->addr), descr->len, descr->gen,
245 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
246}
247
248/* Device state and helper functions */
249#define VMXNET3_RX_RINGS_PER_QUEUE (2)
250
251typedef struct {
252 Vmxnet3Ring tx_ring;
253 Vmxnet3Ring comp_ring;
254
255 uint8_t intr_idx;
256 hwaddr tx_stats_pa;
257 struct UPT1_TxStats txq_stats;
258} Vmxnet3TxqDescr;
259
260typedef struct {
261 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
262 Vmxnet3Ring comp_ring;
263 uint8_t intr_idx;
264 hwaddr rx_stats_pa;
265 struct UPT1_RxStats rxq_stats;
266} Vmxnet3RxqDescr;
267
268typedef struct {
269 bool is_masked;
270 bool is_pending;
271 bool is_asserted;
272} Vmxnet3IntState;
273
274typedef struct {
275 PCIDevice parent_obj;
276 NICState *nic;
277 NICConf conf;
278 MemoryRegion bar0;
279 MemoryRegion bar1;
280 MemoryRegion msix_bar;
281
282 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
283 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
284
285 /* Whether MSI-X support was installed successfully */
286 bool msix_used;
786fd2b0
DF		 287 hwaddr drv_shmem;
288 hwaddr temp_shared_guest_driver_memory;
289
290 uint8_t txq_num;
291
292 /* This boolean tells whether RX packet being indicated has to */
293 /* be split into head and body chunks from different RX rings */
294 bool rx_packets_compound;
295
296 bool rx_vlan_stripping;
297 bool lro_supported;
298
299 uint8_t rxq_num;
300
301 /* Network MTU */
302 uint32_t mtu;
303
304 /* Maximum number of fragments for indicated TX packets */
305 uint32_t max_tx_frags;
306
307 /* Maximum number of fragments for indicated RX packets */
308 uint16_t max_rx_frags;
309
310 /* Index for events interrupt */
311 uint8_t event_int_idx;
312
313 /* Whether automatic interrupts masking enabled */
314 bool auto_int_masking;
315
316 bool peer_has_vhdr;
317
318 /* TX packets to QEMU interface */
605d52e6 319 struct NetTxPkt *tx_pkt;
786fd2b0
DF		 320 uint32_t offload_mode;
321 uint32_t cso_or_gso_size;
322 uint16_t tci;
323 bool needs_vlan;
324
605d52e6 325 struct NetRxPkt *rx_pkt;
786fd2b0
DF		 326
327 bool tx_sop;
328 bool skip_current_tx_pkt;
329
330 uint32_t device_active;
331 uint32_t last_command;
332
333 uint32_t link_status_and_speed;
334
335 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
336
337 uint32_t temp_mac; /* To store the low part first */
338
339 MACAddr perm_mac;
340 uint32_t vlan_table[VMXNET3_VFT_SIZE];
341 uint32_t rx_mode;
342 MACAddr *mcast_list;
343 uint32_t mcast_list_len;
344 uint32_t mcast_list_buff_size; /* needed for live migration. */
f9262dae 345
cb8d4c8f 346 /* Compatibility flags for migration */
f9262dae 347 uint32_t compat_flags;
786fd2b0
DF		 348} VMXNET3State;
349
350/* Interrupt management */
351
352/*
52ea63de 353 * This function returns sign whether interrupt line is in asserted state
786fd2b0
DF		 354 * This depends on the type of interrupt used. For INTX interrupt line will
355 * be asserted until explicit deassertion, for MSI(X) interrupt line will
356 * be deasserted automatically due to notification semantics of the MSI(X)
357 * interrupts
358 */
359static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
360{
361 PCIDevice *d = PCI_DEVICE(s);
362
363 if (s->msix_used && msix_enabled(d)) {
364 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
365 msix_notify(d, int_idx);
366 return false;
367 }
1070048e 368 if (msi_enabled(d)) {
786fd2b0
DF		 369 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
370 msi_notify(d, int_idx);
371 return false;
372 }
373
374 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
4c89e3e5 375 pci_irq_assert(d);
786fd2b0
DF		 376 return true;
377}
378
379static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
380{
381 PCIDevice *d = PCI_DEVICE(s);
382
383 /*
384 * This function should never be called for MSI(X) interrupts
385 * because deassertion never required for message interrupts
386 */
387 assert(!s->msix_used || !msix_enabled(d));
388 /*
389 * This function should never be called for MSI(X) interrupts
390 * because deassertion never required for message interrupts
391 */
1070048e 392 assert(!msi_enabled(d));
786fd2b0
DF		 393
394 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
4c89e3e5 395 pci_irq_deassert(d);
786fd2b0
DF		 396}
397
398static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
399{
400 if (!s->interrupt_states[lidx].is_pending &&
401 s->interrupt_states[lidx].is_asserted) {
402 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
403 _vmxnet3_deassert_interrupt_line(s, lidx);
404 s->interrupt_states[lidx].is_asserted = false;
405 return;
406 }
407
408 if (s->interrupt_states[lidx].is_pending &&
409 !s->interrupt_states[lidx].is_masked &&
410 !s->interrupt_states[lidx].is_asserted) {
411 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
412 s->interrupt_states[lidx].is_asserted =
413 _vmxnet3_assert_interrupt_line(s, lidx);
414 s->interrupt_states[lidx].is_pending = false;
415 return;
416 }
417}
418
419static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
420{
421 PCIDevice *d = PCI_DEVICE(s);
422 s->interrupt_states[lidx].is_pending = true;
423 vmxnet3_update_interrupt_line_state(s, lidx);
424
425 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
426 goto do_automask;
427 }
428
1070048e 429 if (msi_enabled(d) && s->auto_int_masking) {
786fd2b0
DF		 430 goto do_automask;
431 }
432
433 return;
434
435do_automask:
436 s->interrupt_states[lidx].is_masked = true;
437 vmxnet3_update_interrupt_line_state(s, lidx);
438}
439
440static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
441{
442 return s->interrupt_states[lidx].is_asserted;
443}
444
445static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
446{
447 s->interrupt_states[int_idx].is_pending = false;
448 if (s->auto_int_masking) {
449 s->interrupt_states[int_idx].is_masked = true;
450 }
451 vmxnet3_update_interrupt_line_state(s, int_idx);
452}
453
454static void
455vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
456{
457 s->interrupt_states[lidx].is_masked = is_masked;
458 vmxnet3_update_interrupt_line_state(s, lidx);
459}
460
c5082773 461static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem)
786fd2b0 462{
c5082773 463 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC);
786fd2b0
DF		 464}
465
466#define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
467#define VMXNET3_MAKE_BYTE(byte_num, val) \
468 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
469
470static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
471{
472 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
473 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
474 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
475 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
476 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
477 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
478
ab647872 479 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
786fd2b0
DF		 480
481 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
482}
483
484static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
485{
486 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
487 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
488 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
489 VMXNET3_MAKE_BYTE(3, addr->a[3]);
490}
491
492static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
493{
494 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
495 VMXNET3_MAKE_BYTE(1, addr->a[5]);
496}
497
498static void
499vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
500{
501 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
502}
503
504static inline void
505vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
506{
507 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
508}
509
510static inline void
511vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
512{
513 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
514}
515
516static void
517vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
518{
519 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
520}
521
522static void
523vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
524{
525 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
526}
527
3a87d009 528static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
786fd2b0
DF		 529{
530 struct Vmxnet3_TxCompDesc txcq_descr;
c5082773 531 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 532
533 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
534
fdda170e 535 memset(&txcq_descr, 0, sizeof(txcq_descr));
786fd2b0
DF		 536 txcq_descr.txdIdx = tx_ridx;
537 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
538
c5082773 539 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);
786fd2b0
DF		 540
541 /* Flush changes in TX descriptor before changing the counter value */
542 smp_wmb();
543
544 vmxnet3_inc_tx_completion_counter(s, qidx);
545 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
546}
547
548static bool
549vmxnet3_setup_tx_offloads(VMXNET3State *s)
550{
551 switch (s->offload_mode) {
552 case VMXNET3_OM_NONE:
605d52e6 553 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
786fd2b0
DF		 554 break;
555
556 case VMXNET3_OM_CSUM:
605d52e6 557 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
786fd2b0
DF		 558 VMW_PKPRN("L4 CSO requested\n");
559 break;
560
561 case VMXNET3_OM_TSO:
605d52e6 562 net_tx_pkt_build_vheader(s->tx_pkt, true, true,
786fd2b0 563 s->cso_or_gso_size);
605d52e6 564 net_tx_pkt_update_ip_checksums(s->tx_pkt);
786fd2b0
DF		 565 VMW_PKPRN("GSO offload requested.");
566 break;
567
568 default:
dfc6f865 569 g_assert_not_reached();
786fd2b0
DF		 570 return false;
571 }
572
573 return true;
574}
575
576static void
577vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
578 const struct Vmxnet3_TxDesc *txd)
579{
580 s->offload_mode = txd->om;
581 s->cso_or_gso_size = txd->msscof;
582 s->tci = txd->tci;
583 s->needs_vlan = txd->ti;
584}
585
586typedef enum {
587 VMXNET3_PKT_STATUS_OK,
588 VMXNET3_PKT_STATUS_ERROR,
589 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
590 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
591} Vmxnet3PktStatus;
592
593static void
594vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
595 Vmxnet3PktStatus status)
596{
605d52e6 597 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt);
786fd2b0
DF		 598 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
599
600 switch (status) {
601 case VMXNET3_PKT_STATUS_OK:
605d52e6 602 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) {
786fd2b0
DF		 603 case ETH_PKT_BCAST:
604 stats->bcastPktsTxOK++;
605 stats->bcastBytesTxOK += tot_len;
606 break;
607 case ETH_PKT_MCAST:
608 stats->mcastPktsTxOK++;
609 stats->mcastBytesTxOK += tot_len;
610 break;
611 case ETH_PKT_UCAST:
612 stats->ucastPktsTxOK++;
613 stats->ucastBytesTxOK += tot_len;
614 break;
615 default:
dfc6f865 616 g_assert_not_reached();
786fd2b0
DF		 617 }
618
619 if (s->offload_mode == VMXNET3_OM_TSO) {
620 /*
621 * According to VMWARE headers this statistic is a number
622 * of packets after segmentation but since we don't have
623 * this information in QEMU model, the best we can do is to
624 * provide number of non-segmented packets
625 */
626 stats->TSOPktsTxOK++;
627 stats->TSOBytesTxOK += tot_len;
628 }
629 break;
630
631 case VMXNET3_PKT_STATUS_DISCARD:
632 stats->pktsTxDiscard++;
633 break;
634
635 case VMXNET3_PKT_STATUS_ERROR:
636 stats->pktsTxError++;
637 break;
638
639 default:
dfc6f865 640 g_assert_not_reached();
786fd2b0
DF		 641 }
642}
643
644static void
645vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
646 int qidx,
647 Vmxnet3PktStatus status)
648{
649 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
605d52e6 650 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt);
786fd2b0
DF		 651
652 switch (status) {
653 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
654 stats->pktsRxOutOfBuf++;
655 break;
656
657 case VMXNET3_PKT_STATUS_ERROR:
658 stats->pktsRxError++;
659 break;
660 case VMXNET3_PKT_STATUS_OK:
605d52e6 661 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
786fd2b0
DF		 662 case ETH_PKT_BCAST:
663 stats->bcastPktsRxOK++;
664 stats->bcastBytesRxOK += tot_len;
665 break;
666 case ETH_PKT_MCAST:
667 stats->mcastPktsRxOK++;
668 stats->mcastBytesRxOK += tot_len;
669 break;
670 case ETH_PKT_UCAST:
671 stats->ucastPktsRxOK++;
672 stats->ucastBytesRxOK += tot_len;
673 break;
674 default:
dfc6f865 675 g_assert_not_reached();
786fd2b0
DF		 676 }
677
678 if (tot_len > s->mtu) {
679 stats->LROPktsRxOK++;
680 stats->LROBytesRxOK += tot_len;
681 }
682 break;
683 default:
dfc6f865 684 g_assert_not_reached();
786fd2b0
DF		 685 }
686}
687
688static inline bool
689vmxnet3_pop_next_tx_descr(VMXNET3State *s,
690 int qidx,
691 struct Vmxnet3_TxDesc *txd,
692 uint32_t *descr_idx)
693{
694 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
c5082773 695 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 696
c5082773 697 vmxnet3_ring_read_curr_cell(d, ring, txd);
786fd2b0
DF		 698 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
699 /* Only read after generation field verification */
700 smp_rmb();
701 /* Re-read to be sure we got the latest version */
c5082773 702 vmxnet3_ring_read_curr_cell(d, ring, txd);
786fd2b0
DF		 703 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
704 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
705 vmxnet3_inc_tx_consumption_counter(s, qidx);
706 return true;
707 }
708
709 return false;
710}
711
712static bool
713vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
714{
715 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
716
717 if (!vmxnet3_setup_tx_offloads(s)) {
718 status = VMXNET3_PKT_STATUS_ERROR;
719 goto func_exit;
720 }
721
722 /* debug prints */
605d52e6
DF		 723 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt));
724 net_tx_pkt_dump(s->tx_pkt);
786fd2b0 725
605d52e6 726 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
786fd2b0
DF		 727 status = VMXNET3_PKT_STATUS_DISCARD;
728 goto func_exit;
729 }
730
731func_exit:
732 vmxnet3_on_tx_done_update_stats(s, qidx, status);
733 return (status == VMXNET3_PKT_STATUS_OK);
734}
735
736static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
737{
738 struct Vmxnet3_TxDesc txd;
739 uint32_t txd_idx;
740 uint32_t data_len;
741 hwaddr data_pa;
742
743 for (;;) {
744 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
745 break;
746 }
747
748 vmxnet3_dump_tx_descr(&txd);
749
750 if (!s->skip_current_tx_pkt) {
751 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
752 data_pa = le64_to_cpu(txd.addr);
753
605d52e6 754 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt,
786fd2b0
DF		 755 data_pa,
756 data_len)) {
757 s->skip_current_tx_pkt = true;
758 }
759 }
760
761 if (s->tx_sop) {
762 vmxnet3_tx_retrieve_metadata(s, &txd);
763 s->tx_sop = false;
764 }
765
766 if (txd.eop) {
605d52e6 767 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) {
786fd2b0 768 if (s->needs_vlan) {
605d52e6 769 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
786fd2b0
DF		 770 }
771
772 vmxnet3_send_packet(s, qidx);
773 } else {
774 vmxnet3_on_tx_done_update_stats(s, qidx,
775 VMXNET3_PKT_STATUS_ERROR);
776 }
777
778 vmxnet3_complete_packet(s, qidx, txd_idx);
779 s->tx_sop = true;
780 s->skip_current_tx_pkt = false;
605d52e6 781 net_tx_pkt_reset(s->tx_pkt);
786fd2b0
DF		 782 }
783 }
784}
785
786static inline void
787vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
788 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
789{
c5082773
KA		 790 PCIDevice *d = PCI_DEVICE(s);
791
786fd2b0
DF		 792 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
793 *didx = vmxnet3_ring_curr_cell_idx(ring);
c5082773 794 vmxnet3_ring_read_curr_cell(d, ring, dbuf);
786fd2b0
DF		 795}
796
797static inline uint8_t
798vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
799{
800 return s->rxq_descr[qidx].rx_ring[ridx].gen;
801}
802
803static inline hwaddr
804vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
805{
806 uint8_t ring_gen;
807 struct Vmxnet3_RxCompDesc rxcd;
808
809 hwaddr daddr =
810 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
811
c5082773
KA		 812 pci_dma_read(PCI_DEVICE(s),
813 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
786fd2b0
DF		 814 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
815
816 if (rxcd.gen != ring_gen) {
817 *descr_gen = ring_gen;
818 vmxnet3_inc_rx_completion_counter(s, qidx);
819 return daddr;
820 }
821
822 return 0;
823}
824
825static inline void
826vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
827{
828 vmxnet3_dec_rx_completion_counter(s, qidx);
829}
830
831#define RXQ_IDX (0)
832#define RX_HEAD_BODY_RING (0)
833#define RX_BODY_ONLY_RING (1)
834
835static bool
836vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
837 struct Vmxnet3_RxDesc *descr_buf,
838 uint32_t *descr_idx,
839 uint32_t *ridx)
840{
841 for (;;) {
842 uint32_t ring_gen;
843 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
844 descr_buf, descr_idx);
845
846 /* If no more free descriptors - return */
847 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
848 if (descr_buf->gen != ring_gen) {
849 return false;
850 }
851
852 /* Only read after generation field verification */
853 smp_rmb();
854 /* Re-read to be sure we got the latest version */
855 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
856 descr_buf, descr_idx);
857
858 /* Mark current descriptor as used/skipped */
859 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
860
861 /* If this is what we are looking for - return */
862 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
863 *ridx = RX_HEAD_BODY_RING;
864 return true;
865 }
866 }
867}
868
869static bool
870vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
871 struct Vmxnet3_RxDesc *d,
872 uint32_t *didx,
873 uint32_t *ridx)
874{
875 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
876
877 /* Try to find corresponding descriptor in head/body ring */
878 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
879 /* Only read after generation field verification */
880 smp_rmb();
881 /* Re-read to be sure we got the latest version */
882 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
883 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
884 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
885 *ridx = RX_HEAD_BODY_RING;
886 return true;
887 }
888 }
889
890 /*
891 * If there is no free descriptors on head/body ring or next free
892 * descriptor is a head descriptor switch to body only ring
893 */
894 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
895
896 /* If no more free descriptors - return */
897 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
898 /* Only read after generation field verification */
899 smp_rmb();
900 /* Re-read to be sure we got the latest version */
901 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
902 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
903 *ridx = RX_BODY_ONLY_RING;
904 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
905 return true;
906 }
907
908 return false;
909}
910
911static inline bool
912vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
913 struct Vmxnet3_RxDesc *descr_buf,
914 uint32_t *descr_idx,
915 uint32_t *ridx)
916{
917 if (is_head || !s->rx_packets_compound) {
918 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
919 } else {
920 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
921 }
922}
923
80da311d
DR		 924/* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
925 * the implementation always passes an RxCompDesc with a "Checksum
926 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
927 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
928 *
929 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
930 * and place a fully computed checksum into the tcp/udp header.
931 * Otherwise, the OS driver will receive a checksum-correct indication
932 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
933 * having just the pseudo header csum value.
934 *
935 * While this is not a problem if packet is destined for local delivery,
936 * in the case the host OS performs forwarding, it will forward an
937 * incorrectly checksummed packet.
938 */
605d52e6 939static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt,
80da311d
DR		 940 const void *pkt_data,
941 size_t pkt_len)
942{
943 struct virtio_net_hdr *vhdr;
944 bool isip4, isip6, istcp, isudp;
945 uint8_t *data;
946 int len;
947
605d52e6 948 if (!net_rx_pkt_has_virt_hdr(pkt)) {
80da311d
DR		 949 return;
950 }
951
605d52e6 952 vhdr = net_rx_pkt_get_vhdr(pkt);
80da311d
DR		 953 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
954 return;
955 }
956
605d52e6 957 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
80da311d
DR		 958 if (!(isip4 || isip6) || !(istcp || isudp)) {
959 return;
960 }
961
962 vmxnet3_dump_virt_hdr(vhdr);
963
964 /* Validate packet len: csum_start + scum_offset + length of csum field */
965 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
2e4ca7db 966 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
80da311d 967 "cannot calculate checksum",
b9f7c377 968 pkt_len, vhdr->csum_start, vhdr->csum_offset);
80da311d
DR		 969 return;
970 }
971
972 data = (uint8_t *)pkt_data + vhdr->csum_start;
973 len = pkt_len - vhdr->csum_start;
974 /* Put the checksum obtained into the packet */
0dacea92
ES		 975 stw_be_p(data + vhdr->csum_offset,
976 net_checksum_finish_nozero(net_checksum_add(len, data)));
80da311d
DR		 977
978 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
979 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
980}
981
605d52e6 982static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt,
786fd2b0
DF		 983 struct Vmxnet3_RxCompDesc *rxcd)
984{
985 int csum_ok, is_gso;
986 bool isip4, isip6, istcp, isudp;
987 struct virtio_net_hdr *vhdr;
988 uint8_t offload_type;
989
605d52e6 990 if (net_rx_pkt_is_vlan_stripped(pkt)) {
786fd2b0 991 rxcd->ts = 1;
605d52e6 992 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt);
786fd2b0
DF		 993 }
994
605d52e6 995 if (!net_rx_pkt_has_virt_hdr(pkt)) {
786fd2b0
DF		 996 goto nocsum;
997 }
998
605d52e6 999 vhdr = net_rx_pkt_get_vhdr(pkt);
786fd2b0
DF		 1000 /*
1001 * Checksum is valid when lower level tell so or when lower level
1002 * requires checksum offload telling that packet produced/bridged
1003 * locally and did travel over network after last checksum calculation
1004 * or production
1005 */
1006 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
1007 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
1008
1009 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
1010 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
1011
1012 if (!csum_ok && !is_gso) {
1013 goto nocsum;
1014 }
1015
605d52e6 1016 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
786fd2b0
DF		 1017 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
1018 goto nocsum;
1019 }
1020
1021 rxcd->cnc = 0;
1022 rxcd->v4 = isip4 ? 1 : 0;
1023 rxcd->v6 = isip6 ? 1 : 0;
1024 rxcd->tcp = istcp ? 1 : 0;
1025 rxcd->udp = isudp ? 1 : 0;
1026 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
1027 return;
1028
1029nocsum:
1030 rxcd->cnc = 1;
1031 return;
1032}
1033
1034static void
11171010
DF		 1035vmxnet3_pci_dma_writev(PCIDevice *pci_dev,
1036 const struct iovec *iov,
1037 size_t start_iov_off,
1038 hwaddr target_addr,
1039 size_t bytes_to_copy)
786fd2b0
DF		 1040{
1041 size_t curr_off = 0;
1042 size_t copied = 0;
1043
1044 while (bytes_to_copy) {
1045 if (start_iov_off < (curr_off + iov->iov_len)) {
1046 size_t chunk_len =
1047 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
1048
11171010
DF		 1049 pci_dma_write(pci_dev, target_addr + copied,
1050 iov->iov_base + start_iov_off - curr_off,
1051 chunk_len);
786fd2b0
DF		 1052
1053 copied += chunk_len;
1054 start_iov_off += chunk_len;
1055 curr_off = start_iov_off;
1056 bytes_to_copy -= chunk_len;
1057 } else {
1058 curr_off += iov->iov_len;
1059 }
1060 iov++;
1061 }
1062}
1063
1064static bool
1065vmxnet3_indicate_packet(VMXNET3State *s)
1066{
1067 struct Vmxnet3_RxDesc rxd;
c5082773 1068 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1069 bool is_head = true;
1070 uint32_t rxd_idx;
c707582b 1071 uint32_t rx_ridx = 0;
786fd2b0
DF		 1072
1073 struct Vmxnet3_RxCompDesc rxcd;
1074 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
1075 hwaddr new_rxcd_pa = 0;
1076 hwaddr ready_rxcd_pa = 0;
605d52e6 1077 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt);
786fd2b0 1078 size_t bytes_copied = 0;
605d52e6 1079 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt);
786fd2b0
DF		 1080 uint16_t num_frags = 0;
1081 size_t chunk_size;
1082
605d52e6 1083 net_rx_pkt_dump(s->rx_pkt);
786fd2b0
DF		 1084
1085 while (bytes_left > 0) {
1086
1087 /* cannot add more frags to packet */
1088 if (num_frags == s->max_rx_frags) {
1089 break;
1090 }
1091
1092 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1093 if (!new_rxcd_pa) {
1094 break;
1095 }
1096
1097 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1098 break;
1099 }
1100
1101 chunk_size = MIN(bytes_left, rxd.len);
c5082773 1102 vmxnet3_pci_dma_writev(d, data, bytes_copied,
11171010 1103 le64_to_cpu(rxd.addr), chunk_size);
786fd2b0
DF		 1104 bytes_copied += chunk_size;
1105 bytes_left -= chunk_size;
1106
1107 vmxnet3_dump_rx_descr(&rxd);
1108
f7472ca4 1109 if (ready_rxcd_pa != 0) {
c5082773 1110 pci_dma_write(d, ready_rxcd_pa, &rxcd, sizeof(rxcd));
786fd2b0
DF		 1111 }
1112
1113 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1114 rxcd.rxdIdx = rxd_idx;
1115 rxcd.len = chunk_size;
1116 rxcd.sop = is_head;
1117 rxcd.gen = new_rxcd_gen;
1118 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1119
f7472ca4 1120 if (bytes_left == 0) {
786fd2b0
DF		 1121 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1122 }
1123
1124 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1125 "sop %d csum_correct %lu",
1126 (unsigned long) rx_ridx,
1127 (unsigned long) rxcd.rxdIdx,
1128 (unsigned long) rxcd.len,
1129 (int) rxcd.sop,
1130 (unsigned long) rxcd.tuc);
1131
1132 is_head = false;
1133 ready_rxcd_pa = new_rxcd_pa;
1134 new_rxcd_pa = 0;
3e948fd3 1135 num_frags++;
786fd2b0
DF		 1136 }
1137
f7472ca4 1138 if (ready_rxcd_pa != 0) {
786fd2b0 1139 rxcd.eop = 1;
f7472ca4 1140 rxcd.err = (bytes_left != 0);
11171010 1141
c5082773 1142 pci_dma_write(d, ready_rxcd_pa, &rxcd, sizeof(rxcd));
786fd2b0
DF		 1143
1144 /* Flush RX descriptor changes */
1145 smp_wmb();
1146 }
1147
f7472ca4 1148 if (new_rxcd_pa != 0) {
786fd2b0
DF		 1149 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1150 }
1151
1152 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1153
1154 if (bytes_left == 0) {
1155 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1156 return true;
1157 } else if (num_frags == s->max_rx_frags) {
1158 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1159 return false;
1160 } else {
1161 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1162 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1163 return false;
1164 }
1165}
1166
1167static void
1168vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1169 uint64_t val, unsigned size)
1170{
1171 VMXNET3State *s = opaque;
1172
6c352ca9
LQ		 1173 if (!s->device_active) {
1174 return;
1175 }
1176
786fd2b0
DF		 1177 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1178 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1179 int tx_queue_idx =
1180 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1181 VMXNET3_REG_ALIGN);
1182 assert(tx_queue_idx <= s->txq_num);
1183 vmxnet3_process_tx_queue(s, tx_queue_idx);
1184 return;
1185 }
1186
1187 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1188 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1189 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1190 VMXNET3_REG_ALIGN);
1191
1192 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1193
1194 vmxnet3_on_interrupt_mask_changed(s, l, val);
1195 return;
1196 }
1197
1198 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1199 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1200 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1201 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1202 return;
1203 }
1204
1205 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1206 (uint64_t) addr, val, size);
1207}
1208
1209static uint64_t
1210vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1211{
c6048f84
SL		 1212 VMXNET3State *s = opaque;
1213
786fd2b0
DF		 1214 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1215 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
c6048f84
SL		 1216 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1217 VMXNET3_REG_ALIGN);
1218 return s->interrupt_states[l].is_masked;
786fd2b0
DF		 1219 }
1220
1221 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1222 return 0;
1223}
1224
1225static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1226{
1227 int i;
1228 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1229 s->interrupt_states[i].is_asserted = false;
1230 s->interrupt_states[i].is_pending = false;
1231 s->interrupt_states[i].is_masked = true;
1232 }
1233}
1234
1235static void vmxnet3_reset_mac(VMXNET3State *s)
1236{
1237 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
ab647872 1238 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
786fd2b0
DF		 1239}
1240
1241static void vmxnet3_deactivate_device(VMXNET3State *s)
1242{
aa4a3dce
PP		 1243 if (s->device_active) {
1244 VMW_CBPRN("Deactivating vmxnet3...");
605d52e6
DF		 1245 net_tx_pkt_reset(s->tx_pkt);
1246 net_tx_pkt_uninit(s->tx_pkt);
1247 net_rx_pkt_uninit(s->rx_pkt);
aa4a3dce
PP		 1248 s->device_active = false;
1249 }
786fd2b0
DF		 1250}
1251
1252static void vmxnet3_reset(VMXNET3State *s)
1253{
1254 VMW_CBPRN("Resetting vmxnet3...");
1255
1256 vmxnet3_deactivate_device(s);
1257 vmxnet3_reset_interrupt_states(s);
786fd2b0
DF		 1258 s->drv_shmem = 0;
1259 s->tx_sop = true;
1260 s->skip_current_tx_pkt = false;
1261}
1262
1263static void vmxnet3_update_rx_mode(VMXNET3State *s)
1264{
c5082773
KA		 1265 PCIDevice *d = PCI_DEVICE(s);
1266
1267 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
786fd2b0
DF		 1268 devRead.rxFilterConf.rxMode);
1269 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1270}
1271
1272static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1273{
1274 int i;
c5082773 1275 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1276
1277 /* Copy configuration from shared memory */
c5082773 1278 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem,
786fd2b0
DF		 1279 devRead.rxFilterConf.vfTable,
1280 s->vlan_table,
1281 sizeof(s->vlan_table));
1282
1283 /* Invert byte order when needed */
1284 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1285 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1286 }
1287
1288 /* Dump configuration for debugging purposes */
1289 VMW_CFPRN("Configured VLANs:");
1290 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1291 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1292 VMW_CFPRN("\tVLAN %d is present", i);
1293 }
1294 }
1295}
1296
1297static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1298{
c5082773
KA		 1299 PCIDevice *d = PCI_DEVICE(s);
1300
786fd2b0 1301 uint16_t list_bytes =
c5082773 1302 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem,
786fd2b0
DF		 1303 devRead.rxFilterConf.mfTableLen);
1304
1305 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1306
1307 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
f7472ca4
GA		 1308 if (!s->mcast_list) {
1309 if (s->mcast_list_len == 0) {
786fd2b0
DF		 1310 VMW_CFPRN("Current multicast list is empty");
1311 } else {
1312 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1313 s->mcast_list_len);
1314 }
1315 s->mcast_list_len = 0;
1316 } else {
1317 int i;
1318 hwaddr mcast_list_pa =
c5082773 1319 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem,
786fd2b0
DF		 1320 devRead.rxFilterConf.mfTablePA);
1321
c5082773 1322 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes);
11171010 1323
786fd2b0
DF		 1324 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1325 for (i = 0; i < s->mcast_list_len; i++) {
ab647872 1326 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a));
786fd2b0
DF		 1327 }
1328 }
1329}
1330
1331static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1332{
1333 vmxnet3_update_rx_mode(s);
1334 vmxnet3_update_vlan_filters(s);
1335 vmxnet3_update_mcast_filters(s);
1336}
1337
1338static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1339{
1340 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1341 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1342 return interrupt_mode;
1343}
1344
1345static void vmxnet3_fill_stats(VMXNET3State *s)
1346{
1347 int i;
c5082773 1348 PCIDevice *d = PCI_DEVICE(s);
eedeeeff
SL		 1349
1350 if (!s->device_active)
1351 return;
1352
786fd2b0 1353 for (i = 0; i < s->txq_num; i++) {
c5082773 1354 pci_dma_write(d,
11171010
DF		 1355 s->txq_descr[i].tx_stats_pa,
1356 &s->txq_descr[i].txq_stats,
1357 sizeof(s->txq_descr[i].txq_stats));
786fd2b0
DF		 1358 }
1359
1360 for (i = 0; i < s->rxq_num; i++) {
c5082773 1361 pci_dma_write(d,
11171010
DF		 1362 s->rxq_descr[i].rx_stats_pa,
1363 &s->rxq_descr[i].rxq_stats,
1364 sizeof(s->rxq_descr[i].rxq_stats));
786fd2b0
DF		 1365 }
1366}
1367
1368static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1369{
1370 struct Vmxnet3_GOSInfo gos;
c5082773 1371 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 1372
c5082773 1373 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos,
786fd2b0
DF		 1374 &gos, sizeof(gos));
1375 s->rx_packets_compound =
1376 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1377
1378 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1379}
1380
1381static void
1382vmxnet3_dump_conf_descr(const char *name,
1383 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1384{
1385 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1386 name, pm_descr->confVer, pm_descr->confLen);
1387
1388};
1389
1390static void vmxnet3_update_pm_state(VMXNET3State *s)
1391{
1392 struct Vmxnet3_VariableLenConfDesc pm_descr;
c5082773 1393 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1394
1395 pm_descr.confLen =
c5082773 1396 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen);
786fd2b0 1397 pm_descr.confVer =
c5082773 1398 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer);
786fd2b0 1399 pm_descr.confPA =
c5082773 1400 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA);
786fd2b0
DF		 1401
1402 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1403}
1404
1405static void vmxnet3_update_features(VMXNET3State *s)
1406{
1407 uint32_t guest_features;
1408 int rxcso_supported;
c5082773 1409 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 1410
c5082773 1411 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
786fd2b0
DF		 1412 devRead.misc.uptFeatures);
1413
1414 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1415 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1416 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1417
1418 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1419 s->lro_supported, rxcso_supported,
1420 s->rx_vlan_stripping);
1421 if (s->peer_has_vhdr) {
d6085e3a
SH		 1422 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1423 rxcso_supported,
1424 s->lro_supported,
1425 s->lro_supported,
1426 0,
1427 0);
786fd2b0
DF		 1428 }
1429}
1430
4c89e3e5
MA		 1431static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1432{
1070048e
C		 1433 return s->msix_used || msi_enabled(PCI_DEVICE(s))
1434 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1;
4c89e3e5
MA		 1435}
1436
8c6c0478
DF		 1437static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1438{
1439 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1440 if (idx >= max_ints) {
1441 hw_error("Bad interrupt index: %d\n", idx);
1442 }
1443}
1444
1445static void vmxnet3_validate_interrupts(VMXNET3State *s)
1446{
1447 int i;
1448
1449 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1450 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1451
1452 for (i = 0; i < s->txq_num; i++) {
1453 int idx = s->txq_descr[i].intr_idx;
1454 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1455 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1456 }
1457
1458 for (i = 0; i < s->rxq_num; i++) {
1459 int idx = s->rxq_descr[i].intr_idx;
1460 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1461 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1462 }
1463}
1464
9878d173
DF		 1465static void vmxnet3_validate_queues(VMXNET3State *s)
1466{
1467 /*
1468 * txq_num and rxq_num are total number of queues
1469 * configured by guest. These numbers must not
1470 * exceed corresponding maximal values.
1471 */
1472
1473 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1474 hw_error("Bad TX queues number: %d\n", s->txq_num);
1475 }
1476
1477 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1478 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1479 }
1480}
1481
786fd2b0
DF		 1482static void vmxnet3_activate_device(VMXNET3State *s)
1483{
1484 int i;
1485 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
c5082773 1486 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1487 hwaddr qdescr_table_pa;
1488 uint64_t pa;
1489 uint32_t size;
1490
1491 /* Verify configuration consistency */
c5082773 1492 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) {
786fd2b0
DF		 1493 VMW_ERPRN("Device configuration received from driver is invalid");
1494 return;
1495 }
1496
aa4a3dce
PP		 1497 /* Verify if device is active */
1498 if (s->device_active) {
1499 VMW_CFPRN("Vmxnet3 device is active");
1500 return;
1501 }
1502
786fd2b0
DF		 1503 vmxnet3_adjust_by_guest_type(s);
1504 vmxnet3_update_features(s);
1505 vmxnet3_update_pm_state(s);
1506 vmxnet3_setup_rx_filtering(s);
1507 /* Cache fields from shared memory */
c5082773 1508 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu);
786fd2b0
DF		 1509 VMW_CFPRN("MTU is %u", s->mtu);
1510
1511 s->max_rx_frags =
c5082773 1512 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG);
786fd2b0 1513
3e948fd3
DF		 1514 if (s->max_rx_frags == 0) {
1515 s->max_rx_frags = 1;
1516 }
1517
786fd2b0
DF		 1518 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1519
1520 s->event_int_idx =
c5082773 1521 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx);
4c89e3e5 1522 assert(vmxnet3_verify_intx(s, s->event_int_idx));
786fd2b0
DF		 1523 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1524
1525 s->auto_int_masking =
c5082773 1526 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask);
786fd2b0
DF		 1527 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1528
1529 s->txq_num =
c5082773 1530 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues);
786fd2b0 1531 s->rxq_num =
c5082773 1532 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues);
786fd2b0
DF		 1533
1534 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
9878d173 1535 vmxnet3_validate_queues(s);
786fd2b0
DF		 1536
1537 qdescr_table_pa =
c5082773 1538 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA);
786fd2b0
DF		 1539 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1540
1541 /*
1542 * Worst-case scenario is a packet that holds all TX rings space so
1543 * we calculate total size of all TX rings for max TX fragments number
1544 */
1545 s->max_tx_frags = 0;
1546
1547 /* TX queues */
1548 for (i = 0; i < s->txq_num; i++) {
1549 hwaddr qdescr_pa =
1550 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1551
1552 /* Read interrupt number for this TX queue */
1553 s->txq_descr[i].intr_idx =
c5082773 1554 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx);
4c89e3e5 1555 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
786fd2b0
DF		 1556
1557 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1558
1559 /* Read rings memory locations for TX queues */
c5082773
KA		 1560 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);
1561 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize);
786fd2b0 1562
c5082773 1563 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,
786fd2b0
DF		 1564 sizeof(struct Vmxnet3_TxDesc), false);
1565 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1566
1567 s->max_tx_frags += size;
1568
1569 /* TXC ring */
c5082773
KA		 1570 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);
1571 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize);
1572 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,
786fd2b0
DF		 1573 sizeof(struct Vmxnet3_TxCompDesc), true);
1574 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1575
1576 s->txq_descr[i].tx_stats_pa =
1577 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1578
1579 memset(&s->txq_descr[i].txq_stats, 0,
1580 sizeof(s->txq_descr[i].txq_stats));
1581
1582 /* Fill device-managed parameters for queues */
c5082773 1583 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
786fd2b0
DF		 1584 ctrl.txThreshold,
1585 VMXNET3_DEF_TX_THRESHOLD);
1586 }
1587
1588 /* Preallocate TX packet wrapper */
1589 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
11171010
DF		 1590 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
1591 s->max_tx_frags, s->peer_has_vhdr);
605d52e6 1592 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
786fd2b0
DF		 1593
1594 /* Read rings memory locations for RX queues */
1595 for (i = 0; i < s->rxq_num; i++) {
1596 int j;
1597 hwaddr qd_pa =
1598 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1599 i * sizeof(struct Vmxnet3_RxQueueDesc);
1600
1601 /* Read interrupt number for this RX queue */
1602 s->rxq_descr[i].intr_idx =
c5082773 1603 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx);
4c89e3e5 1604 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
786fd2b0
DF		 1605
1606 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1607
1608 /* Read rings memory locations */
1609 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1610 /* RX rings */
c5082773
KA		 1611 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);
1612 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]);
1613 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,
786fd2b0
DF		 1614 sizeof(struct Vmxnet3_RxDesc), false);
1615 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1616 i, j, pa, size);
1617 }
1618
1619 /* RXC ring */
c5082773
KA		 1620 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);
1621 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize);
1622 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,
786fd2b0
DF		 1623 sizeof(struct Vmxnet3_RxCompDesc), true);
1624 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1625
1626 s->rxq_descr[i].rx_stats_pa =
1627 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1628 memset(&s->rxq_descr[i].rxq_stats, 0,
1629 sizeof(s->rxq_descr[i].rxq_stats));
1630 }
1631
8c6c0478
DF		 1632 vmxnet3_validate_interrupts(s);
1633
786fd2b0
DF		 1634 /* Make sure everything is in place before device activation */
1635 smp_wmb();
1636
1637 vmxnet3_reset_mac(s);
1638
1639 s->device_active = true;
1640}
1641
1642static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1643{
1644 s->last_command = cmd;
1645
1646 switch (cmd) {
1647 case VMXNET3_CMD_GET_PERM_MAC_HI:
1648 VMW_CBPRN("Set: Get upper part of permanent MAC");
1649 break;
1650
1651 case VMXNET3_CMD_GET_PERM_MAC_LO:
1652 VMW_CBPRN("Set: Get lower part of permanent MAC");
1653 break;
1654
1655 case VMXNET3_CMD_GET_STATS:
1656 VMW_CBPRN("Set: Get device statistics");
1657 vmxnet3_fill_stats(s);
1658 break;
1659
1660 case VMXNET3_CMD_ACTIVATE_DEV:
1661 VMW_CBPRN("Set: Activating vmxnet3 device");
1662 vmxnet3_activate_device(s);
1663 break;
1664
1665 case VMXNET3_CMD_UPDATE_RX_MODE:
1666 VMW_CBPRN("Set: Update rx mode");
1667 vmxnet3_update_rx_mode(s);
1668 break;
1669
1670 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1671 VMW_CBPRN("Set: Update VLAN filters");
1672 vmxnet3_update_vlan_filters(s);
1673 break;
1674
1675 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1676 VMW_CBPRN("Set: Update MAC filters");
1677 vmxnet3_update_mcast_filters(s);
1678 break;
1679
1680 case VMXNET3_CMD_UPDATE_FEATURE:
1681 VMW_CBPRN("Set: Update features");
1682 vmxnet3_update_features(s);
1683 break;
1684
1685 case VMXNET3_CMD_UPDATE_PMCFG:
1686 VMW_CBPRN("Set: Update power management config");
1687 vmxnet3_update_pm_state(s);
1688 break;
1689
1690 case VMXNET3_CMD_GET_LINK:
1691 VMW_CBPRN("Set: Get link");
1692 break;
1693
1694 case VMXNET3_CMD_RESET_DEV:
1695 VMW_CBPRN("Set: Reset device");
1696 vmxnet3_reset(s);
1697 break;
1698
1699 case VMXNET3_CMD_QUIESCE_DEV:
aa4a3dce 1700 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
786fd2b0
DF		 1701 vmxnet3_deactivate_device(s);
1702 break;
1703
1704 case VMXNET3_CMD_GET_CONF_INTR:
1705 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1706 break;
1707
d62241eb
SL		 1708 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1709 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1710 "adaptive ring info flags");
1711 break;
1712
c469669e
MY		 1713 case VMXNET3_CMD_GET_DID_LO:
1714 VMW_CBPRN("Set: Get lower part of device ID");
1715 break;
1716
1717 case VMXNET3_CMD_GET_DID_HI:
1718 VMW_CBPRN("Set: Get upper part of device ID");
1719 break;
1720
5ae3e91c
MY		 1721 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1722 VMW_CBPRN("Set: Get device extra info");
1723 break;
1724
786fd2b0
DF		 1725 default:
1726 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1727 break;
1728 }
1729}
1730
1731static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1732{
1733 uint64_t ret;
1734
1735 switch (s->last_command) {
1736 case VMXNET3_CMD_ACTIVATE_DEV:
fde58177 1737 ret = (s->device_active) ? 0 : 1;
786fd2b0
DF		 1738 VMW_CFPRN("Device active: %" PRIx64, ret);
1739 break;
1740
3e948fd3
DF		 1741 case VMXNET3_CMD_RESET_DEV:
1742 case VMXNET3_CMD_QUIESCE_DEV:
1743 case VMXNET3_CMD_GET_QUEUE_STATUS:
5ae3e91c 1744 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
3e948fd3
DF		 1745 ret = 0;
1746 break;
1747
786fd2b0
DF		 1748 case VMXNET3_CMD_GET_LINK:
1749 ret = s->link_status_and_speed;
1750 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1751 break;
1752
1753 case VMXNET3_CMD_GET_PERM_MAC_LO:
1754 ret = vmxnet3_get_mac_low(&s->perm_mac);
1755 break;
1756
1757 case VMXNET3_CMD_GET_PERM_MAC_HI:
1758 ret = vmxnet3_get_mac_high(&s->perm_mac);
1759 break;
1760
1761 case VMXNET3_CMD_GET_CONF_INTR:
1762 ret = vmxnet3_get_interrupt_config(s);
1763 break;
1764
d62241eb
SL		 1765 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1766 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1767 break;
1768
c469669e
MY		 1769 case VMXNET3_CMD_GET_DID_LO:
1770 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1771 break;
1772
1773 case VMXNET3_CMD_GET_DID_HI:
1774 ret = VMXNET3_DEVICE_REVISION;
1775 break;
1776
786fd2b0
DF		 1777 default:
1778 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
8856be15 1779 ret = 0;
786fd2b0
DF		 1780 break;
1781 }
1782
1783 return ret;
1784}
1785
1786static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1787{
1788 uint32_t events;
c5082773 1789 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1790
1791 VMW_CBPRN("Setting events: 0x%x", val);
c5082773
KA		 1792 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val;
1793 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
786fd2b0
DF		 1794}
1795
1796static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1797{
c5082773 1798 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1799 uint32_t events;
1800
1801 VMW_CBPRN("Clearing events: 0x%x", val);
c5082773
KA		 1802 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val;
1803 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
786fd2b0
DF		 1804}
1805
1806static void
1807vmxnet3_io_bar1_write(void *opaque,
1808 hwaddr addr,
1809 uint64_t val,
1810 unsigned size)
1811{
1812 VMXNET3State *s = opaque;
1813
1814 switch (addr) {
1815 /* Vmxnet3 Revision Report Selection */
1816 case VMXNET3_REG_VRRS:
1817 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1818 val, size);
1819 break;
1820
1821 /* UPT Version Report Selection */
1822 case VMXNET3_REG_UVRS:
1823 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1824 val, size);
1825 break;
1826
1827 /* Driver Shared Address Low */
1828 case VMXNET3_REG_DSAL:
1829 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1830 val, size);
1831 /*
1832 * Guest driver will first write the low part of the shared
1833 * memory address. We save it to temp variable and set the
1834 * shared address only after we get the high part
1835 */
f7472ca4 1836 if (val == 0) {
aa4a3dce 1837 vmxnet3_deactivate_device(s);
786fd2b0
DF		 1838 }
1839 s->temp_shared_guest_driver_memory = val;
1840 s->drv_shmem = 0;
1841 break;
1842
1843 /* Driver Shared Address High */
1844 case VMXNET3_REG_DSAH:
1845 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1846 val, size);
1847 /*
1848 * Set the shared memory between guest driver and device.
1849 * We already should have low address part.
1850 */
1851 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1852 break;
1853
1854 /* Command */
1855 case VMXNET3_REG_CMD:
1856 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1857 val, size);
1858 vmxnet3_handle_command(s, val);
1859 break;
1860
1861 /* MAC Address Low */
1862 case VMXNET3_REG_MACL:
1863 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1864 val, size);
1865 s->temp_mac = val;
1866 break;
1867
1868 /* MAC Address High */
1869 case VMXNET3_REG_MACH:
1870 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1871 val, size);
1872 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1873 break;
1874
1875 /* Interrupt Cause Register */
1876 case VMXNET3_REG_ICR:
1877 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1878 val, size);
dfc6f865 1879 g_assert_not_reached();
786fd2b0
DF		 1880 break;
1881
1882 /* Event Cause Register */
1883 case VMXNET3_REG_ECR:
1884 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1885 val, size);
1886 vmxnet3_ack_events(s, val);
1887 break;
1888
1889 default:
1890 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1891 addr, val, size);
1892 break;
1893 }
1894}
1895
1896static uint64_t
1897vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1898{
1899 VMXNET3State *s = opaque;
1900 uint64_t ret = 0;
1901
1902 switch (addr) {
1903 /* Vmxnet3 Revision Report Selection */
1904 case VMXNET3_REG_VRRS:
1905 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1906 ret = VMXNET3_DEVICE_REVISION;
1907 break;
1908
1909 /* UPT Version Report Selection */
1910 case VMXNET3_REG_UVRS:
1911 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
c12d82ef 1912 ret = VMXNET3_UPT_REVISION;
786fd2b0
DF		 1913 break;
1914
1915 /* Command */
1916 case VMXNET3_REG_CMD:
1917 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1918 ret = vmxnet3_get_command_status(s);
1919 break;
1920
1921 /* MAC Address Low */
1922 case VMXNET3_REG_MACL:
1923 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1924 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1925 break;
1926
1927 /* MAC Address High */
1928 case VMXNET3_REG_MACH:
1929 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1930 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1931 break;
1932
1933 /*
1934 * Interrupt Cause Register
1935 * Used for legacy interrupts only so interrupt index always 0
1936 */
1937 case VMXNET3_REG_ICR:
1938 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1939 if (vmxnet3_interrupt_asserted(s, 0)) {
1940 vmxnet3_clear_interrupt(s, 0);
1941 ret = true;
1942 } else {
1943 ret = false;
1944 }
1945 break;
1946
1947 default:
1948 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1949 break;
1950 }
1951
1952 return ret;
1953}
1954
1955static int
1956vmxnet3_can_receive(NetClientState *nc)
1957{
1958 VMXNET3State *s = qemu_get_nic_opaque(nc);
1959 return s->device_active &&
1960 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1961}
1962
1963static inline bool
1964vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1965{
1966 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1967 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1968 return true;
1969 }
1970
1971 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1972}
1973
1974static bool
1975vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1976{
1977 int i;
1978 for (i = 0; i < s->mcast_list_len; i++) {
1979 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1980 return true;
1981 }
1982 }
1983 return false;
1984}
1985
1986static bool
1987vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1988 size_t size)
1989{
1990 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1991
1992 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1993 return true;
1994 }
1995
1996 if (!vmxnet3_is_registered_vlan(s, data)) {
1997 return false;
1998 }
1999
605d52e6 2000 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
786fd2b0
DF		 2001 case ETH_PKT_UCAST:
2002 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
2003 return false;
2004 }
2005 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
2006 return false;
2007 }
2008 break;
2009
2010 case ETH_PKT_BCAST:
2011 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
2012 return false;
2013 }
2014 break;
2015
2016 case ETH_PKT_MCAST:
2017 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
2018 return true;
2019 }
2020 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
2021 return false;
2022 }
2023 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
2024 return false;
2025 }
2026 break;
2027
2028 default:
dfc6f865 2029 g_assert_not_reached();
786fd2b0
DF		 2030 }
2031
2032 return true;
2033}
2034
2035static ssize_t
2036vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
2037{
2038 VMXNET3State *s = qemu_get_nic_opaque(nc);
2039 size_t bytes_indicated;
40a87c6c 2040 uint8_t min_buf[MIN_BUF_SIZE];
786fd2b0
DF		 2041
2042 if (!vmxnet3_can_receive(nc)) {
2043 VMW_PKPRN("Cannot receive now");
2044 return -1;
2045 }
2046
b83b5f2e 2047 if (s->peer_has_vhdr) {
605d52e6 2048 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
b83b5f2e
BK		 2049 buf += sizeof(struct virtio_net_hdr);
2050 size -= sizeof(struct virtio_net_hdr);
2051 }
2052
40a87c6c
BD		 2053 /* Pad to minimum Ethernet frame length */
2054 if (size < sizeof(min_buf)) {
2055 memcpy(min_buf, buf, size);
2056 memset(&min_buf[size], 0, sizeof(min_buf) - size);
2057 buf = min_buf;
2058 size = sizeof(min_buf);
2059 }
2060
605d52e6 2061 net_rx_pkt_set_packet_type(s->rx_pkt,
786fd2b0
DF		 2062 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
2063
2064 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
605d52e6 2065 net_rx_pkt_set_protocols(s->rx_pkt, buf, size);
80da311d 2066 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
605d52e6 2067 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
786fd2b0
DF		 2068 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2069 if (bytes_indicated < size) {
2e4ca7db 2070 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
786fd2b0
DF		 2071 }
2072 } else {
2073 VMW_PKPRN("Packet dropped by RX filter");
2074 bytes_indicated = size;
2075 }
2076
2077 assert(size > 0);
2078 assert(bytes_indicated != 0);
2079 return bytes_indicated;
2080}
2081
786fd2b0
DF		 2082static void vmxnet3_set_link_status(NetClientState *nc)
2083{
2084 VMXNET3State *s = qemu_get_nic_opaque(nc);
2085
2086 if (nc->link_down) {
2087 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2088 } else {
2089 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2090 }
2091
2092 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2093 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2094}
2095
2096static NetClientInfo net_vmxnet3_info = {
f394b2e2 2097 .type = NET_CLIENT_DRIVER_NIC,
786fd2b0 2098 .size = sizeof(NICState),
786fd2b0 2099 .receive = vmxnet3_receive,
786fd2b0
DF		 2100 .link_status_changed = vmxnet3_set_link_status,
2101};
2102
2103static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2104{
cf528b89 2105 NetClientState *nc = qemu_get_queue(s->nic);
786fd2b0 2106
d6085e3a 2107 if (qemu_has_vnet_hdr(nc->peer)) {
786fd2b0
DF		 2108 return true;
2109 }
2110
786fd2b0
DF		 2111 return false;
2112}
2113
2114static void vmxnet3_net_uninit(VMXNET3State *s)
2115{
2116 g_free(s->mcast_list);
aa4a3dce 2117 vmxnet3_deactivate_device(s);
3ffee3cd 2118 qemu_del_nic(s->nic);
786fd2b0
DF		 2119}
2120
2121static void vmxnet3_net_init(VMXNET3State *s)
2122{
2123 DeviceState *d = DEVICE(s);
2124
2125 VMW_CBPRN("vmxnet3_net_init called...");
2126
2127 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2128
2129 /* Windows guest will query the address that was set on init */
2130 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2131
2132 s->mcast_list = NULL;
2133 s->mcast_list_len = 0;
2134
2135 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2136
ab647872 2137 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
786fd2b0
DF		 2138
2139 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2140 object_get_typename(OBJECT(s)),
2141 d->id, s);
2142
2143 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2144 s->tx_sop = true;
2145 s->skip_current_tx_pkt = false;
2146 s->tx_pkt = NULL;
2147 s->rx_pkt = NULL;
2148 s->rx_vlan_stripping = false;
2149 s->lro_supported = false;
2150
2151 if (s->peer_has_vhdr) {
d6085e3a 2152 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
786fd2b0
DF		 2153 sizeof(struct virtio_net_hdr));
2154
d6085e3a 2155 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
786fd2b0
DF		 2156 }
2157
2158 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2159}
2160
2161static void
2162vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2163{
2164 PCIDevice *d = PCI_DEVICE(s);
2165 int i;
2166 for (i = 0; i < num_vectors; i++) {
2167 msix_vector_unuse(d, i);
2168 }
2169}
2170
2171static bool
2172vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2173{
2174 PCIDevice *d = PCI_DEVICE(s);
2175 int i;
2176 for (i = 0; i < num_vectors; i++) {
2177 int res = msix_vector_use(d, i);
2178 if (0 > res) {
2179 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2180 vmxnet3_unuse_msix_vectors(s, i);
2181 return false;
2182 }
2183 }
2184 return true;
2185}
2186
2187static bool
2188vmxnet3_init_msix(VMXNET3State *s)
2189{
2190 PCIDevice *d = PCI_DEVICE(s);
2191 int res = msix_init(d, VMXNET3_MAX_INTRS,
2192 &s->msix_bar,
2193 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2194 &s->msix_bar,
9c087a05 2195 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
ee640c62 2196 VMXNET3_MSIX_OFFSET(s), NULL);
786fd2b0
DF		 2197
2198 if (0 > res) {
2199 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2200 s->msix_used = false;
2201 } else {
2202 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2203 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2204 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2205 s->msix_used = false;
2206 } else {
2207 s->msix_used = true;
2208 }
2209 }
2210 return s->msix_used;
2211}
2212
2213static void
2214vmxnet3_cleanup_msix(VMXNET3State *s)
2215{
2216 PCIDevice *d = PCI_DEVICE(s);
2217
2218 if (s->msix_used) {
b4467284 2219 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
786fd2b0
DF		 2220 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2221 }
2222}
2223
786fd2b0
DF		 2224static void
2225vmxnet3_cleanup_msi(VMXNET3State *s)
2226{
2227 PCIDevice *d = PCI_DEVICE(s);
2228
1070048e 2229 msi_uninit(d);
786fd2b0
DF		 2230}
2231
2232static void
2233vmxnet3_msix_save(QEMUFile *f, void *opaque)
2234{
2235 PCIDevice *d = PCI_DEVICE(opaque);
2236 msix_save(d, f);
2237}
2238
2239static int
2240vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2241{
2242 PCIDevice *d = PCI_DEVICE(opaque);
2243 msix_load(d, f);
2244 return 0;
2245}
2246
2247static const MemoryRegionOps b0_ops = {
2248 .read = vmxnet3_io_bar0_read,
2249 .write = vmxnet3_io_bar0_write,
2250 .endianness = DEVICE_LITTLE_ENDIAN,
2251 .impl = {
2252 .min_access_size = 4,
2253 .max_access_size = 4,
2254 },
2255};
2256
2257static const MemoryRegionOps b1_ops = {
2258 .read = vmxnet3_io_bar1_read,
2259 .write = vmxnet3_io_bar1_write,
2260 .endianness = DEVICE_LITTLE_ENDIAN,
2261 .impl = {
2262 .min_access_size = 4,
2263 .max_access_size = 4,
2264 },
2265};
2266
1b6e7482
LV		 2267static SaveVMHandlers savevm_vmxnet3_msix = {
2268 .save_state = vmxnet3_msix_save,
2269 .load_state = vmxnet3_msix_load,
2270};
2271
a4b387e6 2272static uint64_t vmxnet3_device_serial_num(VMXNET3State *s)
3509866a 2273{
a4b387e6 2274 uint64_t dsn_payload;
3509866a
SL		 2275 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2276
2277 dsnp[0] = 0xfe;
2278 dsnp[1] = s->conf.macaddr.a[3];
2279 dsnp[2] = s->conf.macaddr.a[4];
2280 dsnp[3] = s->conf.macaddr.a[5];
2281 dsnp[4] = s->conf.macaddr.a[0];
2282 dsnp[5] = s->conf.macaddr.a[1];
2283 dsnp[6] = s->conf.macaddr.a[2];
2284 dsnp[7] = 0xff;
a4b387e6 2285 return dsn_payload;
3509866a
SL		 2286}
2287
1108b2f8
C		 2288
2289#define VMXNET3_USE_64BIT (true)
2290#define VMXNET3_PER_VECTOR_MASK (false)
2291
9af21dbe 2292static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
786fd2b0
DF		 2293{
2294 DeviceState *dev = DEVICE(pci_dev);
2295 VMXNET3State *s = VMXNET3(pci_dev);
1108b2f8 2296 int ret;
786fd2b0
DF		 2297
2298 VMW_CBPRN("Starting init...");
2299
eedfac6f 2300 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
786fd2b0
DF		 2301 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2302 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2303 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2304
eedfac6f 2305 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
786fd2b0
DF		 2306 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2307 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2308 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2309
eedfac6f 2310 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
786fd2b0
DF		 2311 VMXNET3_MSIX_BAR_SIZE);
2312 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2313 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2314
2315 vmxnet3_reset_interrupt_states(s);
2316
2317 /* Interrupt pin A */
2318 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2319
1108b2f8
C		 2320 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
2321 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
2322 /* Any error other than -ENOTSUP(board's MSI support is broken)
2323 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2324 assert(!ret || ret == -ENOTSUP);
1108b2f8 2325
786fd2b0
DF		 2326 if (!vmxnet3_init_msix(s)) {
2327 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2328 }
2329
786fd2b0
DF		 2330 vmxnet3_net_init(s);
2331
3509866a
SL		 2332 if (pci_is_express(pci_dev)) {
2333 if (pci_bus_is_express(pci_dev->bus)) {
2334 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2335 }
2336
a4b387e6
DF		 2337 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
2338 vmxnet3_device_serial_num(s));
f713d4d2
SL		 2339 }
2340
1b6e7482 2341 register_savevm_live(dev, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix, s);
786fd2b0
DF		 2342}
2343
e25524ef
GA		 2344static void vmxnet3_instance_init(Object *obj)
2345{
2346 VMXNET3State *s = VMXNET3(obj);
2347 device_add_bootindex_property(obj, &s->conf.bootindex,
2348 "bootindex", "/ethernet-phy@0",
2349 DEVICE(obj), NULL);
2350}
786fd2b0
DF		 2351
2352static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2353{
2354 DeviceState *dev = DEVICE(pci_dev);
2355 VMXNET3State *s = VMXNET3(pci_dev);
2356
2357 VMW_CBPRN("Starting uninit...");
2358
2359 unregister_savevm(dev, "vmxnet3-msix", s);
2360
2361 vmxnet3_net_uninit(s);
2362
2363 vmxnet3_cleanup_msix(s);
2364
2365 vmxnet3_cleanup_msi(s);
786fd2b0
DF		 2366}
2367
2368static void vmxnet3_qdev_reset(DeviceState *dev)
2369{
2370 PCIDevice *d = PCI_DEVICE(dev);
2371 VMXNET3State *s = VMXNET3(d);
2372
2373 VMW_CBPRN("Starting QDEV reset...");
2374 vmxnet3_reset(s);
2375}
2376
2377static bool vmxnet3_mc_list_needed(void *opaque)
2378{
2379 return true;
2380}
2381
2382static int vmxnet3_mcast_list_pre_load(void *opaque)
2383{
2384 VMXNET3State *s = opaque;
2385
2386 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2387
2388 return 0;
2389}
2390
2391
44b1ff31 2392static int vmxnet3_pre_save(void *opaque)
786fd2b0
DF		 2393{
2394 VMXNET3State *s = opaque;
2395
2396 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
44b1ff31
DDAG		 2397
2398 return 0;
786fd2b0
DF		 2399}
2400
2401static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2402 .name = "vmxnet3/mcast_list",
2403 .version_id = 1,
2404 .minimum_version_id = 1,
786fd2b0 2405 .pre_load = vmxnet3_mcast_list_pre_load,
5cd8cada 2406 .needed = vmxnet3_mc_list_needed,
786fd2b0 2407 .fields = (VMStateField[]) {
59046ec2 2408 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL,
786fd2b0
DF		 2409 mcast_list_buff_size),
2410 VMSTATE_END_OF_LIST()
2411 }
2412};
2413
a11f5cb0
DDAG		 2414static const VMStateDescription vmstate_vmxnet3_ring = {
2415 .name = "vmxnet3-ring",
2416 .version_id = 0,
2417 .fields = (VMStateField[]) {
2418 VMSTATE_UINT64(pa, Vmxnet3Ring),
2419 VMSTATE_UINT32(size, Vmxnet3Ring),
2420 VMSTATE_UINT32(cell_size, Vmxnet3Ring),
2421 VMSTATE_UINT32(next, Vmxnet3Ring),
2422 VMSTATE_UINT8(gen, Vmxnet3Ring),
2423 VMSTATE_END_OF_LIST()
2424 }
786fd2b0
DF		 2425};
2426
a11f5cb0
DDAG		 2427static const VMStateDescription vmstate_vmxnet3_tx_stats = {
2428 .name = "vmxnet3-tx-stats",
2429 .version_id = 0,
2430 .fields = (VMStateField[]) {
2431 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats),
2432 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats),
2433 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats),
2434 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats),
2435 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats),
2436 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats),
2437 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats),
2438 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats),
2439 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats),
2440 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats),
2441 VMSTATE_END_OF_LIST()
786fd2b0 2442 }
a11f5cb0 2443};
786fd2b0 2444
a11f5cb0
DDAG		 2445static const VMStateDescription vmstate_vmxnet3_txq_descr = {
2446 .name = "vmxnet3-txq-descr",
2447 .version_id = 0,
2448 .fields = (VMStateField[]) {
2449 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2450 Vmxnet3Ring),
2451 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2452 Vmxnet3Ring),
2453 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr),
2454 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr),
2455 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats,
2456 struct UPT1_TxStats),
2457 VMSTATE_END_OF_LIST()
786fd2b0 2458 }
a11f5cb0 2459};
786fd2b0 2460
a11f5cb0
DDAG		 2461static const VMStateDescription vmstate_vmxnet3_rx_stats = {
2462 .name = "vmxnet3-rx-stats",
2463 .version_id = 0,
2464 .fields = (VMStateField[]) {
2465 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats),
2466 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats),
2467 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats),
2468 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats),
2469 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats),
2470 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats),
2471 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats),
2472 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats),
2473 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats),
2474 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats),
2475 VMSTATE_END_OF_LIST()
2476 }
2477};
2c21ee76 2478
a11f5cb0
DDAG		 2479static const VMStateDescription vmstate_vmxnet3_rxq_descr = {
2480 .name = "vmxnet3-rxq-descr",
2481 .version_id = 0,
2482 .fields = (VMStateField[]) {
2483 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr,
2484 VMXNET3_RX_RINGS_PER_QUEUE, 0,
2485 vmstate_vmxnet3_ring, Vmxnet3Ring),
2486 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring,
2487 Vmxnet3Ring),
2488 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr),
2489 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr),
2490 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats,
2491 struct UPT1_RxStats),
2492 VMSTATE_END_OF_LIST()
2493 }
2494};
786fd2b0
DF		 2495
2496static int vmxnet3_post_load(void *opaque, int version_id)
2497{
2498 VMXNET3State *s = opaque;
2499 PCIDevice *d = PCI_DEVICE(s);
2500
11171010
DF		 2501 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
2502 s->max_tx_frags, s->peer_has_vhdr);
605d52e6 2503 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
786fd2b0
DF		 2504
2505 if (s->msix_used) {
2506 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2507 VMW_WRPRN("Failed to re-use MSI-X vectors");
2508 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2509 s->msix_used = false;
2510 return -1;
2511 }
2512 }
2513
f12d048a 2514 vmxnet3_validate_queues(s);
3c99afc7
DF		 2515 vmxnet3_validate_interrupts(s);
2516
786fd2b0
DF		 2517 return 0;
2518}
2519
a11f5cb0
DDAG		 2520static const VMStateDescription vmstate_vmxnet3_int_state = {
2521 .name = "vmxnet3-int-state",
2522 .version_id = 0,
2523 .fields = (VMStateField[]) {
2524 VMSTATE_BOOL(is_masked, Vmxnet3IntState),
2525 VMSTATE_BOOL(is_pending, Vmxnet3IntState),
2526 VMSTATE_BOOL(is_asserted, Vmxnet3IntState),
2527 VMSTATE_END_OF_LIST()
2528 }
786fd2b0
DF		 2529};
2530
f713d4d2
SL		 2531static bool vmxnet3_vmstate_need_pcie_device(void *opaque)
2532{
2533 VMXNET3State *s = VMXNET3(opaque);
2534
2535 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE);
2536}
2537
2538static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id)
2539{
2540 return !vmxnet3_vmstate_need_pcie_device(opaque);
2541}
2542
2543static const VMStateDescription vmstate_vmxnet3_pcie_device = {
2544 .name = "vmxnet3/pcie",
2545 .version_id = 1,
2546 .minimum_version_id = 1,
2547 .needed = vmxnet3_vmstate_need_pcie_device,
2548 .fields = (VMStateField[]) {
20daa90a 2549 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
f713d4d2
SL		 2550 VMSTATE_END_OF_LIST()
2551 }
2552};
2553
786fd2b0
DF		 2554static const VMStateDescription vmstate_vmxnet3 = {
2555 .name = "vmxnet3",
2556 .version_id = 1,
2557 .minimum_version_id = 1,
786fd2b0
DF		 2558 .pre_save = vmxnet3_pre_save,
2559 .post_load = vmxnet3_post_load,
d49805ae 2560 .fields = (VMStateField[]) {
f713d4d2
SL		 2561 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State,
2562 vmxnet3_vmstate_test_pci_device, 0,
2563 vmstate_pci_device, PCIDevice),
786fd2b0
DF		 2564 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2565 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2566 VMSTATE_BOOL(lro_supported, VMXNET3State),
2567 VMSTATE_UINT32(rx_mode, VMXNET3State),
2568 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2569 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2570 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2571 VMSTATE_UINT32(mtu, VMXNET3State),
2572 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2573 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2574 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2575 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2576 VMSTATE_UINT8(txq_num, VMXNET3State),
2577 VMSTATE_UINT8(rxq_num, VMXNET3State),
2578 VMSTATE_UINT32(device_active, VMXNET3State),
2579 VMSTATE_UINT32(last_command, VMXNET3State),
2580 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2581 VMSTATE_UINT32(temp_mac, VMXNET3State),
2582 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2583 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2584
a11f5cb0
DDAG		 2585 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State,
2586 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr,
786fd2b0 2587 Vmxnet3TxqDescr),
a11f5cb0
DDAG		 2588 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State,
2589 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr,
786fd2b0 2590 Vmxnet3RxqDescr),
a11f5cb0
DDAG		 2591 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State,
2592 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state,
2593 Vmxnet3IntState),
786fd2b0
DF		 2594
2595 VMSTATE_END_OF_LIST()
2596 },
5cd8cada
JQ		 2597 .subsections = (const VMStateDescription*[]) {
2598 &vmxstate_vmxnet3_mcast_list,
f713d4d2 2599 &vmstate_vmxnet3_pcie_device,
5cd8cada 2600 NULL
786fd2b0
DF		 2601 }
2602};
2603
786fd2b0
DF		 2604static Property vmxnet3_properties[] = {
2605 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
b22e0aef
SL		 2606 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
2607 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
7d6d347d
SL		 2608 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
2609 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
786fd2b0
DF		 2610 DEFINE_PROP_END_OF_LIST(),
2611};
2612
f713d4d2
SL		 2613static void vmxnet3_realize(DeviceState *qdev, Error **errp)
2614{
2615 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
2616 PCIDevice *pci_dev = PCI_DEVICE(qdev);
2617 VMXNET3State *s = VMXNET3(qdev);
2618
2619 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
2620 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2621 }
2622
2623 vc->parent_dc_realize(qdev, errp);
2624}
2625
786fd2b0
DF		 2626static void vmxnet3_class_init(ObjectClass *class, void *data)
2627{
2628 DeviceClass *dc = DEVICE_CLASS(class);
2629 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
f713d4d2 2630 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
786fd2b0 2631
9af21dbe 2632 c->realize = vmxnet3_pci_realize;
786fd2b0
DF		 2633 c->exit = vmxnet3_pci_uninit;
2634 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2635 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2636 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
43716de6 2637 c->romfile = "efi-vmxnet3.rom";
786fd2b0
DF		 2638 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2639 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2640 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
f713d4d2
SL		 2641 vc->parent_dc_realize = dc->realize;
2642 dc->realize = vmxnet3_realize;
786fd2b0
DF		 2643 dc->desc = "VMWare Paravirtualized Ethernet v3";
2644 dc->reset = vmxnet3_qdev_reset;
2645 dc->vmsd = &vmstate_vmxnet3;
2646 dc->props = vmxnet3_properties;
125ee0ed 2647 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
786fd2b0
DF		 2648}
2649
2650static const TypeInfo vmxnet3_info = {
2651 .name = TYPE_VMXNET3,
2652 .parent = TYPE_PCI_DEVICE,
b79f17a9 2653 .class_size = sizeof(VMXNET3Class),
786fd2b0
DF		 2654 .instance_size = sizeof(VMXNET3State),
2655 .class_init = vmxnet3_class_init,
e25524ef 2656 .instance_init = vmxnet3_instance_init,
a5fa336f
EH		 2657 .interfaces = (InterfaceInfo[]) {
2658 { INTERFACE_PCIE_DEVICE },
2659 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2660 { }
2661 },
786fd2b0
DF		 2662};
2663
2664static void vmxnet3_register_types(void)
2665{
2666 VMW_CBPRN("vmxnet3_register_types called...");
2667 type_register_static(&vmxnet3_info);
2668}
2669
2670type_init(vmxnet3_register_types)
Mirror of https://git.qemu.org/git/qemu.git