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[thirdparty/qemu.git] / hw / net / vmxnet3.c
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786fd2b0
DF		 1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
e8d40465 18#include "qemu/osdep.h"
0d09e41a
PB		 19#include "hw/hw.h"
20#include "hw/pci/pci.h"
786fd2b0
DF		 21#include "net/tap.h"
22#include "net/checksum.h"
23#include "sysemu/sysemu.h"
786fd2b0 24#include "qemu/bswap.h"
0b8fa32f 25#include "qemu/module.h"
0d09e41a
PB		 26#include "hw/pci/msix.h"
27#include "hw/pci/msi.h"
f2a8f0a6 28#include "migration/register.h"
d6454270 29#include "migration/vmstate.h"
786fd2b0
DF		 30
31#include "vmxnet3.h"
317639aa 32#include "vmxnet3_defs.h"
786fd2b0
DF		 33#include "vmxnet_debug.h"
34#include "vmware_utils.h"
605d52e6
DF		 35#include "net_tx_pkt.h"
36#include "net_rx_pkt.h"
786fd2b0
DF		 37
38#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
39#define VMXNET3_MSIX_BAR_SIZE 0x2000
40a87c6c 40#define MIN_BUF_SIZE 60
786fd2b0 41
cb8d4c8f 42/* Compatibility flags for migration */
f9262dae
SL		 43#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
44#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
45 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
f713d4d2
SL		 46#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
47#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
48 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
f9262dae 49
f713d4d2 50#define VMXNET3_EXP_EP_OFFSET (0x48)
f9262dae
SL		 51#define VMXNET3_MSI_OFFSET(s) \
52 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
53#define VMXNET3_MSIX_OFFSET(s) \
54 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
3509866a 55#define VMXNET3_DSN_OFFSET (0x100)
f9262dae 56
786fd2b0
DF		 57#define VMXNET3_BAR0_IDX (0)
58#define VMXNET3_BAR1_IDX (1)
59#define VMXNET3_MSIX_BAR_IDX (2)
60
61#define VMXNET3_OFF_MSIX_TABLE (0x000)
9c087a05
SL		 62#define VMXNET3_OFF_MSIX_PBA(s) \
63 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
786fd2b0
DF		 64
65/* Link speed in Mbps should be shifted by 16 */
66#define VMXNET3_LINK_SPEED (1000 << 16)
67
68/* Link status: 1 - up, 0 - down. */
69#define VMXNET3_LINK_STATUS_UP 0x1
70
71/* Least significant bit should be set for revision and version */
c12d82ef 72#define VMXNET3_UPT_REVISION 0x1
786fd2b0
DF		 73#define VMXNET3_DEVICE_REVISION 0x1
74
8c6c0478
DF		 75/* Number of interrupt vectors for non-MSIx modes */
76#define VMXNET3_MAX_NMSIX_INTRS (1)
77
786fd2b0 78/* Macros for rings descriptors access */
c5082773
KA		 79#define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
80 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 81
c5082773
KA		 82#define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
83 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
786fd2b0 84
c5082773
KA		 85#define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
86 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 87
c5082773
KA		 88#define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
89 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
786fd2b0 90
c5082773
KA		 91#define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
92 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
786fd2b0 93
c5082773
KA		 94#define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
95 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
786fd2b0 96
c5082773
KA		 97#define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
98 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
786fd2b0 99
c5082773
KA		 100#define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
101 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
786fd2b0 102
c5082773
KA		 103#define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
104 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
786fd2b0 105
c5082773
KA		 106#define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
107 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
786fd2b0
DF		 108
109/* Macros for guest driver shared area access */
c5082773
KA		 110#define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
111 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 112
c5082773
KA		 113#define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
114 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 115
c5082773
KA		 116#define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
117 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
786fd2b0 118
c5082773
KA		 119#define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
120 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 121
c5082773
KA		 122#define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
123 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
786fd2b0 124
c5082773
KA		 125#define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
126 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
786fd2b0
DF		 127
128#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
129
b79f17a9
SL		 130typedef struct VMXNET3Class {
131 PCIDeviceClass parent_class;
f713d4d2 132 DeviceRealize parent_dc_realize;
b79f17a9
SL		 133} VMXNET3Class;
134
b79f17a9
SL		 135#define VMXNET3_DEVICE_CLASS(klass) \
136 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3)
137#define VMXNET3_DEVICE_GET_CLASS(obj) \
138 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3)
139
c5082773 140static inline void vmxnet3_ring_init(PCIDevice *d,
7d37435b 141 Vmxnet3Ring *ring,
786fd2b0 142 hwaddr pa,
5504bba1
DDAG		 143 uint32_t size,
144 uint32_t cell_size,
786fd2b0
DF		 145 bool zero_region)
146{
147 ring->pa = pa;
148 ring->size = size;
149 ring->cell_size = cell_size;
150 ring->gen = VMXNET3_INIT_GEN;
151 ring->next = 0;
152
153 if (zero_region) {
c5082773 154 vmw_shmem_set(d, pa, 0, size * cell_size);
786fd2b0
DF		 155 }
156}
157
158#define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
5504bba1 159 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
786fd2b0
DF		 160 (ring_name), (ridx), \
161 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
162
163static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
164{
165 if (++ring->next >= ring->size) {
166 ring->next = 0;
167 ring->gen ^= 1;
168 }
169}
170
171static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
172{
173 if (ring->next-- == 0) {
174 ring->next = ring->size - 1;
175 ring->gen ^= 1;
176 }
177}
178
179static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
180{
181 return ring->pa + ring->next * ring->cell_size;
182}
183
c5082773 184static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
7d37435b 185 void *buff)
786fd2b0 186{
c5082773 187 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
786fd2b0
DF		 188}
189
c5082773 190static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
7d37435b 191 void *buff)
786fd2b0 192{
c5082773 193 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
786fd2b0
DF		 194}
195
196static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
197{
198 return ring->next;
199}
200
201static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
202{
203 return ring->gen;
204}
205
206/* Debug trace-related functions */
207static inline void
208vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
209{
210 VMW_PKPRN("TX DESCR: "
211 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
212 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
213 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
c527e0af 214 descr->addr, descr->len, descr->gen, descr->rsvd,
786fd2b0
DF		 215 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
216 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
217}
218
219static inline void
220vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
221{
222 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
223 "csum_start: %d, csum_offset: %d",
224 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
225 vhdr->csum_start, vhdr->csum_offset);
226}
227
228static inline void
229vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
230{
231 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
232 "dtype: %d, ext1: %d, btype: %d",
c527e0af 233 descr->addr, descr->len, descr->gen,
786fd2b0
DF		 234 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
235}
236
786fd2b0
DF		 237/* Interrupt management */
238
239/*
52ea63de 240 * This function returns sign whether interrupt line is in asserted state
786fd2b0
DF		 241 * This depends on the type of interrupt used. For INTX interrupt line will
242 * be asserted until explicit deassertion, for MSI(X) interrupt line will
243 * be deasserted automatically due to notification semantics of the MSI(X)
244 * interrupts
245 */
246static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
247{
248 PCIDevice *d = PCI_DEVICE(s);
249
250 if (s->msix_used && msix_enabled(d)) {
251 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
252 msix_notify(d, int_idx);
253 return false;
254 }
1070048e 255 if (msi_enabled(d)) {
786fd2b0
DF		 256 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
257 msi_notify(d, int_idx);
258 return false;
259 }
260
261 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
4c89e3e5 262 pci_irq_assert(d);
786fd2b0
DF		 263 return true;
264}
265
266static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
267{
268 PCIDevice *d = PCI_DEVICE(s);
269
270 /*
271 * This function should never be called for MSI(X) interrupts
272 * because deassertion never required for message interrupts
273 */
274 assert(!s->msix_used || !msix_enabled(d));
275 /*
276 * This function should never be called for MSI(X) interrupts
277 * because deassertion never required for message interrupts
278 */
1070048e 279 assert(!msi_enabled(d));
786fd2b0
DF		 280
281 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
4c89e3e5 282 pci_irq_deassert(d);
786fd2b0
DF		 283}
284
285static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
286{
287 if (!s->interrupt_states[lidx].is_pending &&
288 s->interrupt_states[lidx].is_asserted) {
289 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
290 _vmxnet3_deassert_interrupt_line(s, lidx);
291 s->interrupt_states[lidx].is_asserted = false;
292 return;
293 }
294
295 if (s->interrupt_states[lidx].is_pending &&
296 !s->interrupt_states[lidx].is_masked &&
297 !s->interrupt_states[lidx].is_asserted) {
298 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
299 s->interrupt_states[lidx].is_asserted =
300 _vmxnet3_assert_interrupt_line(s, lidx);
301 s->interrupt_states[lidx].is_pending = false;
302 return;
303 }
304}
305
306static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
307{
308 PCIDevice *d = PCI_DEVICE(s);
309 s->interrupt_states[lidx].is_pending = true;
310 vmxnet3_update_interrupt_line_state(s, lidx);
311
312 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
313 goto do_automask;
314 }
315
1070048e 316 if (msi_enabled(d) && s->auto_int_masking) {
786fd2b0
DF		 317 goto do_automask;
318 }
319
320 return;
321
322do_automask:
323 s->interrupt_states[lidx].is_masked = true;
324 vmxnet3_update_interrupt_line_state(s, lidx);
325}
326
327static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
328{
329 return s->interrupt_states[lidx].is_asserted;
330}
331
332static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
333{
334 s->interrupt_states[int_idx].is_pending = false;
335 if (s->auto_int_masking) {
336 s->interrupt_states[int_idx].is_masked = true;
337 }
338 vmxnet3_update_interrupt_line_state(s, int_idx);
339}
340
341static void
342vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
343{
344 s->interrupt_states[lidx].is_masked = is_masked;
345 vmxnet3_update_interrupt_line_state(s, lidx);
346}
347
c5082773 348static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem)
786fd2b0 349{
c5082773 350 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC);
786fd2b0
DF		 351}
352
353#define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
354#define VMXNET3_MAKE_BYTE(byte_num, val) \
355 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
356
357static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
358{
359 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
360 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
361 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
362 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
363 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
364 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
365
ab647872 366 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
786fd2b0
DF		 367
368 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
369}
370
371static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
372{
373 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
374 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
375 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
376 VMXNET3_MAKE_BYTE(3, addr->a[3]);
377}
378
379static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
380{
381 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
382 VMXNET3_MAKE_BYTE(1, addr->a[5]);
383}
384
385static void
386vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
387{
388 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
389}
390
391static inline void
392vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
393{
394 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
395}
396
397static inline void
398vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
399{
400 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
401}
402
403static void
404vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
405{
406 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
407}
408
409static void
410vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
411{
412 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
413}
414
3a87d009 415static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
786fd2b0
DF		 416{
417 struct Vmxnet3_TxCompDesc txcq_descr;
c5082773 418 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 419
420 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
421
fdda170e 422 memset(&txcq_descr, 0, sizeof(txcq_descr));
786fd2b0
DF		 423 txcq_descr.txdIdx = tx_ridx;
424 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
c527e0af
TH		 425 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1);
426 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2);
c5082773 427 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);
786fd2b0
DF		 428
429 /* Flush changes in TX descriptor before changing the counter value */
430 smp_wmb();
431
432 vmxnet3_inc_tx_completion_counter(s, qidx);
433 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
434}
435
436static bool
437vmxnet3_setup_tx_offloads(VMXNET3State *s)
438{
439 switch (s->offload_mode) {
440 case VMXNET3_OM_NONE:
605d52e6 441 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
786fd2b0
DF		 442 break;
443
444 case VMXNET3_OM_CSUM:
605d52e6 445 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
786fd2b0
DF		 446 VMW_PKPRN("L4 CSO requested\n");
447 break;
448
449 case VMXNET3_OM_TSO:
605d52e6 450 net_tx_pkt_build_vheader(s->tx_pkt, true, true,
786fd2b0 451 s->cso_or_gso_size);
605d52e6 452 net_tx_pkt_update_ip_checksums(s->tx_pkt);
786fd2b0
DF		 453 VMW_PKPRN("GSO offload requested.");
454 break;
455
456 default:
dfc6f865 457 g_assert_not_reached();
786fd2b0
DF		 458 return false;
459 }
460
461 return true;
462}
463
464static void
465vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
466 const struct Vmxnet3_TxDesc *txd)
467{
468 s->offload_mode = txd->om;
469 s->cso_or_gso_size = txd->msscof;
470 s->tci = txd->tci;
471 s->needs_vlan = txd->ti;
472}
473
474typedef enum {
475 VMXNET3_PKT_STATUS_OK,
476 VMXNET3_PKT_STATUS_ERROR,
477 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
478 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
479} Vmxnet3PktStatus;
480
481static void
482vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
483 Vmxnet3PktStatus status)
484{
605d52e6 485 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt);
786fd2b0
DF		 486 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
487
488 switch (status) {
489 case VMXNET3_PKT_STATUS_OK:
605d52e6 490 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) {
786fd2b0
DF		 491 case ETH_PKT_BCAST:
492 stats->bcastPktsTxOK++;
493 stats->bcastBytesTxOK += tot_len;
494 break;
495 case ETH_PKT_MCAST:
496 stats->mcastPktsTxOK++;
497 stats->mcastBytesTxOK += tot_len;
498 break;
499 case ETH_PKT_UCAST:
500 stats->ucastPktsTxOK++;
501 stats->ucastBytesTxOK += tot_len;
502 break;
503 default:
dfc6f865 504 g_assert_not_reached();
786fd2b0
DF		 505 }
506
507 if (s->offload_mode == VMXNET3_OM_TSO) {
508 /*
509 * According to VMWARE headers this statistic is a number
510 * of packets after segmentation but since we don't have
511 * this information in QEMU model, the best we can do is to
512 * provide number of non-segmented packets
513 */
514 stats->TSOPktsTxOK++;
515 stats->TSOBytesTxOK += tot_len;
516 }
517 break;
518
519 case VMXNET3_PKT_STATUS_DISCARD:
520 stats->pktsTxDiscard++;
521 break;
522
523 case VMXNET3_PKT_STATUS_ERROR:
524 stats->pktsTxError++;
525 break;
526
527 default:
dfc6f865 528 g_assert_not_reached();
786fd2b0
DF		 529 }
530}
531
532static void
533vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
534 int qidx,
535 Vmxnet3PktStatus status)
536{
537 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
605d52e6 538 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt);
786fd2b0
DF		 539
540 switch (status) {
541 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
542 stats->pktsRxOutOfBuf++;
543 break;
544
545 case VMXNET3_PKT_STATUS_ERROR:
546 stats->pktsRxError++;
547 break;
548 case VMXNET3_PKT_STATUS_OK:
605d52e6 549 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
786fd2b0
DF		 550 case ETH_PKT_BCAST:
551 stats->bcastPktsRxOK++;
552 stats->bcastBytesRxOK += tot_len;
553 break;
554 case ETH_PKT_MCAST:
555 stats->mcastPktsRxOK++;
556 stats->mcastBytesRxOK += tot_len;
557 break;
558 case ETH_PKT_UCAST:
559 stats->ucastPktsRxOK++;
560 stats->ucastBytesRxOK += tot_len;
561 break;
562 default:
dfc6f865 563 g_assert_not_reached();
786fd2b0
DF		 564 }
565
566 if (tot_len > s->mtu) {
567 stats->LROPktsRxOK++;
568 stats->LROBytesRxOK += tot_len;
569 }
570 break;
571 default:
dfc6f865 572 g_assert_not_reached();
786fd2b0
DF		 573 }
574}
575
c527e0af
TH		 576static inline void
577vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring,
578 struct Vmxnet3_TxDesc *txd)
579{
580 vmxnet3_ring_read_curr_cell(pcidev, ring, txd);
581 txd->addr = le64_to_cpu(txd->addr);
582 txd->val1 = le32_to_cpu(txd->val1);
583 txd->val2 = le32_to_cpu(txd->val2);
584}
585
786fd2b0
DF		 586static inline bool
587vmxnet3_pop_next_tx_descr(VMXNET3State *s,
588 int qidx,
589 struct Vmxnet3_TxDesc *txd,
590 uint32_t *descr_idx)
591{
592 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
c5082773 593 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 594
c527e0af 595 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
786fd2b0
DF		 596 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
597 /* Only read after generation field verification */
598 smp_rmb();
599 /* Re-read to be sure we got the latest version */
c527e0af 600 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
786fd2b0
DF		 601 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
602 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
603 vmxnet3_inc_tx_consumption_counter(s, qidx);
604 return true;
605 }
606
607 return false;
608}
609
610static bool
611vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
612{
613 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
614
615 if (!vmxnet3_setup_tx_offloads(s)) {
616 status = VMXNET3_PKT_STATUS_ERROR;
617 goto func_exit;
618 }
619
620 /* debug prints */
605d52e6
DF		 621 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt));
622 net_tx_pkt_dump(s->tx_pkt);
786fd2b0 623
605d52e6 624 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
786fd2b0
DF		 625 status = VMXNET3_PKT_STATUS_DISCARD;
626 goto func_exit;
627 }
628
629func_exit:
630 vmxnet3_on_tx_done_update_stats(s, qidx, status);
631 return (status == VMXNET3_PKT_STATUS_OK);
632}
633
634static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
635{
636 struct Vmxnet3_TxDesc txd;
637 uint32_t txd_idx;
638 uint32_t data_len;
639 hwaddr data_pa;
640
641 for (;;) {
642 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
643 break;
644 }
645
646 vmxnet3_dump_tx_descr(&txd);
647
648 if (!s->skip_current_tx_pkt) {
649 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
c527e0af 650 data_pa = txd.addr;
786fd2b0 651
605d52e6 652 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt,
786fd2b0
DF		 653 data_pa,
654 data_len)) {
655 s->skip_current_tx_pkt = true;
656 }
657 }
658
659 if (s->tx_sop) {
660 vmxnet3_tx_retrieve_metadata(s, &txd);
661 s->tx_sop = false;
662 }
663
664 if (txd.eop) {
605d52e6 665 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) {
786fd2b0 666 if (s->needs_vlan) {
605d52e6 667 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
786fd2b0
DF		 668 }
669
670 vmxnet3_send_packet(s, qidx);
671 } else {
672 vmxnet3_on_tx_done_update_stats(s, qidx,
673 VMXNET3_PKT_STATUS_ERROR);
674 }
675
676 vmxnet3_complete_packet(s, qidx, txd_idx);
677 s->tx_sop = true;
678 s->skip_current_tx_pkt = false;
605d52e6 679 net_tx_pkt_reset(s->tx_pkt);
786fd2b0
DF		 680 }
681 }
682}
683
684static inline void
685vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
686 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
687{
c5082773
KA		 688 PCIDevice *d = PCI_DEVICE(s);
689
786fd2b0
DF		 690 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
691 *didx = vmxnet3_ring_curr_cell_idx(ring);
c5082773 692 vmxnet3_ring_read_curr_cell(d, ring, dbuf);
c527e0af
TH		 693 dbuf->addr = le64_to_cpu(dbuf->addr);
694 dbuf->val1 = le32_to_cpu(dbuf->val1);
695 dbuf->ext1 = le32_to_cpu(dbuf->ext1);
786fd2b0
DF		 696}
697
698static inline uint8_t
699vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
700{
701 return s->rxq_descr[qidx].rx_ring[ridx].gen;
702}
703
704static inline hwaddr
705vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
706{
707 uint8_t ring_gen;
708 struct Vmxnet3_RxCompDesc rxcd;
709
710 hwaddr daddr =
711 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
712
c5082773
KA		 713 pci_dma_read(PCI_DEVICE(s),
714 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
c527e0af
TH		 715 rxcd.val1 = le32_to_cpu(rxcd.val1);
716 rxcd.val2 = le32_to_cpu(rxcd.val2);
717 rxcd.val3 = le32_to_cpu(rxcd.val3);
786fd2b0
DF		 718 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
719
720 if (rxcd.gen != ring_gen) {
721 *descr_gen = ring_gen;
722 vmxnet3_inc_rx_completion_counter(s, qidx);
723 return daddr;
724 }
725
726 return 0;
727}
728
729static inline void
730vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
731{
732 vmxnet3_dec_rx_completion_counter(s, qidx);
733}
734
735#define RXQ_IDX (0)
736#define RX_HEAD_BODY_RING (0)
737#define RX_BODY_ONLY_RING (1)
738
739static bool
740vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
741 struct Vmxnet3_RxDesc *descr_buf,
742 uint32_t *descr_idx,
743 uint32_t *ridx)
744{
745 for (;;) {
746 uint32_t ring_gen;
747 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
748 descr_buf, descr_idx);
749
750 /* If no more free descriptors - return */
751 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
752 if (descr_buf->gen != ring_gen) {
753 return false;
754 }
755
756 /* Only read after generation field verification */
757 smp_rmb();
758 /* Re-read to be sure we got the latest version */
759 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
760 descr_buf, descr_idx);
761
762 /* Mark current descriptor as used/skipped */
763 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
764
765 /* If this is what we are looking for - return */
766 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
767 *ridx = RX_HEAD_BODY_RING;
768 return true;
769 }
770 }
771}
772
773static bool
774vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
775 struct Vmxnet3_RxDesc *d,
776 uint32_t *didx,
777 uint32_t *ridx)
778{
779 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
780
781 /* Try to find corresponding descriptor in head/body ring */
782 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
783 /* Only read after generation field verification */
784 smp_rmb();
785 /* Re-read to be sure we got the latest version */
786 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
787 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
788 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
789 *ridx = RX_HEAD_BODY_RING;
790 return true;
791 }
792 }
793
794 /*
795 * If there is no free descriptors on head/body ring or next free
796 * descriptor is a head descriptor switch to body only ring
797 */
798 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
799
800 /* If no more free descriptors - return */
801 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
802 /* Only read after generation field verification */
803 smp_rmb();
804 /* Re-read to be sure we got the latest version */
805 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
806 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
807 *ridx = RX_BODY_ONLY_RING;
808 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
809 return true;
810 }
811
812 return false;
813}
814
815static inline bool
816vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
817 struct Vmxnet3_RxDesc *descr_buf,
818 uint32_t *descr_idx,
819 uint32_t *ridx)
820{
821 if (is_head || !s->rx_packets_compound) {
822 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
823 } else {
824 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
825 }
826}
827
80da311d
DR		 828/* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
829 * the implementation always passes an RxCompDesc with a "Checksum
830 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
831 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
832 *
833 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
834 * and place a fully computed checksum into the tcp/udp header.
835 * Otherwise, the OS driver will receive a checksum-correct indication
836 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
837 * having just the pseudo header csum value.
838 *
839 * While this is not a problem if packet is destined for local delivery,
840 * in the case the host OS performs forwarding, it will forward an
841 * incorrectly checksummed packet.
842 */
605d52e6 843static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt,
80da311d
DR		 844 const void *pkt_data,
845 size_t pkt_len)
846{
847 struct virtio_net_hdr *vhdr;
848 bool isip4, isip6, istcp, isudp;
849 uint8_t *data;
850 int len;
851
605d52e6 852 if (!net_rx_pkt_has_virt_hdr(pkt)) {
80da311d
DR		 853 return;
854 }
855
605d52e6 856 vhdr = net_rx_pkt_get_vhdr(pkt);
80da311d
DR		 857 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
858 return;
859 }
860
605d52e6 861 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
80da311d
DR		 862 if (!(isip4 || isip6) || !(istcp || isudp)) {
863 return;
864 }
865
866 vmxnet3_dump_virt_hdr(vhdr);
867
868 /* Validate packet len: csum_start + scum_offset + length of csum field */
869 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
2e4ca7db 870 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
80da311d 871 "cannot calculate checksum",
b9f7c377 872 pkt_len, vhdr->csum_start, vhdr->csum_offset);
80da311d
DR		 873 return;
874 }
875
876 data = (uint8_t *)pkt_data + vhdr->csum_start;
877 len = pkt_len - vhdr->csum_start;
878 /* Put the checksum obtained into the packet */
0dacea92
ES		 879 stw_be_p(data + vhdr->csum_offset,
880 net_checksum_finish_nozero(net_checksum_add(len, data)));
80da311d
DR		 881
882 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
883 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
884}
885
605d52e6 886static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt,
786fd2b0
DF		 887 struct Vmxnet3_RxCompDesc *rxcd)
888{
889 int csum_ok, is_gso;
890 bool isip4, isip6, istcp, isudp;
891 struct virtio_net_hdr *vhdr;
892 uint8_t offload_type;
893
605d52e6 894 if (net_rx_pkt_is_vlan_stripped(pkt)) {
786fd2b0 895 rxcd->ts = 1;
605d52e6 896 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt);
786fd2b0
DF		 897 }
898
605d52e6 899 if (!net_rx_pkt_has_virt_hdr(pkt)) {
786fd2b0
DF		 900 goto nocsum;
901 }
902
605d52e6 903 vhdr = net_rx_pkt_get_vhdr(pkt);
786fd2b0
DF		 904 /*
905 * Checksum is valid when lower level tell so or when lower level
906 * requires checksum offload telling that packet produced/bridged
907 * locally and did travel over network after last checksum calculation
908 * or production
909 */
910 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
911 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
912
913 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
914 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
915
916 if (!csum_ok && !is_gso) {
917 goto nocsum;
918 }
919
605d52e6 920 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
786fd2b0
DF		 921 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
922 goto nocsum;
923 }
924
925 rxcd->cnc = 0;
926 rxcd->v4 = isip4 ? 1 : 0;
927 rxcd->v6 = isip6 ? 1 : 0;
928 rxcd->tcp = istcp ? 1 : 0;
929 rxcd->udp = isudp ? 1 : 0;
930 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
931 return;
932
933nocsum:
934 rxcd->cnc = 1;
935 return;
936}
937
938static void
11171010
DF		 939vmxnet3_pci_dma_writev(PCIDevice *pci_dev,
940 const struct iovec *iov,
941 size_t start_iov_off,
942 hwaddr target_addr,
943 size_t bytes_to_copy)
786fd2b0
DF		 944{
945 size_t curr_off = 0;
946 size_t copied = 0;
947
948 while (bytes_to_copy) {
949 if (start_iov_off < (curr_off + iov->iov_len)) {
950 size_t chunk_len =
951 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
952
11171010
DF		 953 pci_dma_write(pci_dev, target_addr + copied,
954 iov->iov_base + start_iov_off - curr_off,
955 chunk_len);
786fd2b0
DF		 956
957 copied += chunk_len;
958 start_iov_off += chunk_len;
959 curr_off = start_iov_off;
960 bytes_to_copy -= chunk_len;
961 } else {
962 curr_off += iov->iov_len;
963 }
964 iov++;
965 }
966}
967
c527e0af
TH		 968static void
969vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa,
970 struct Vmxnet3_RxCompDesc *rxcd)
971{
972 rxcd->val1 = cpu_to_le32(rxcd->val1);
973 rxcd->val2 = cpu_to_le32(rxcd->val2);
974 rxcd->val3 = cpu_to_le32(rxcd->val3);
975 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd));
976}
977
786fd2b0
DF		 978static bool
979vmxnet3_indicate_packet(VMXNET3State *s)
980{
981 struct Vmxnet3_RxDesc rxd;
c5082773 982 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 983 bool is_head = true;
984 uint32_t rxd_idx;
c707582b 985 uint32_t rx_ridx = 0;
786fd2b0
DF		 986
987 struct Vmxnet3_RxCompDesc rxcd;
988 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
989 hwaddr new_rxcd_pa = 0;
990 hwaddr ready_rxcd_pa = 0;
605d52e6 991 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt);
786fd2b0 992 size_t bytes_copied = 0;
605d52e6 993 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt);
786fd2b0
DF		 994 uint16_t num_frags = 0;
995 size_t chunk_size;
996
605d52e6 997 net_rx_pkt_dump(s->rx_pkt);
786fd2b0
DF		 998
999 while (bytes_left > 0) {
1000
1001 /* cannot add more frags to packet */
1002 if (num_frags == s->max_rx_frags) {
1003 break;
1004 }
1005
1006 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1007 if (!new_rxcd_pa) {
1008 break;
1009 }
1010
1011 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1012 break;
1013 }
1014
1015 chunk_size = MIN(bytes_left, rxd.len);
c527e0af 1016 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size);
786fd2b0
DF		 1017 bytes_copied += chunk_size;
1018 bytes_left -= chunk_size;
1019
1020 vmxnet3_dump_rx_descr(&rxd);
1021
f7472ca4 1022 if (ready_rxcd_pa != 0) {
c527e0af 1023 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
786fd2b0
DF		 1024 }
1025
1026 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1027 rxcd.rxdIdx = rxd_idx;
1028 rxcd.len = chunk_size;
1029 rxcd.sop = is_head;
1030 rxcd.gen = new_rxcd_gen;
1031 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1032
f7472ca4 1033 if (bytes_left == 0) {
786fd2b0
DF		 1034 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1035 }
1036
1037 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1038 "sop %d csum_correct %lu",
1039 (unsigned long) rx_ridx,
1040 (unsigned long) rxcd.rxdIdx,
1041 (unsigned long) rxcd.len,
1042 (int) rxcd.sop,
1043 (unsigned long) rxcd.tuc);
1044
1045 is_head = false;
1046 ready_rxcd_pa = new_rxcd_pa;
1047 new_rxcd_pa = 0;
3e948fd3 1048 num_frags++;
786fd2b0
DF		 1049 }
1050
f7472ca4 1051 if (ready_rxcd_pa != 0) {
786fd2b0 1052 rxcd.eop = 1;
f7472ca4 1053 rxcd.err = (bytes_left != 0);
11171010 1054
c527e0af 1055 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
786fd2b0
DF		 1056
1057 /* Flush RX descriptor changes */
1058 smp_wmb();
1059 }
1060
f7472ca4 1061 if (new_rxcd_pa != 0) {
786fd2b0
DF		 1062 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1063 }
1064
1065 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1066
1067 if (bytes_left == 0) {
1068 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1069 return true;
1070 } else if (num_frags == s->max_rx_frags) {
1071 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1072 return false;
1073 } else {
1074 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1075 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1076 return false;
1077 }
1078}
1079
1080static void
1081vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1082 uint64_t val, unsigned size)
1083{
1084 VMXNET3State *s = opaque;
1085
6c352ca9
LQ		 1086 if (!s->device_active) {
1087 return;
1088 }
1089
786fd2b0
DF		 1090 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1091 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1092 int tx_queue_idx =
1093 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1094 VMXNET3_REG_ALIGN);
1095 assert(tx_queue_idx <= s->txq_num);
1096 vmxnet3_process_tx_queue(s, tx_queue_idx);
1097 return;
1098 }
1099
1100 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1101 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1102 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1103 VMXNET3_REG_ALIGN);
1104
1105 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1106
1107 vmxnet3_on_interrupt_mask_changed(s, l, val);
1108 return;
1109 }
1110
1111 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1112 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1113 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1114 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1115 return;
1116 }
1117
1118 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1119 (uint64_t) addr, val, size);
1120}
1121
1122static uint64_t
1123vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1124{
c6048f84
SL		 1125 VMXNET3State *s = opaque;
1126
786fd2b0
DF		 1127 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1128 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
c6048f84
SL		 1129 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1130 VMXNET3_REG_ALIGN);
1131 return s->interrupt_states[l].is_masked;
786fd2b0
DF		 1132 }
1133
1134 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1135 return 0;
1136}
1137
1138static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1139{
1140 int i;
1141 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1142 s->interrupt_states[i].is_asserted = false;
1143 s->interrupt_states[i].is_pending = false;
1144 s->interrupt_states[i].is_masked = true;
1145 }
1146}
1147
1148static void vmxnet3_reset_mac(VMXNET3State *s)
1149{
1150 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
ab647872 1151 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
786fd2b0
DF		 1152}
1153
1154static void vmxnet3_deactivate_device(VMXNET3State *s)
1155{
aa4a3dce
PP		 1156 if (s->device_active) {
1157 VMW_CBPRN("Deactivating vmxnet3...");
605d52e6
DF		 1158 net_tx_pkt_reset(s->tx_pkt);
1159 net_tx_pkt_uninit(s->tx_pkt);
1160 net_rx_pkt_uninit(s->rx_pkt);
aa4a3dce
PP		 1161 s->device_active = false;
1162 }
786fd2b0
DF		 1163}
1164
1165static void vmxnet3_reset(VMXNET3State *s)
1166{
1167 VMW_CBPRN("Resetting vmxnet3...");
1168
1169 vmxnet3_deactivate_device(s);
1170 vmxnet3_reset_interrupt_states(s);
786fd2b0
DF		 1171 s->drv_shmem = 0;
1172 s->tx_sop = true;
1173 s->skip_current_tx_pkt = false;
1174}
1175
1176static void vmxnet3_update_rx_mode(VMXNET3State *s)
1177{
c5082773
KA		 1178 PCIDevice *d = PCI_DEVICE(s);
1179
1180 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
786fd2b0
DF		 1181 devRead.rxFilterConf.rxMode);
1182 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1183}
1184
1185static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1186{
1187 int i;
c5082773 1188 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1189
1190 /* Copy configuration from shared memory */
c5082773 1191 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem,
786fd2b0
DF		 1192 devRead.rxFilterConf.vfTable,
1193 s->vlan_table,
1194 sizeof(s->vlan_table));
1195
1196 /* Invert byte order when needed */
1197 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1198 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1199 }
1200
1201 /* Dump configuration for debugging purposes */
1202 VMW_CFPRN("Configured VLANs:");
1203 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1204 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1205 VMW_CFPRN("\tVLAN %d is present", i);
1206 }
1207 }
1208}
1209
1210static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1211{
c5082773
KA		 1212 PCIDevice *d = PCI_DEVICE(s);
1213
786fd2b0 1214 uint16_t list_bytes =
c5082773 1215 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem,
786fd2b0
DF		 1216 devRead.rxFilterConf.mfTableLen);
1217
1218 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1219
1220 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
f7472ca4
GA		 1221 if (!s->mcast_list) {
1222 if (s->mcast_list_len == 0) {
786fd2b0
DF		 1223 VMW_CFPRN("Current multicast list is empty");
1224 } else {
1225 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1226 s->mcast_list_len);
1227 }
1228 s->mcast_list_len = 0;
1229 } else {
1230 int i;
1231 hwaddr mcast_list_pa =
c5082773 1232 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem,
786fd2b0
DF		 1233 devRead.rxFilterConf.mfTablePA);
1234
c5082773 1235 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes);
11171010 1236
786fd2b0
DF		 1237 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1238 for (i = 0; i < s->mcast_list_len; i++) {
ab647872 1239 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a));
786fd2b0
DF		 1240 }
1241 }
1242}
1243
1244static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1245{
1246 vmxnet3_update_rx_mode(s);
1247 vmxnet3_update_vlan_filters(s);
1248 vmxnet3_update_mcast_filters(s);
1249}
1250
1251static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1252{
1253 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1254 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1255 return interrupt_mode;
1256}
1257
1258static void vmxnet3_fill_stats(VMXNET3State *s)
1259{
1260 int i;
c5082773 1261 PCIDevice *d = PCI_DEVICE(s);
eedeeeff
SL		 1262
1263 if (!s->device_active)
1264 return;
1265
786fd2b0 1266 for (i = 0; i < s->txq_num; i++) {
c5082773 1267 pci_dma_write(d,
11171010
DF		 1268 s->txq_descr[i].tx_stats_pa,
1269 &s->txq_descr[i].txq_stats,
1270 sizeof(s->txq_descr[i].txq_stats));
786fd2b0
DF		 1271 }
1272
1273 for (i = 0; i < s->rxq_num; i++) {
c5082773 1274 pci_dma_write(d,
11171010
DF		 1275 s->rxq_descr[i].rx_stats_pa,
1276 &s->rxq_descr[i].rxq_stats,
1277 sizeof(s->rxq_descr[i].rxq_stats));
786fd2b0
DF		 1278 }
1279}
1280
1281static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1282{
1283 struct Vmxnet3_GOSInfo gos;
c5082773 1284 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 1285
c5082773 1286 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos,
786fd2b0
DF		 1287 &gos, sizeof(gos));
1288 s->rx_packets_compound =
1289 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1290
1291 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1292}
1293
1294static void
1295vmxnet3_dump_conf_descr(const char *name,
1296 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1297{
1298 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1299 name, pm_descr->confVer, pm_descr->confLen);
1300
1301};
1302
1303static void vmxnet3_update_pm_state(VMXNET3State *s)
1304{
1305 struct Vmxnet3_VariableLenConfDesc pm_descr;
c5082773 1306 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1307
1308 pm_descr.confLen =
c5082773 1309 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen);
786fd2b0 1310 pm_descr.confVer =
c5082773 1311 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer);
786fd2b0 1312 pm_descr.confPA =
c5082773 1313 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA);
786fd2b0
DF		 1314
1315 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1316}
1317
1318static void vmxnet3_update_features(VMXNET3State *s)
1319{
1320 uint32_t guest_features;
1321 int rxcso_supported;
c5082773 1322 PCIDevice *d = PCI_DEVICE(s);
786fd2b0 1323
c5082773 1324 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
786fd2b0
DF		 1325 devRead.misc.uptFeatures);
1326
1327 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1328 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1329 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1330
1331 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1332 s->lro_supported, rxcso_supported,
1333 s->rx_vlan_stripping);
1334 if (s->peer_has_vhdr) {
d6085e3a
SH		 1335 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1336 rxcso_supported,
1337 s->lro_supported,
1338 s->lro_supported,
1339 0,
1340 0);
786fd2b0
DF		 1341 }
1342}
1343
4c89e3e5
MA		 1344static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1345{
1070048e
C		 1346 return s->msix_used || msi_enabled(PCI_DEVICE(s))
1347 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1;
4c89e3e5
MA		 1348}
1349
8c6c0478
DF		 1350static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1351{
1352 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1353 if (idx >= max_ints) {
1354 hw_error("Bad interrupt index: %d\n", idx);
1355 }
1356}
1357
1358static void vmxnet3_validate_interrupts(VMXNET3State *s)
1359{
1360 int i;
1361
1362 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1363 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1364
1365 for (i = 0; i < s->txq_num; i++) {
1366 int idx = s->txq_descr[i].intr_idx;
1367 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1368 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1369 }
1370
1371 for (i = 0; i < s->rxq_num; i++) {
1372 int idx = s->rxq_descr[i].intr_idx;
1373 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1374 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1375 }
1376}
1377
9878d173
DF		 1378static void vmxnet3_validate_queues(VMXNET3State *s)
1379{
1380 /*
1381 * txq_num and rxq_num are total number of queues
1382 * configured by guest. These numbers must not
1383 * exceed corresponding maximal values.
1384 */
1385
1386 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1387 hw_error("Bad TX queues number: %d\n", s->txq_num);
1388 }
1389
1390 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1391 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1392 }
1393}
1394
786fd2b0
DF		 1395static void vmxnet3_activate_device(VMXNET3State *s)
1396{
1397 int i;
1398 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
c5082773 1399 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1400 hwaddr qdescr_table_pa;
1401 uint64_t pa;
1402 uint32_t size;
1403
1404 /* Verify configuration consistency */
c5082773 1405 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) {
786fd2b0
DF		 1406 VMW_ERPRN("Device configuration received from driver is invalid");
1407 return;
1408 }
1409
aa4a3dce
PP		 1410 /* Verify if device is active */
1411 if (s->device_active) {
1412 VMW_CFPRN("Vmxnet3 device is active");
1413 return;
1414 }
1415
786fd2b0
DF		 1416 vmxnet3_adjust_by_guest_type(s);
1417 vmxnet3_update_features(s);
1418 vmxnet3_update_pm_state(s);
1419 vmxnet3_setup_rx_filtering(s);
1420 /* Cache fields from shared memory */
c5082773 1421 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu);
786fd2b0
DF		 1422 VMW_CFPRN("MTU is %u", s->mtu);
1423
1424 s->max_rx_frags =
c5082773 1425 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG);
786fd2b0 1426
3e948fd3
DF		 1427 if (s->max_rx_frags == 0) {
1428 s->max_rx_frags = 1;
1429 }
1430
786fd2b0
DF		 1431 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1432
1433 s->event_int_idx =
c5082773 1434 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx);
4c89e3e5 1435 assert(vmxnet3_verify_intx(s, s->event_int_idx));
786fd2b0
DF		 1436 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1437
1438 s->auto_int_masking =
c5082773 1439 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask);
786fd2b0
DF		 1440 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1441
1442 s->txq_num =
c5082773 1443 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues);
786fd2b0 1444 s->rxq_num =
c5082773 1445 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues);
786fd2b0
DF		 1446
1447 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
9878d173 1448 vmxnet3_validate_queues(s);
786fd2b0
DF		 1449
1450 qdescr_table_pa =
c5082773 1451 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA);
786fd2b0
DF		 1452 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1453
1454 /*
1455 * Worst-case scenario is a packet that holds all TX rings space so
1456 * we calculate total size of all TX rings for max TX fragments number
1457 */
1458 s->max_tx_frags = 0;
1459
1460 /* TX queues */
1461 for (i = 0; i < s->txq_num; i++) {
1462 hwaddr qdescr_pa =
1463 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1464
1465 /* Read interrupt number for this TX queue */
1466 s->txq_descr[i].intr_idx =
c5082773 1467 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx);
4c89e3e5 1468 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
786fd2b0
DF		 1469
1470 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1471
1472 /* Read rings memory locations for TX queues */
c5082773
KA		 1473 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);
1474 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize);
786fd2b0 1475
c5082773 1476 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,
786fd2b0
DF		 1477 sizeof(struct Vmxnet3_TxDesc), false);
1478 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1479
1480 s->max_tx_frags += size;
1481
1482 /* TXC ring */
c5082773
KA		 1483 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);
1484 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize);
1485 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,
786fd2b0
DF		 1486 sizeof(struct Vmxnet3_TxCompDesc), true);
1487 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1488
1489 s->txq_descr[i].tx_stats_pa =
1490 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1491
1492 memset(&s->txq_descr[i].txq_stats, 0,
1493 sizeof(s->txq_descr[i].txq_stats));
1494
1495 /* Fill device-managed parameters for queues */
c5082773 1496 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
786fd2b0
DF		 1497 ctrl.txThreshold,
1498 VMXNET3_DEF_TX_THRESHOLD);
1499 }
1500
1501 /* Preallocate TX packet wrapper */
1502 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
11171010
DF		 1503 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
1504 s->max_tx_frags, s->peer_has_vhdr);
605d52e6 1505 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
786fd2b0
DF		 1506
1507 /* Read rings memory locations for RX queues */
1508 for (i = 0; i < s->rxq_num; i++) {
1509 int j;
1510 hwaddr qd_pa =
1511 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1512 i * sizeof(struct Vmxnet3_RxQueueDesc);
1513
1514 /* Read interrupt number for this RX queue */
1515 s->rxq_descr[i].intr_idx =
c5082773 1516 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx);
4c89e3e5 1517 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
786fd2b0
DF		 1518
1519 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1520
1521 /* Read rings memory locations */
1522 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1523 /* RX rings */
c5082773
KA		 1524 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);
1525 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]);
1526 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,
786fd2b0
DF		 1527 sizeof(struct Vmxnet3_RxDesc), false);
1528 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1529 i, j, pa, size);
1530 }
1531
1532 /* RXC ring */
c5082773
KA		 1533 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);
1534 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize);
1535 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,
786fd2b0
DF		 1536 sizeof(struct Vmxnet3_RxCompDesc), true);
1537 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1538
1539 s->rxq_descr[i].rx_stats_pa =
1540 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1541 memset(&s->rxq_descr[i].rxq_stats, 0,
1542 sizeof(s->rxq_descr[i].rxq_stats));
1543 }
1544
8c6c0478
DF		 1545 vmxnet3_validate_interrupts(s);
1546
786fd2b0
DF		 1547 /* Make sure everything is in place before device activation */
1548 smp_wmb();
1549
1550 vmxnet3_reset_mac(s);
1551
1552 s->device_active = true;
1553}
1554
1555static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1556{
1557 s->last_command = cmd;
1558
1559 switch (cmd) {
1560 case VMXNET3_CMD_GET_PERM_MAC_HI:
1561 VMW_CBPRN("Set: Get upper part of permanent MAC");
1562 break;
1563
1564 case VMXNET3_CMD_GET_PERM_MAC_LO:
1565 VMW_CBPRN("Set: Get lower part of permanent MAC");
1566 break;
1567
1568 case VMXNET3_CMD_GET_STATS:
1569 VMW_CBPRN("Set: Get device statistics");
1570 vmxnet3_fill_stats(s);
1571 break;
1572
1573 case VMXNET3_CMD_ACTIVATE_DEV:
1574 VMW_CBPRN("Set: Activating vmxnet3 device");
1575 vmxnet3_activate_device(s);
1576 break;
1577
1578 case VMXNET3_CMD_UPDATE_RX_MODE:
1579 VMW_CBPRN("Set: Update rx mode");
1580 vmxnet3_update_rx_mode(s);
1581 break;
1582
1583 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1584 VMW_CBPRN("Set: Update VLAN filters");
1585 vmxnet3_update_vlan_filters(s);
1586 break;
1587
1588 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1589 VMW_CBPRN("Set: Update MAC filters");
1590 vmxnet3_update_mcast_filters(s);
1591 break;
1592
1593 case VMXNET3_CMD_UPDATE_FEATURE:
1594 VMW_CBPRN("Set: Update features");
1595 vmxnet3_update_features(s);
1596 break;
1597
1598 case VMXNET3_CMD_UPDATE_PMCFG:
1599 VMW_CBPRN("Set: Update power management config");
1600 vmxnet3_update_pm_state(s);
1601 break;
1602
1603 case VMXNET3_CMD_GET_LINK:
1604 VMW_CBPRN("Set: Get link");
1605 break;
1606
1607 case VMXNET3_CMD_RESET_DEV:
1608 VMW_CBPRN("Set: Reset device");
1609 vmxnet3_reset(s);
1610 break;
1611
1612 case VMXNET3_CMD_QUIESCE_DEV:
aa4a3dce 1613 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
786fd2b0
DF		 1614 vmxnet3_deactivate_device(s);
1615 break;
1616
1617 case VMXNET3_CMD_GET_CONF_INTR:
1618 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1619 break;
1620
d62241eb
SL		 1621 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1622 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1623 "adaptive ring info flags");
1624 break;
1625
c469669e
MY		 1626 case VMXNET3_CMD_GET_DID_LO:
1627 VMW_CBPRN("Set: Get lower part of device ID");
1628 break;
1629
1630 case VMXNET3_CMD_GET_DID_HI:
1631 VMW_CBPRN("Set: Get upper part of device ID");
1632 break;
1633
5ae3e91c
MY		 1634 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1635 VMW_CBPRN("Set: Get device extra info");
1636 break;
1637
786fd2b0
DF		 1638 default:
1639 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1640 break;
1641 }
1642}
1643
1644static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1645{
1646 uint64_t ret;
1647
1648 switch (s->last_command) {
1649 case VMXNET3_CMD_ACTIVATE_DEV:
fde58177 1650 ret = (s->device_active) ? 0 : 1;
786fd2b0
DF		 1651 VMW_CFPRN("Device active: %" PRIx64, ret);
1652 break;
1653
3e948fd3
DF		 1654 case VMXNET3_CMD_RESET_DEV:
1655 case VMXNET3_CMD_QUIESCE_DEV:
1656 case VMXNET3_CMD_GET_QUEUE_STATUS:
5ae3e91c 1657 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
3e948fd3
DF		 1658 ret = 0;
1659 break;
1660
786fd2b0
DF		 1661 case VMXNET3_CMD_GET_LINK:
1662 ret = s->link_status_and_speed;
1663 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1664 break;
1665
1666 case VMXNET3_CMD_GET_PERM_MAC_LO:
1667 ret = vmxnet3_get_mac_low(&s->perm_mac);
1668 break;
1669
1670 case VMXNET3_CMD_GET_PERM_MAC_HI:
1671 ret = vmxnet3_get_mac_high(&s->perm_mac);
1672 break;
1673
1674 case VMXNET3_CMD_GET_CONF_INTR:
1675 ret = vmxnet3_get_interrupt_config(s);
1676 break;
1677
d62241eb
SL		 1678 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1679 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1680 break;
1681
c469669e
MY		 1682 case VMXNET3_CMD_GET_DID_LO:
1683 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1684 break;
1685
1686 case VMXNET3_CMD_GET_DID_HI:
1687 ret = VMXNET3_DEVICE_REVISION;
1688 break;
1689
786fd2b0
DF		 1690 default:
1691 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
8856be15 1692 ret = 0;
786fd2b0
DF		 1693 break;
1694 }
1695
1696 return ret;
1697}
1698
1699static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1700{
1701 uint32_t events;
c5082773 1702 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1703
1704 VMW_CBPRN("Setting events: 0x%x", val);
c5082773
KA		 1705 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val;
1706 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
786fd2b0
DF		 1707}
1708
1709static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1710{
c5082773 1711 PCIDevice *d = PCI_DEVICE(s);
786fd2b0
DF		 1712 uint32_t events;
1713
1714 VMW_CBPRN("Clearing events: 0x%x", val);
c5082773
KA		 1715 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val;
1716 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
786fd2b0
DF		 1717}
1718
1719static void
1720vmxnet3_io_bar1_write(void *opaque,
1721 hwaddr addr,
1722 uint64_t val,
1723 unsigned size)
1724{
1725 VMXNET3State *s = opaque;
1726
1727 switch (addr) {
1728 /* Vmxnet3 Revision Report Selection */
1729 case VMXNET3_REG_VRRS:
1730 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1731 val, size);
1732 break;
1733
1734 /* UPT Version Report Selection */
1735 case VMXNET3_REG_UVRS:
1736 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1737 val, size);
1738 break;
1739
1740 /* Driver Shared Address Low */
1741 case VMXNET3_REG_DSAL:
1742 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1743 val, size);
1744 /*
1745 * Guest driver will first write the low part of the shared
1746 * memory address. We save it to temp variable and set the
1747 * shared address only after we get the high part
1748 */
f7472ca4 1749 if (val == 0) {
aa4a3dce 1750 vmxnet3_deactivate_device(s);
786fd2b0
DF		 1751 }
1752 s->temp_shared_guest_driver_memory = val;
1753 s->drv_shmem = 0;
1754 break;
1755
1756 /* Driver Shared Address High */
1757 case VMXNET3_REG_DSAH:
1758 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1759 val, size);
1760 /*
1761 * Set the shared memory between guest driver and device.
1762 * We already should have low address part.
1763 */
1764 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1765 break;
1766
1767 /* Command */
1768 case VMXNET3_REG_CMD:
1769 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1770 val, size);
1771 vmxnet3_handle_command(s, val);
1772 break;
1773
1774 /* MAC Address Low */
1775 case VMXNET3_REG_MACL:
1776 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1777 val, size);
1778 s->temp_mac = val;
1779 break;
1780
1781 /* MAC Address High */
1782 case VMXNET3_REG_MACH:
1783 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1784 val, size);
1785 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1786 break;
1787
1788 /* Interrupt Cause Register */
1789 case VMXNET3_REG_ICR:
1790 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1791 val, size);
dfc6f865 1792 g_assert_not_reached();
786fd2b0
DF		 1793 break;
1794
1795 /* Event Cause Register */
1796 case VMXNET3_REG_ECR:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1798 val, size);
1799 vmxnet3_ack_events(s, val);
1800 break;
1801
1802 default:
1803 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1804 addr, val, size);
1805 break;
1806 }
1807}
1808
1809static uint64_t
1810vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1811{
1812 VMXNET3State *s = opaque;
1813 uint64_t ret = 0;
1814
1815 switch (addr) {
1816 /* Vmxnet3 Revision Report Selection */
1817 case VMXNET3_REG_VRRS:
1818 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1819 ret = VMXNET3_DEVICE_REVISION;
1820 break;
1821
1822 /* UPT Version Report Selection */
1823 case VMXNET3_REG_UVRS:
1824 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
c12d82ef 1825 ret = VMXNET3_UPT_REVISION;
786fd2b0
DF		 1826 break;
1827
1828 /* Command */
1829 case VMXNET3_REG_CMD:
1830 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1831 ret = vmxnet3_get_command_status(s);
1832 break;
1833
1834 /* MAC Address Low */
1835 case VMXNET3_REG_MACL:
1836 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1837 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1838 break;
1839
1840 /* MAC Address High */
1841 case VMXNET3_REG_MACH:
1842 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1843 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1844 break;
1845
1846 /*
1847 * Interrupt Cause Register
1848 * Used for legacy interrupts only so interrupt index always 0
1849 */
1850 case VMXNET3_REG_ICR:
1851 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1852 if (vmxnet3_interrupt_asserted(s, 0)) {
1853 vmxnet3_clear_interrupt(s, 0);
1854 ret = true;
1855 } else {
1856 ret = false;
1857 }
1858 break;
1859
1860 default:
1861 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1862 break;
1863 }
1864
1865 return ret;
1866}
1867
1868static int
1869vmxnet3_can_receive(NetClientState *nc)
1870{
1871 VMXNET3State *s = qemu_get_nic_opaque(nc);
1872 return s->device_active &&
1873 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1874}
1875
1876static inline bool
1877vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1878{
1879 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1880 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1881 return true;
1882 }
1883
1884 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1885}
1886
1887static bool
1888vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1889{
1890 int i;
1891 for (i = 0; i < s->mcast_list_len; i++) {
1892 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1893 return true;
1894 }
1895 }
1896 return false;
1897}
1898
1899static bool
1900vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1901 size_t size)
1902{
1903 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1904
1905 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1906 return true;
1907 }
1908
1909 if (!vmxnet3_is_registered_vlan(s, data)) {
1910 return false;
1911 }
1912
605d52e6 1913 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
786fd2b0
DF		 1914 case ETH_PKT_UCAST:
1915 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1916 return false;
1917 }
1918 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1919 return false;
1920 }
1921 break;
1922
1923 case ETH_PKT_BCAST:
1924 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1925 return false;
1926 }
1927 break;
1928
1929 case ETH_PKT_MCAST:
1930 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1931 return true;
1932 }
1933 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1934 return false;
1935 }
1936 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1937 return false;
1938 }
1939 break;
1940
1941 default:
dfc6f865 1942 g_assert_not_reached();
786fd2b0
DF		 1943 }
1944
1945 return true;
1946}
1947
1948static ssize_t
1949vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1950{
1951 VMXNET3State *s = qemu_get_nic_opaque(nc);
1952 size_t bytes_indicated;
40a87c6c 1953 uint8_t min_buf[MIN_BUF_SIZE];
786fd2b0
DF		 1954
1955 if (!vmxnet3_can_receive(nc)) {
1956 VMW_PKPRN("Cannot receive now");
1957 return -1;
1958 }
1959
b83b5f2e 1960 if (s->peer_has_vhdr) {
605d52e6 1961 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
b83b5f2e
BK		 1962 buf += sizeof(struct virtio_net_hdr);
1963 size -= sizeof(struct virtio_net_hdr);
1964 }
1965
40a87c6c
BD		 1966 /* Pad to minimum Ethernet frame length */
1967 if (size < sizeof(min_buf)) {
1968 memcpy(min_buf, buf, size);
1969 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1970 buf = min_buf;
1971 size = sizeof(min_buf);
1972 }
1973
605d52e6 1974 net_rx_pkt_set_packet_type(s->rx_pkt,
786fd2b0
DF		 1975 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1976
1977 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
605d52e6 1978 net_rx_pkt_set_protocols(s->rx_pkt, buf, size);
80da311d 1979 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
605d52e6 1980 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
786fd2b0
DF		 1981 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
1982 if (bytes_indicated < size) {
2e4ca7db 1983 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
786fd2b0
DF		 1984 }
1985 } else {
1986 VMW_PKPRN("Packet dropped by RX filter");
1987 bytes_indicated = size;
1988 }
1989
1990 assert(size > 0);
1991 assert(bytes_indicated != 0);
1992 return bytes_indicated;
1993}
1994
786fd2b0
DF		 1995static void vmxnet3_set_link_status(NetClientState *nc)
1996{
1997 VMXNET3State *s = qemu_get_nic_opaque(nc);
1998
1999 if (nc->link_down) {
2000 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2001 } else {
2002 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2003 }
2004
2005 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2006 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2007}
2008
2009static NetClientInfo net_vmxnet3_info = {
f394b2e2 2010 .type = NET_CLIENT_DRIVER_NIC,
786fd2b0 2011 .size = sizeof(NICState),
786fd2b0 2012 .receive = vmxnet3_receive,
786fd2b0
DF		 2013 .link_status_changed = vmxnet3_set_link_status,
2014};
2015
2016static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2017{
cf528b89 2018 NetClientState *nc = qemu_get_queue(s->nic);
786fd2b0 2019
d6085e3a 2020 if (qemu_has_vnet_hdr(nc->peer)) {
786fd2b0
DF		 2021 return true;
2022 }
2023
786fd2b0
DF		 2024 return false;
2025}
2026
2027static void vmxnet3_net_uninit(VMXNET3State *s)
2028{
2029 g_free(s->mcast_list);
aa4a3dce 2030 vmxnet3_deactivate_device(s);
3ffee3cd 2031 qemu_del_nic(s->nic);
786fd2b0
DF		 2032}
2033
2034static void vmxnet3_net_init(VMXNET3State *s)
2035{
2036 DeviceState *d = DEVICE(s);
2037
2038 VMW_CBPRN("vmxnet3_net_init called...");
2039
2040 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2041
2042 /* Windows guest will query the address that was set on init */
2043 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2044
2045 s->mcast_list = NULL;
2046 s->mcast_list_len = 0;
2047
2048 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2049
ab647872 2050 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
786fd2b0
DF		 2051
2052 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2053 object_get_typename(OBJECT(s)),
2054 d->id, s);
2055
2056 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2057 s->tx_sop = true;
2058 s->skip_current_tx_pkt = false;
2059 s->tx_pkt = NULL;
2060 s->rx_pkt = NULL;
2061 s->rx_vlan_stripping = false;
2062 s->lro_supported = false;
2063
2064 if (s->peer_has_vhdr) {
d6085e3a 2065 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
786fd2b0
DF		 2066 sizeof(struct virtio_net_hdr));
2067
d6085e3a 2068 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
786fd2b0
DF		 2069 }
2070
2071 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2072}
2073
2074static void
2075vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2076{
2077 PCIDevice *d = PCI_DEVICE(s);
2078 int i;
2079 for (i = 0; i < num_vectors; i++) {
2080 msix_vector_unuse(d, i);
2081 }
2082}
2083
2084static bool
2085vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2086{
2087 PCIDevice *d = PCI_DEVICE(s);
2088 int i;
2089 for (i = 0; i < num_vectors; i++) {
2090 int res = msix_vector_use(d, i);
2091 if (0 > res) {
2092 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2093 vmxnet3_unuse_msix_vectors(s, i);
2094 return false;
2095 }
2096 }
2097 return true;
2098}
2099
2100static bool
2101vmxnet3_init_msix(VMXNET3State *s)
2102{
2103 PCIDevice *d = PCI_DEVICE(s);
2104 int res = msix_init(d, VMXNET3_MAX_INTRS,
2105 &s->msix_bar,
2106 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2107 &s->msix_bar,
9c087a05 2108 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
ee640c62 2109 VMXNET3_MSIX_OFFSET(s), NULL);
786fd2b0
DF		 2110
2111 if (0 > res) {
2112 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2113 s->msix_used = false;
2114 } else {
2115 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2116 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2117 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2118 s->msix_used = false;
2119 } else {
2120 s->msix_used = true;
2121 }
2122 }
2123 return s->msix_used;
2124}
2125
2126static void
2127vmxnet3_cleanup_msix(VMXNET3State *s)
2128{
2129 PCIDevice *d = PCI_DEVICE(s);
2130
2131 if (s->msix_used) {
b4467284 2132 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
786fd2b0
DF		 2133 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2134 }
2135}
2136
786fd2b0
DF		 2137static void
2138vmxnet3_cleanup_msi(VMXNET3State *s)
2139{
2140 PCIDevice *d = PCI_DEVICE(s);
2141
1070048e 2142 msi_uninit(d);
786fd2b0
DF		 2143}
2144
2145static void
2146vmxnet3_msix_save(QEMUFile *f, void *opaque)
2147{
2148 PCIDevice *d = PCI_DEVICE(opaque);
2149 msix_save(d, f);
2150}
2151
2152static int
2153vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2154{
2155 PCIDevice *d = PCI_DEVICE(opaque);
2156 msix_load(d, f);
2157 return 0;
2158}
2159
2160static const MemoryRegionOps b0_ops = {
2161 .read = vmxnet3_io_bar0_read,
2162 .write = vmxnet3_io_bar0_write,
2163 .endianness = DEVICE_LITTLE_ENDIAN,
2164 .impl = {
2165 .min_access_size = 4,
2166 .max_access_size = 4,
2167 },
2168};
2169
2170static const MemoryRegionOps b1_ops = {
2171 .read = vmxnet3_io_bar1_read,
2172 .write = vmxnet3_io_bar1_write,
2173 .endianness = DEVICE_LITTLE_ENDIAN,
2174 .impl = {
2175 .min_access_size = 4,
2176 .max_access_size = 4,
2177 },
2178};
2179
1b6e7482
LV		 2180static SaveVMHandlers savevm_vmxnet3_msix = {
2181 .save_state = vmxnet3_msix_save,
2182 .load_state = vmxnet3_msix_load,
2183};
2184
a4b387e6 2185static uint64_t vmxnet3_device_serial_num(VMXNET3State *s)
3509866a 2186{
a4b387e6 2187 uint64_t dsn_payload;
3509866a
SL		 2188 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2189
2190 dsnp[0] = 0xfe;
2191 dsnp[1] = s->conf.macaddr.a[3];
2192 dsnp[2] = s->conf.macaddr.a[4];
2193 dsnp[3] = s->conf.macaddr.a[5];
2194 dsnp[4] = s->conf.macaddr.a[0];
2195 dsnp[5] = s->conf.macaddr.a[1];
2196 dsnp[6] = s->conf.macaddr.a[2];
2197 dsnp[7] = 0xff;
a4b387e6 2198 return dsn_payload;
3509866a
SL		 2199}
2200
1108b2f8
C		 2201
2202#define VMXNET3_USE_64BIT (true)
2203#define VMXNET3_PER_VECTOR_MASK (false)
2204
9af21dbe 2205static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
786fd2b0
DF		 2206{
2207 DeviceState *dev = DEVICE(pci_dev);
2208 VMXNET3State *s = VMXNET3(pci_dev);
1108b2f8 2209 int ret;
786fd2b0
DF		 2210
2211 VMW_CBPRN("Starting init...");
2212
eedfac6f 2213 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
786fd2b0
DF		 2214 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2215 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2216 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2217
eedfac6f 2218 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
786fd2b0
DF		 2219 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2220 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2221 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2222
eedfac6f 2223 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
786fd2b0
DF		 2224 VMXNET3_MSIX_BAR_SIZE);
2225 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2226 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2227
2228 vmxnet3_reset_interrupt_states(s);
2229
2230 /* Interrupt pin A */
2231 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2232
1108b2f8
C		 2233 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
2234 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
2235 /* Any error other than -ENOTSUP(board's MSI support is broken)
2236 * is a programming error. Fall back to INTx silently on -ENOTSUP */
2237 assert(!ret || ret == -ENOTSUP);
1108b2f8 2238
786fd2b0
DF		 2239 if (!vmxnet3_init_msix(s)) {
2240 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2241 }
2242
786fd2b0
DF		 2243 vmxnet3_net_init(s);
2244
3509866a 2245 if (pci_is_express(pci_dev)) {
fd56e061 2246 if (pci_bus_is_express(pci_get_bus(pci_dev))) {
3509866a
SL		 2247 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2248 }
2249
a4b387e6
DF		 2250 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
2251 vmxnet3_device_serial_num(s));
f713d4d2
SL		 2252 }
2253
1b6e7482 2254 register_savevm_live(dev, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix, s);
786fd2b0
DF		 2255}
2256
e25524ef
GA		 2257static void vmxnet3_instance_init(Object *obj)
2258{
2259 VMXNET3State *s = VMXNET3(obj);
2260 device_add_bootindex_property(obj, &s->conf.bootindex,
2261 "bootindex", "/ethernet-phy@0",
2262 DEVICE(obj), NULL);
2263}
786fd2b0
DF		 2264
2265static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2266{
2267 DeviceState *dev = DEVICE(pci_dev);
2268 VMXNET3State *s = VMXNET3(pci_dev);
2269
2270 VMW_CBPRN("Starting uninit...");
2271
2272 unregister_savevm(dev, "vmxnet3-msix", s);
2273
2274 vmxnet3_net_uninit(s);
2275
2276 vmxnet3_cleanup_msix(s);
2277
2278 vmxnet3_cleanup_msi(s);
786fd2b0
DF		 2279}
2280
2281static void vmxnet3_qdev_reset(DeviceState *dev)
2282{
2283 PCIDevice *d = PCI_DEVICE(dev);
2284 VMXNET3State *s = VMXNET3(d);
2285
2286 VMW_CBPRN("Starting QDEV reset...");
2287 vmxnet3_reset(s);
2288}
2289
2290static bool vmxnet3_mc_list_needed(void *opaque)
2291{
2292 return true;
2293}
2294
2295static int vmxnet3_mcast_list_pre_load(void *opaque)
2296{
2297 VMXNET3State *s = opaque;
2298
2299 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2300
2301 return 0;
2302}
2303
2304
44b1ff31 2305static int vmxnet3_pre_save(void *opaque)
786fd2b0
DF		 2306{
2307 VMXNET3State *s = opaque;
2308
2309 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
44b1ff31
DDAG		 2310
2311 return 0;
786fd2b0
DF		 2312}
2313
2314static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2315 .name = "vmxnet3/mcast_list",
2316 .version_id = 1,
2317 .minimum_version_id = 1,
786fd2b0 2318 .pre_load = vmxnet3_mcast_list_pre_load,
5cd8cada 2319 .needed = vmxnet3_mc_list_needed,
786fd2b0 2320 .fields = (VMStateField[]) {
59046ec2 2321 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL,
786fd2b0
DF		 2322 mcast_list_buff_size),
2323 VMSTATE_END_OF_LIST()
2324 }
2325};
2326
a11f5cb0
DDAG		 2327static const VMStateDescription vmstate_vmxnet3_ring = {
2328 .name = "vmxnet3-ring",
2329 .version_id = 0,
2330 .fields = (VMStateField[]) {
2331 VMSTATE_UINT64(pa, Vmxnet3Ring),
2332 VMSTATE_UINT32(size, Vmxnet3Ring),
2333 VMSTATE_UINT32(cell_size, Vmxnet3Ring),
2334 VMSTATE_UINT32(next, Vmxnet3Ring),
2335 VMSTATE_UINT8(gen, Vmxnet3Ring),
2336 VMSTATE_END_OF_LIST()
2337 }
786fd2b0
DF		 2338};
2339
a11f5cb0
DDAG		 2340static const VMStateDescription vmstate_vmxnet3_tx_stats = {
2341 .name = "vmxnet3-tx-stats",
2342 .version_id = 0,
2343 .fields = (VMStateField[]) {
2344 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats),
2345 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats),
2346 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats),
2347 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats),
2348 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats),
2349 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats),
2350 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats),
2351 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats),
2352 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats),
2353 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats),
2354 VMSTATE_END_OF_LIST()
786fd2b0 2355 }
a11f5cb0 2356};
786fd2b0 2357
a11f5cb0
DDAG		 2358static const VMStateDescription vmstate_vmxnet3_txq_descr = {
2359 .name = "vmxnet3-txq-descr",
2360 .version_id = 0,
2361 .fields = (VMStateField[]) {
2362 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2363 Vmxnet3Ring),
2364 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2365 Vmxnet3Ring),
2366 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr),
2367 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr),
2368 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats,
2369 struct UPT1_TxStats),
2370 VMSTATE_END_OF_LIST()
786fd2b0 2371 }
a11f5cb0 2372};
786fd2b0 2373
a11f5cb0
DDAG		 2374static const VMStateDescription vmstate_vmxnet3_rx_stats = {
2375 .name = "vmxnet3-rx-stats",
2376 .version_id = 0,
2377 .fields = (VMStateField[]) {
2378 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats),
2379 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats),
2380 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats),
2381 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats),
2382 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats),
2383 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats),
2384 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats),
2385 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats),
2386 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats),
2387 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats),
2388 VMSTATE_END_OF_LIST()
2389 }
2390};
2c21ee76 2391
a11f5cb0
DDAG		 2392static const VMStateDescription vmstate_vmxnet3_rxq_descr = {
2393 .name = "vmxnet3-rxq-descr",
2394 .version_id = 0,
2395 .fields = (VMStateField[]) {
2396 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr,
2397 VMXNET3_RX_RINGS_PER_QUEUE, 0,
2398 vmstate_vmxnet3_ring, Vmxnet3Ring),
2399 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring,
2400 Vmxnet3Ring),
2401 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr),
2402 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr),
2403 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats,
2404 struct UPT1_RxStats),
2405 VMSTATE_END_OF_LIST()
2406 }
2407};
786fd2b0
DF		 2408
2409static int vmxnet3_post_load(void *opaque, int version_id)
2410{
2411 VMXNET3State *s = opaque;
2412 PCIDevice *d = PCI_DEVICE(s);
2413
11171010
DF		 2414 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
2415 s->max_tx_frags, s->peer_has_vhdr);
605d52e6 2416 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
786fd2b0
DF		 2417
2418 if (s->msix_used) {
2419 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2420 VMW_WRPRN("Failed to re-use MSI-X vectors");
2421 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2422 s->msix_used = false;
2423 return -1;
2424 }
2425 }
2426
f12d048a 2427 vmxnet3_validate_queues(s);
3c99afc7
DF		 2428 vmxnet3_validate_interrupts(s);
2429
786fd2b0
DF		 2430 return 0;
2431}
2432
a11f5cb0
DDAG		 2433static const VMStateDescription vmstate_vmxnet3_int_state = {
2434 .name = "vmxnet3-int-state",
2435 .version_id = 0,
2436 .fields = (VMStateField[]) {
2437 VMSTATE_BOOL(is_masked, Vmxnet3IntState),
2438 VMSTATE_BOOL(is_pending, Vmxnet3IntState),
2439 VMSTATE_BOOL(is_asserted, Vmxnet3IntState),
2440 VMSTATE_END_OF_LIST()
2441 }
786fd2b0
DF		 2442};
2443
f713d4d2
SL		 2444static bool vmxnet3_vmstate_need_pcie_device(void *opaque)
2445{
2446 VMXNET3State *s = VMXNET3(opaque);
2447
2448 return !(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE);
2449}
2450
2451static bool vmxnet3_vmstate_test_pci_device(void *opaque, int version_id)
2452{
2453 return !vmxnet3_vmstate_need_pcie_device(opaque);
2454}
2455
2456static const VMStateDescription vmstate_vmxnet3_pcie_device = {
2457 .name = "vmxnet3/pcie",
2458 .version_id = 1,
2459 .minimum_version_id = 1,
2460 .needed = vmxnet3_vmstate_need_pcie_device,
2461 .fields = (VMStateField[]) {
20daa90a 2462 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
f713d4d2
SL		 2463 VMSTATE_END_OF_LIST()
2464 }
2465};
2466
786fd2b0
DF		 2467static const VMStateDescription vmstate_vmxnet3 = {
2468 .name = "vmxnet3",
2469 .version_id = 1,
2470 .minimum_version_id = 1,
786fd2b0
DF		 2471 .pre_save = vmxnet3_pre_save,
2472 .post_load = vmxnet3_post_load,
d49805ae 2473 .fields = (VMStateField[]) {
f713d4d2
SL		 2474 VMSTATE_STRUCT_TEST(parent_obj, VMXNET3State,
2475 vmxnet3_vmstate_test_pci_device, 0,
2476 vmstate_pci_device, PCIDevice),
786fd2b0
DF		 2477 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2478 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2479 VMSTATE_BOOL(lro_supported, VMXNET3State),
2480 VMSTATE_UINT32(rx_mode, VMXNET3State),
2481 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2482 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2483 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2484 VMSTATE_UINT32(mtu, VMXNET3State),
2485 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2486 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2487 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2488 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2489 VMSTATE_UINT8(txq_num, VMXNET3State),
2490 VMSTATE_UINT8(rxq_num, VMXNET3State),
2491 VMSTATE_UINT32(device_active, VMXNET3State),
2492 VMSTATE_UINT32(last_command, VMXNET3State),
2493 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2494 VMSTATE_UINT32(temp_mac, VMXNET3State),
2495 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2496 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2497
a11f5cb0
DDAG		 2498 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State,
2499 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr,
786fd2b0 2500 Vmxnet3TxqDescr),
a11f5cb0
DDAG		 2501 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State,
2502 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr,
786fd2b0 2503 Vmxnet3RxqDescr),
a11f5cb0
DDAG		 2504 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State,
2505 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state,
2506 Vmxnet3IntState),
786fd2b0
DF		 2507
2508 VMSTATE_END_OF_LIST()
2509 },
5cd8cada
JQ		 2510 .subsections = (const VMStateDescription*[]) {
2511 &vmxstate_vmxnet3_mcast_list,
f713d4d2 2512 &vmstate_vmxnet3_pcie_device,
5cd8cada 2513 NULL
786fd2b0
DF		 2514 }
2515};
2516
786fd2b0
DF		 2517static Property vmxnet3_properties[] = {
2518 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
b22e0aef
SL		 2519 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
2520 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
7d6d347d
SL		 2521 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
2522 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
786fd2b0
DF		 2523 DEFINE_PROP_END_OF_LIST(),
2524};
2525
f713d4d2
SL		 2526static void vmxnet3_realize(DeviceState *qdev, Error **errp)
2527{
2528 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
2529 PCIDevice *pci_dev = PCI_DEVICE(qdev);
2530 VMXNET3State *s = VMXNET3(qdev);
2531
2532 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
2533 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2534 }
2535
2536 vc->parent_dc_realize(qdev, errp);
2537}
2538
786fd2b0
DF		 2539static void vmxnet3_class_init(ObjectClass *class, void *data)
2540{
2541 DeviceClass *dc = DEVICE_CLASS(class);
2542 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
f713d4d2 2543 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
786fd2b0 2544
9af21dbe 2545 c->realize = vmxnet3_pci_realize;
786fd2b0
DF		 2546 c->exit = vmxnet3_pci_uninit;
2547 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2548 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2549 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
43716de6 2550 c->romfile = "efi-vmxnet3.rom";
786fd2b0
DF		 2551 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2552 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2553 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
bf853881
PMD		 2554 device_class_set_parent_realize(dc, vmxnet3_realize,
2555 &vc->parent_dc_realize);
786fd2b0
DF		 2556 dc->desc = "VMWare Paravirtualized Ethernet v3";
2557 dc->reset = vmxnet3_qdev_reset;
2558 dc->vmsd = &vmstate_vmxnet3;
2559 dc->props = vmxnet3_properties;
125ee0ed 2560 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
786fd2b0
DF		 2561}
2562
2563static const TypeInfo vmxnet3_info = {
2564 .name = TYPE_VMXNET3,
2565 .parent = TYPE_PCI_DEVICE,
b79f17a9 2566 .class_size = sizeof(VMXNET3Class),
786fd2b0
DF		 2567 .instance_size = sizeof(VMXNET3State),
2568 .class_init = vmxnet3_class_init,
e25524ef 2569 .instance_init = vmxnet3_instance_init,
a5fa336f
EH		 2570 .interfaces = (InterfaceInfo[]) {
2571 { INTERFACE_PCIE_DEVICE },
2572 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2573 { }
2574 },
786fd2b0
DF		 2575};
2576
2577static void vmxnet3_register_types(void)
2578{
2579 VMW_CBPRN("vmxnet3_register_types called...");
2580 type_register_static(&vmxnet3_info);
2581}
2582
2583type_init(vmxnet3_register_types)
Mirror of https://git.qemu.org/git/qemu.git