]>
Commit | Line | Data |
---|---|---|
3cce6243 BS |
1 | /* |
2 | * QEMU Firmware configuration device emulation | |
3 | * | |
4 | * Copyright (c) 2008 Gleb Natapov | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
922a01a0 | 24 | |
0430891c | 25 | #include "qemu/osdep.h" |
a8d25326 | 26 | #include "qemu-common.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
a4c0d1de | 29 | #include "sysemu/dma.h" |
71e8a915 | 30 | #include "sysemu/reset.h" |
cfc58cf3 | 31 | #include "hw/boards.h" |
0d09e41a | 32 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
ca77ee28 | 34 | #include "migration/qemu-file-types.h" |
d6454270 | 35 | #include "migration/vmstate.h" |
f6e35343 | 36 | #include "trace.h" |
1de7afc9 | 37 | #include "qemu/error-report.h" |
922a01a0 | 38 | #include "qemu/option.h" |
1de7afc9 | 39 | #include "qemu/config-file.h" |
f348b6d1 | 40 | #include "qemu/cutils.h" |
e12f3a13 | 41 | #include "qapi/error.h" |
3cce6243 | 42 | |
a5b3ebfd LE |
43 | #define FW_CFG_FILE_SLOTS_DFLT 0x20 |
44 | ||
a4c0d1de MM |
45 | /* FW_CFG_VERSION bits */ |
46 | #define FW_CFG_VERSION 0x01 | |
47 | #define FW_CFG_VERSION_DMA 0x02 | |
48 | ||
49 | /* FW_CFG_DMA_CONTROL bits */ | |
50 | #define FW_CFG_DMA_CTL_ERROR 0x01 | |
51 | #define FW_CFG_DMA_CTL_READ 0x02 | |
52 | #define FW_CFG_DMA_CTL_SKIP 0x04 | |
53 | #define FW_CFG_DMA_CTL_SELECT 0x08 | |
baf2d5bf | 54 | #define FW_CFG_DMA_CTL_WRITE 0x10 |
a4c0d1de | 55 | |
2cc06a88 KC |
56 | #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */ |
57 | ||
39736e18 | 58 | struct FWCfgEntry { |
ff06108b | 59 | uint32_t len; |
baf2d5bf | 60 | bool allow_write; |
3cce6243 BS |
61 | uint8_t *data; |
62 | void *callback_opaque; | |
6f6f4aec | 63 | FWCfgCallback select_cb; |
5f9252f7 | 64 | FWCfgWriteCallback write_cb; |
5712db6a LE |
65 | }; |
66 | ||
1f80b0d6 PMD |
67 | /** |
68 | * key_name: | |
69 | * | |
70 | * @key: The uint16 selector key. | |
71 | * | |
72 | * Returns: The stringified name if the selector refers to a well-known | |
73 | * numerically defined item, or NULL on key lookup failure. | |
74 | */ | |
75 | static const char *key_name(uint16_t key) | |
76 | { | |
77 | static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = { | |
78 | [FW_CFG_SIGNATURE] = "signature", | |
79 | [FW_CFG_ID] = "id", | |
80 | [FW_CFG_UUID] = "uuid", | |
81 | [FW_CFG_RAM_SIZE] = "ram_size", | |
82 | [FW_CFG_NOGRAPHIC] = "nographic", | |
83 | [FW_CFG_NB_CPUS] = "nb_cpus", | |
84 | [FW_CFG_MACHINE_ID] = "machine_id", | |
85 | [FW_CFG_KERNEL_ADDR] = "kernel_addr", | |
86 | [FW_CFG_KERNEL_SIZE] = "kernel_size", | |
87 | [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline", | |
88 | [FW_CFG_INITRD_ADDR] = "initrd_addr", | |
89 | [FW_CFG_INITRD_SIZE] = "initdr_size", | |
90 | [FW_CFG_BOOT_DEVICE] = "boot_device", | |
91 | [FW_CFG_NUMA] = "numa", | |
92 | [FW_CFG_BOOT_MENU] = "boot_menu", | |
93 | [FW_CFG_MAX_CPUS] = "max_cpus", | |
94 | [FW_CFG_KERNEL_ENTRY] = "kernel_entry", | |
95 | [FW_CFG_KERNEL_DATA] = "kernel_data", | |
96 | [FW_CFG_INITRD_DATA] = "initrd_data", | |
97 | [FW_CFG_CMDLINE_ADDR] = "cmdline_addr", | |
98 | [FW_CFG_CMDLINE_SIZE] = "cmdline_size", | |
99 | [FW_CFG_CMDLINE_DATA] = "cmdline_data", | |
100 | [FW_CFG_SETUP_ADDR] = "setup_addr", | |
101 | [FW_CFG_SETUP_SIZE] = "setup_size", | |
102 | [FW_CFG_SETUP_DATA] = "setup_data", | |
103 | [FW_CFG_FILE_DIR] = "file_dir", | |
104 | }; | |
105 | ||
106 | if (key & FW_CFG_ARCH_LOCAL) { | |
b15c0f7d | 107 | return fw_cfg_arch_key_name(key); |
1f80b0d6 PMD |
108 | } |
109 | if (key < FW_CFG_FILE_FIRST) { | |
110 | return fw_cfg_wellknown_keys[key]; | |
111 | } | |
112 | ||
113 | return NULL; | |
114 | } | |
115 | ||
116 | static inline const char *trace_key_name(uint16_t key) | |
117 | { | |
118 | const char *name = key_name(key); | |
119 | ||
120 | return name ? name : "unknown"; | |
121 | } | |
122 | ||
3d3b8303 WX |
123 | #define JPG_FILE 0 |
124 | #define BMP_FILE 1 | |
125 | ||
3d1bba20 | 126 | static char *read_splashfile(char *filename, gsize *file_sizep, |
d09acb9b | 127 | int *file_typep) |
3d3b8303 | 128 | { |
9477c87e | 129 | GError *err = NULL; |
9477c87e | 130 | gchar *content; |
9f8863eb MA |
131 | int file_type; |
132 | unsigned int filehead; | |
3d3b8303 WX |
133 | int bmp_bpp; |
134 | ||
bed66336 LQ |
135 | if (!g_file_get_contents(filename, &content, file_sizep, &err)) { |
136 | error_report("failed to read splash file '%s': %s", | |
137 | filename, err->message); | |
9477c87e PB |
138 | g_error_free(err); |
139 | return NULL; | |
3d3b8303 | 140 | } |
9477c87e | 141 | |
3d3b8303 | 142 | /* check file size */ |
9477c87e PB |
143 | if (*file_sizep < 30) { |
144 | goto error; | |
3d3b8303 | 145 | } |
9477c87e | 146 | |
3d3b8303 | 147 | /* check magic ID */ |
3b777a79 | 148 | filehead = lduw_le_p(content); |
9477c87e | 149 | if (filehead == 0xd8ff) { |
3d3b8303 | 150 | file_type = JPG_FILE; |
9477c87e PB |
151 | } else if (filehead == 0x4d42) { |
152 | file_type = BMP_FILE; | |
3d3b8303 | 153 | } else { |
9477c87e | 154 | goto error; |
3d3b8303 | 155 | } |
9477c87e | 156 | |
3d3b8303 WX |
157 | /* check BMP bpp */ |
158 | if (file_type == BMP_FILE) { | |
3b777a79 | 159 | bmp_bpp = lduw_le_p(&content[28]); |
3d3b8303 | 160 | if (bmp_bpp != 24) { |
9477c87e | 161 | goto error; |
3d3b8303 WX |
162 | } |
163 | } | |
9477c87e | 164 | |
3d3b8303 | 165 | /* return values */ |
3d3b8303 | 166 | *file_typep = file_type; |
9477c87e PB |
167 | |
168 | return content; | |
169 | ||
170 | error: | |
171 | error_report("splash file '%s' format not recognized; must be JPEG " | |
172 | "or 24 bit BMP", filename); | |
173 | g_free(content); | |
174 | return NULL; | |
3d3b8303 WX |
175 | } |
176 | ||
177 | static void fw_cfg_bootsplash(FWCfgState *s) | |
178 | { | |
3d3b8303 | 179 | const char *boot_splash_filename = NULL; |
6912bb0b | 180 | const char *boot_splash_time = NULL; |
9477c87e | 181 | char *filename, *file_data; |
3d1bba20 | 182 | gsize file_size; |
9f8863eb | 183 | int file_type; |
3d3b8303 WX |
184 | |
185 | /* get user configuration */ | |
186 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
187 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
6912bb0b LQ |
188 | boot_splash_filename = qemu_opt_get(opts, "splash"); |
189 | boot_splash_time = qemu_opt_get(opts, "splash-time"); | |
3d3b8303 WX |
190 | |
191 | /* insert splash time if user configurated */ | |
6912bb0b LQ |
192 | if (boot_splash_time) { |
193 | int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1); | |
3b3df3e5 LE |
194 | uint16_t bst_le16; |
195 | ||
3d3b8303 | 196 | /* validate the input */ |
6912bb0b LQ |
197 | if (bst_val < 0 || bst_val > 0xffff) { |
198 | error_report("splash-time is invalid," | |
199 | "it should be a value between 0 and 65535"); | |
200 | exit(1); | |
3d3b8303 WX |
201 | } |
202 | /* use little endian format */ | |
3b3df3e5 LE |
203 | bst_le16 = cpu_to_le16(bst_val); |
204 | fw_cfg_add_file(s, "etc/boot-menu-wait", | |
205 | g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16); | |
3d3b8303 WX |
206 | } |
207 | ||
208 | /* insert splash file if user configurated */ | |
6912bb0b | 209 | if (boot_splash_filename) { |
3d3b8303 WX |
210 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); |
211 | if (filename == NULL) { | |
6912bb0b | 212 | error_report("failed to find file '%s'", boot_splash_filename); |
3d3b8303 WX |
213 | return; |
214 | } | |
9477c87e PB |
215 | |
216 | /* loading file data */ | |
217 | file_data = read_splashfile(filename, &file_size, &file_type); | |
218 | if (file_data == NULL) { | |
7267c094 | 219 | g_free(filename); |
3d3b8303 WX |
220 | return; |
221 | } | |
ef1e1e07 | 222 | g_free(boot_splash_filedata); |
9477c87e | 223 | boot_splash_filedata = (uint8_t *)file_data; |
9477c87e | 224 | |
3d3b8303 WX |
225 | /* insert data */ |
226 | if (file_type == JPG_FILE) { | |
227 | fw_cfg_add_file(s, "bootsplash.jpg", | |
96f209b9 | 228 | boot_splash_filedata, file_size); |
3d3b8303 WX |
229 | } else { |
230 | fw_cfg_add_file(s, "bootsplash.bmp", | |
96f209b9 | 231 | boot_splash_filedata, file_size); |
3d3b8303 | 232 | } |
7267c094 | 233 | g_free(filename); |
3d3b8303 WX |
234 | } |
235 | } | |
236 | ||
ac05f349 AK |
237 | static void fw_cfg_reboot(FWCfgState *s) |
238 | { | |
ee5d0f89 LQ |
239 | const char *reboot_timeout = NULL; |
240 | int64_t rt_val = -1; | |
04da9735 | 241 | uint32_t rt_le32; |
ac05f349 AK |
242 | |
243 | /* get user configuration */ | |
244 | QemuOptsList *plist = qemu_find_opts("boot-opts"); | |
245 | QemuOpts *opts = QTAILQ_FIRST(&plist->head); | |
ee5d0f89 LQ |
246 | reboot_timeout = qemu_opt_get(opts, "reboot-timeout"); |
247 | ||
248 | if (reboot_timeout) { | |
249 | rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1); | |
250 | /* validate the input */ | |
251 | if (rt_val < 0 || rt_val > 0xffff) { | |
252 | error_report("reboot timeout is invalid," | |
253 | "it should be a value between 0 and 65535"); | |
254 | exit(1); | |
ac05f349 AK |
255 | } |
256 | } | |
ee5d0f89 | 257 | |
04da9735 LQ |
258 | rt_le32 = cpu_to_le32(rt_val); |
259 | fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4); | |
ac05f349 AK |
260 | } |
261 | ||
3cce6243 BS |
262 | static void fw_cfg_write(FWCfgState *s, uint8_t value) |
263 | { | |
023e3148 | 264 | /* nothing, write support removed in QEMU v2.4+ */ |
3cce6243 BS |
265 | } |
266 | ||
e12f3a13 LE |
267 | static inline uint16_t fw_cfg_file_slots(const FWCfgState *s) |
268 | { | |
269 | return s->file_slots; | |
270 | } | |
271 | ||
272 | /* Note: this function returns an exclusive limit. */ | |
273 | static inline uint32_t fw_cfg_max_entry(const FWCfgState *s) | |
274 | { | |
275 | return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s); | |
276 | } | |
277 | ||
3cce6243 BS |
278 | static int fw_cfg_select(FWCfgState *s, uint16_t key) |
279 | { | |
3bef7e8a GS |
280 | int arch, ret; |
281 | FWCfgEntry *e; | |
3cce6243 BS |
282 | |
283 | s->cur_offset = 0; | |
e12f3a13 | 284 | if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) { |
3cce6243 BS |
285 | s->cur_entry = FW_CFG_INVALID; |
286 | ret = 0; | |
287 | } else { | |
288 | s->cur_entry = key; | |
289 | ret = 1; | |
3bef7e8a GS |
290 | /* entry successfully selected, now run callback if present */ |
291 | arch = !!(key & FW_CFG_ARCH_LOCAL); | |
292 | e = &s->entries[arch][key & FW_CFG_ENTRY_MASK]; | |
6f6f4aec MAL |
293 | if (e->select_cb) { |
294 | e->select_cb(e->callback_opaque); | |
3bef7e8a | 295 | } |
3cce6243 BS |
296 | } |
297 | ||
1f80b0d6 | 298 | trace_fw_cfg_select(s, key, trace_key_name(key), ret); |
3cce6243 BS |
299 | return ret; |
300 | } | |
301 | ||
38bf2093 GS |
302 | static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size) |
303 | { | |
304 | FWCfgState *s = opaque; | |
305 | int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
306 | FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL : | |
307 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
308 | uint64_t value = 0; | |
309 | ||
310 | assert(size > 0 && size <= sizeof(value)); | |
311 | if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) { | |
312 | /* The least significant 'size' bytes of the return value are | |
313 | * expected to contain a string preserving portion of the item | |
314 | * data, padded with zeros on the right in case we run out early. | |
315 | * In technical terms, we're composing the host-endian representation | |
316 | * of the big endian interpretation of the fw_cfg string. | |
317 | */ | |
318 | do { | |
319 | value = (value << 8) | e->data[s->cur_offset++]; | |
320 | } while (--size && s->cur_offset < e->len); | |
321 | /* If size is still not zero, we *did* run out early, so continue | |
322 | * left-shifting, to add the appropriate number of padding zeros | |
323 | * on the right. | |
324 | */ | |
325 | value <<= 8 * size; | |
326 | } | |
327 | ||
328 | trace_fw_cfg_read(s, value); | |
329 | return value; | |
330 | } | |
331 | ||
a8170e5e | 332 | static void fw_cfg_data_mem_write(void *opaque, hwaddr addr, |
561e1827 | 333 | uint64_t value, unsigned size) |
3cce6243 | 334 | { |
cfaadf0e | 335 | FWCfgState *s = opaque; |
36b62ae6 | 336 | unsigned i = size; |
cfaadf0e | 337 | |
36b62ae6 LE |
338 | do { |
339 | fw_cfg_write(s, value >> (8 * --i)); | |
340 | } while (i); | |
cfaadf0e LE |
341 | } |
342 | ||
a4c0d1de MM |
343 | static void fw_cfg_dma_transfer(FWCfgState *s) |
344 | { | |
345 | dma_addr_t len; | |
346 | FWCfgDmaAccess dma; | |
347 | int arch; | |
348 | FWCfgEntry *e; | |
baf2d5bf | 349 | int read = 0, write = 0; |
a4c0d1de MM |
350 | dma_addr_t dma_addr; |
351 | ||
352 | /* Reset the address before the next access */ | |
353 | dma_addr = s->dma_addr; | |
354 | s->dma_addr = 0; | |
355 | ||
356 | if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { | |
357 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
358 | FW_CFG_DMA_CTL_ERROR); | |
359 | return; | |
360 | } | |
361 | ||
362 | dma.address = be64_to_cpu(dma.address); | |
363 | dma.length = be32_to_cpu(dma.length); | |
364 | dma.control = be32_to_cpu(dma.control); | |
365 | ||
366 | if (dma.control & FW_CFG_DMA_CTL_SELECT) { | |
367 | fw_cfg_select(s, dma.control >> 16); | |
368 | } | |
369 | ||
370 | arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); | |
66f8fd9d GS |
371 | e = (s->cur_entry == FW_CFG_INVALID) ? NULL : |
372 | &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; | |
a4c0d1de MM |
373 | |
374 | if (dma.control & FW_CFG_DMA_CTL_READ) { | |
375 | read = 1; | |
baf2d5bf MT |
376 | write = 0; |
377 | } else if (dma.control & FW_CFG_DMA_CTL_WRITE) { | |
378 | read = 0; | |
379 | write = 1; | |
a4c0d1de MM |
380 | } else if (dma.control & FW_CFG_DMA_CTL_SKIP) { |
381 | read = 0; | |
baf2d5bf | 382 | write = 0; |
a4c0d1de MM |
383 | } else { |
384 | dma.length = 0; | |
385 | } | |
386 | ||
387 | dma.control = 0; | |
388 | ||
389 | while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) { | |
390 | if (s->cur_entry == FW_CFG_INVALID || !e->data || | |
391 | s->cur_offset >= e->len) { | |
392 | len = dma.length; | |
393 | ||
394 | /* If the access is not a read access, it will be a skip access, | |
395 | * tested before. | |
396 | */ | |
397 | if (read) { | |
398 | if (dma_memory_set(s->dma_as, dma.address, 0, len)) { | |
399 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
400 | } | |
401 | } | |
baf2d5bf MT |
402 | if (write) { |
403 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
404 | } | |
a4c0d1de MM |
405 | } else { |
406 | if (dma.length <= (e->len - s->cur_offset)) { | |
407 | len = dma.length; | |
408 | } else { | |
409 | len = (e->len - s->cur_offset); | |
410 | } | |
411 | ||
a4c0d1de MM |
412 | /* If the access is not a read access, it will be a skip access, |
413 | * tested before. | |
414 | */ | |
415 | if (read) { | |
416 | if (dma_memory_write(s->dma_as, dma.address, | |
417 | &e->data[s->cur_offset], len)) { | |
418 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
419 | } | |
420 | } | |
baf2d5bf MT |
421 | if (write) { |
422 | if (!e->allow_write || | |
423 | len != dma.length || | |
424 | dma_memory_read(s->dma_as, dma.address, | |
425 | &e->data[s->cur_offset], len)) { | |
426 | dma.control |= FW_CFG_DMA_CTL_ERROR; | |
5f9252f7 MAL |
427 | } else if (e->write_cb) { |
428 | e->write_cb(e->callback_opaque, s->cur_offset, len); | |
baf2d5bf MT |
429 | } |
430 | } | |
a4c0d1de MM |
431 | |
432 | s->cur_offset += len; | |
433 | } | |
434 | ||
435 | dma.address += len; | |
436 | dma.length -= len; | |
437 | ||
438 | } | |
439 | ||
440 | stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), | |
441 | dma.control); | |
442 | ||
443 | trace_fw_cfg_read(s, 0); | |
444 | } | |
445 | ||
2cc06a88 KC |
446 | static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr, |
447 | unsigned size) | |
448 | { | |
449 | /* Return a signature value (and handle various read sizes) */ | |
450 | return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8); | |
451 | } | |
452 | ||
a4c0d1de MM |
453 | static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, |
454 | uint64_t value, unsigned size) | |
455 | { | |
456 | FWCfgState *s = opaque; | |
457 | ||
458 | if (size == 4) { | |
459 | if (addr == 0) { | |
460 | /* FWCfgDmaAccess high address */ | |
461 | s->dma_addr = value << 32; | |
462 | } else if (addr == 4) { | |
463 | /* FWCfgDmaAccess low address */ | |
464 | s->dma_addr |= value; | |
465 | fw_cfg_dma_transfer(s); | |
466 | } | |
467 | } else if (size == 8 && addr == 0) { | |
468 | s->dma_addr = value; | |
469 | fw_cfg_dma_transfer(s); | |
470 | } | |
471 | } | |
472 | ||
473 | static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, | |
8372d383 PM |
474 | unsigned size, bool is_write, |
475 | MemTxAttrs attrs) | |
a4c0d1de | 476 | { |
2cc06a88 KC |
477 | return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || |
478 | (size == 8 && addr == 0)); | |
a4c0d1de MM |
479 | } |
480 | ||
cfaadf0e | 481 | static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, |
8372d383 PM |
482 | unsigned size, bool is_write, |
483 | MemTxAttrs attrs) | |
cfaadf0e LE |
484 | { |
485 | return addr == 0; | |
3cce6243 BS |
486 | } |
487 | ||
2247936a LQ |
488 | static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size) |
489 | { | |
490 | return 0; | |
491 | } | |
492 | ||
a8170e5e | 493 | static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, |
561e1827 | 494 | uint64_t value, unsigned size) |
3cce6243 BS |
495 | { |
496 | fw_cfg_select(opaque, (uint16_t)value); | |
497 | } | |
498 | ||
a8170e5e | 499 | static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, |
8372d383 PM |
500 | unsigned size, bool is_write, |
501 | MemTxAttrs attrs) | |
3cce6243 | 502 | { |
561e1827 | 503 | return is_write && size == 2; |
3cce6243 BS |
504 | } |
505 | ||
a8170e5e | 506 | static void fw_cfg_comb_write(void *opaque, hwaddr addr, |
561e1827 | 507 | uint64_t value, unsigned size) |
3cce6243 | 508 | { |
561e1827 AK |
509 | switch (size) { |
510 | case 1: | |
511 | fw_cfg_write(opaque, (uint8_t)value); | |
512 | break; | |
513 | case 2: | |
514 | fw_cfg_select(opaque, (uint16_t)value); | |
515 | break; | |
516 | } | |
3cce6243 BS |
517 | } |
518 | ||
a8170e5e | 519 | static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, |
8372d383 PM |
520 | unsigned size, bool is_write, |
521 | MemTxAttrs attrs) | |
561e1827 AK |
522 | { |
523 | return (size == 1) || (is_write && size == 2); | |
524 | } | |
3cce6243 | 525 | |
561e1827 | 526 | static const MemoryRegionOps fw_cfg_ctl_mem_ops = { |
2247936a | 527 | .read = fw_cfg_ctl_mem_read, |
561e1827 | 528 | .write = fw_cfg_ctl_mem_write, |
d789c845 | 529 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 | 530 | .valid.accepts = fw_cfg_ctl_mem_valid, |
3cce6243 BS |
531 | }; |
532 | ||
561e1827 | 533 | static const MemoryRegionOps fw_cfg_data_mem_ops = { |
38bf2093 | 534 | .read = fw_cfg_data_read, |
561e1827 | 535 | .write = fw_cfg_data_mem_write, |
d789c845 | 536 | .endianness = DEVICE_BIG_ENDIAN, |
561e1827 AK |
537 | .valid = { |
538 | .min_access_size = 1, | |
539 | .max_access_size = 1, | |
cfaadf0e | 540 | .accepts = fw_cfg_data_mem_valid, |
561e1827 | 541 | }, |
3cce6243 BS |
542 | }; |
543 | ||
561e1827 | 544 | static const MemoryRegionOps fw_cfg_comb_mem_ops = { |
6c8d56a2 | 545 | .read = fw_cfg_data_read, |
561e1827 | 546 | .write = fw_cfg_comb_write, |
6fdf98f2 | 547 | .endianness = DEVICE_LITTLE_ENDIAN, |
561e1827 | 548 | .valid.accepts = fw_cfg_comb_valid, |
3cce6243 BS |
549 | }; |
550 | ||
a4c0d1de | 551 | static const MemoryRegionOps fw_cfg_dma_mem_ops = { |
2cc06a88 | 552 | .read = fw_cfg_dma_mem_read, |
a4c0d1de MM |
553 | .write = fw_cfg_dma_mem_write, |
554 | .endianness = DEVICE_BIG_ENDIAN, | |
555 | .valid.accepts = fw_cfg_dma_mem_valid, | |
556 | .valid.max_access_size = 8, | |
557 | .impl.max_access_size = 8, | |
558 | }; | |
559 | ||
3a5c16fc | 560 | static void fw_cfg_reset(DeviceState *d) |
3cce6243 | 561 | { |
2ce92a11 | 562 | FWCfgState *s = FW_CFG(d); |
3cce6243 | 563 | |
3bef7e8a GS |
564 | /* we never register a read callback for FW_CFG_SIGNATURE */ |
565 | fw_cfg_select(s, FW_CFG_SIGNATURE); | |
3cce6243 BS |
566 | } |
567 | ||
ff06108b JQ |
568 | /* Save restore 32 bit int as uint16_t |
569 | This is a Big hack, but it is how the old state did it. | |
570 | Or we broke compatibility in the state, or we can't use struct tm | |
571 | */ | |
572 | ||
2c21ee76 | 573 | static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size, |
03fee66f | 574 | const VMStateField *field) |
ff06108b JQ |
575 | { |
576 | uint32_t *v = pv; | |
577 | *v = qemu_get_be16(f); | |
578 | return 0; | |
579 | } | |
580 | ||
03fee66f MAL |
581 | static int put_unused(QEMUFile *f, void *pv, size_t size, |
582 | const VMStateField *field, QJSON *vmdesc) | |
ff06108b | 583 | { |
66c80e75 | 584 | fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n"); |
ff06108b | 585 | fprintf(stderr, "This functions shouldn't be called.\n"); |
2c21ee76 JD |
586 | |
587 | return 0; | |
ff06108b JQ |
588 | } |
589 | ||
d05ac8fa | 590 | static const VMStateInfo vmstate_hack_uint32_as_uint16 = { |
ff06108b JQ |
591 | .name = "int32_as_uint16", |
592 | .get = get_uint32_as_uint16, | |
593 | .put = put_unused, | |
594 | }; | |
595 | ||
596 | #define VMSTATE_UINT16_HACK(_f, _s, _t) \ | |
597 | VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t) | |
598 | ||
599 | ||
600 | static bool is_version_1(void *opaque, int version_id) | |
601 | { | |
602 | return version_id == 1; | |
603 | } | |
604 | ||
b2a575a1 | 605 | bool fw_cfg_dma_enabled(void *opaque) |
a4c0d1de MM |
606 | { |
607 | FWCfgState *s = opaque; | |
608 | ||
609 | return s->dma_enabled; | |
610 | } | |
611 | ||
612 | static const VMStateDescription vmstate_fw_cfg_dma = { | |
613 | .name = "fw_cfg/dma", | |
614 | .needed = fw_cfg_dma_enabled, | |
615 | .fields = (VMStateField[]) { | |
616 | VMSTATE_UINT64(dma_addr, FWCfgState), | |
617 | VMSTATE_END_OF_LIST() | |
618 | }, | |
619 | }; | |
620 | ||
7d2edd40 JQ |
621 | static const VMStateDescription vmstate_fw_cfg = { |
622 | .name = "fw_cfg", | |
ff06108b | 623 | .version_id = 2, |
7d2edd40 | 624 | .minimum_version_id = 1, |
d49805ae | 625 | .fields = (VMStateField[]) { |
7d2edd40 | 626 | VMSTATE_UINT16(cur_entry, FWCfgState), |
ff06108b JQ |
627 | VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1), |
628 | VMSTATE_UINT32_V(cur_offset, FWCfgState, 2), | |
7d2edd40 | 629 | VMSTATE_END_OF_LIST() |
a4c0d1de MM |
630 | }, |
631 | .subsections = (const VMStateDescription*[]) { | |
632 | &vmstate_fw_cfg_dma, | |
633 | NULL, | |
7d2edd40 JQ |
634 | } |
635 | }; | |
3cce6243 | 636 | |
6f6f4aec MAL |
637 | static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key, |
638 | FWCfgCallback select_cb, | |
5f9252f7 | 639 | FWCfgWriteCallback write_cb, |
6f6f4aec MAL |
640 | void *callback_opaque, |
641 | void *data, size_t len, | |
642 | bool read_only) | |
3cce6243 | 643 | { |
3cce6243 BS |
644 | int arch = !!(key & FW_CFG_ARCH_LOCAL); |
645 | ||
646 | key &= FW_CFG_ENTRY_MASK; | |
647 | ||
e12f3a13 | 648 | assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); |
0f9b2141 | 649 | assert(s->entries[arch][key].data == NULL); /* avoid key conflict */ |
3cce6243 BS |
650 | |
651 | s->entries[arch][key].data = data; | |
089da572 | 652 | s->entries[arch][key].len = (uint32_t)len; |
6f6f4aec | 653 | s->entries[arch][key].select_cb = select_cb; |
5f9252f7 | 654 | s->entries[arch][key].write_cb = write_cb; |
d87072ce | 655 | s->entries[arch][key].callback_opaque = callback_opaque; |
baf2d5bf | 656 | s->entries[arch][key].allow_write = !read_only; |
d87072ce MT |
657 | } |
658 | ||
bdbb5b17 GA |
659 | static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key, |
660 | void *data, size_t len) | |
661 | { | |
662 | void *ptr; | |
663 | int arch = !!(key & FW_CFG_ARCH_LOCAL); | |
664 | ||
665 | key &= FW_CFG_ENTRY_MASK; | |
666 | ||
e12f3a13 | 667 | assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX); |
bdbb5b17 GA |
668 | |
669 | /* return the old data to the function caller, avoid memory leak */ | |
670 | ptr = s->entries[arch][key].data; | |
671 | s->entries[arch][key].data = data; | |
672 | s->entries[arch][key].len = len; | |
673 | s->entries[arch][key].callback_opaque = NULL; | |
baf2d5bf | 674 | s->entries[arch][key].allow_write = false; |
bdbb5b17 GA |
675 | |
676 | return ptr; | |
677 | } | |
678 | ||
d87072ce MT |
679 | void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len) |
680 | { | |
1f80b0d6 | 681 | trace_fw_cfg_add_bytes(key, trace_key_name(key), len); |
5f9252f7 | 682 | fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true); |
3cce6243 BS |
683 | } |
684 | ||
44687f75 MA |
685 | void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value) |
686 | { | |
687 | size_t sz = strlen(value) + 1; | |
688 | ||
1f80b0d6 | 689 | trace_fw_cfg_add_string(key, trace_key_name(key), value); |
e7ae771f | 690 | fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz); |
44687f75 MA |
691 | } |
692 | ||
4cad3867 | 693 | void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value) |
3cce6243 BS |
694 | { |
695 | uint16_t *copy; | |
696 | ||
7267c094 | 697 | copy = g_malloc(sizeof(value)); |
3cce6243 | 698 | *copy = cpu_to_le16(value); |
1f80b0d6 | 699 | trace_fw_cfg_add_i16(key, trace_key_name(key), value); |
089da572 | 700 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
701 | } |
702 | ||
1edd34b6 GS |
703 | void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value) |
704 | { | |
705 | uint16_t *copy, *old; | |
706 | ||
707 | copy = g_malloc(sizeof(value)); | |
708 | *copy = cpu_to_le16(value); | |
709 | old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value)); | |
710 | g_free(old); | |
711 | } | |
712 | ||
4cad3867 | 713 | void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value) |
3cce6243 BS |
714 | { |
715 | uint32_t *copy; | |
716 | ||
7267c094 | 717 | copy = g_malloc(sizeof(value)); |
3cce6243 | 718 | *copy = cpu_to_le32(value); |
1f80b0d6 | 719 | trace_fw_cfg_add_i32(key, trace_key_name(key), value); |
089da572 | 720 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
721 | } |
722 | ||
4cad3867 | 723 | void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value) |
3cce6243 BS |
724 | { |
725 | uint64_t *copy; | |
726 | ||
7267c094 | 727 | copy = g_malloc(sizeof(value)); |
3cce6243 | 728 | *copy = cpu_to_le64(value); |
1f80b0d6 | 729 | trace_fw_cfg_add_i64(key, trace_key_name(key), value); |
089da572 | 730 | fw_cfg_add_bytes(s, key, copy, sizeof(value)); |
3cce6243 BS |
731 | } |
732 | ||
bab47d9a GH |
733 | void fw_cfg_set_order_override(FWCfgState *s, int order) |
734 | { | |
735 | assert(s->fw_cfg_order_override == 0); | |
736 | s->fw_cfg_order_override = order; | |
737 | } | |
738 | ||
739 | void fw_cfg_reset_order_override(FWCfgState *s) | |
740 | { | |
741 | assert(s->fw_cfg_order_override != 0); | |
742 | s->fw_cfg_order_override = 0; | |
743 | } | |
744 | ||
745 | /* | |
746 | * This is the legacy order list. For legacy systems, files are in | |
747 | * the fw_cfg in the order defined below, by the "order" value. Note | |
748 | * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a | |
749 | * specific area, but there may be more than one and they occur in the | |
750 | * order that the user specifies them on the command line. Those are | |
751 | * handled in a special manner, using the order override above. | |
752 | * | |
753 | * For non-legacy, the files are sorted by filename to avoid this kind | |
754 | * of complexity in the future. | |
755 | * | |
756 | * This is only for x86, other arches don't implement versioning so | |
757 | * they won't set legacy mode. | |
758 | */ | |
759 | static struct { | |
760 | const char *name; | |
761 | int order; | |
762 | } fw_cfg_order[] = { | |
763 | { "etc/boot-menu-wait", 10 }, | |
764 | { "bootsplash.jpg", 11 }, | |
765 | { "bootsplash.bmp", 12 }, | |
766 | { "etc/boot-fail-wait", 15 }, | |
767 | { "etc/smbios/smbios-tables", 20 }, | |
768 | { "etc/smbios/smbios-anchor", 30 }, | |
769 | { "etc/e820", 40 }, | |
770 | { "etc/reserved-memory-end", 50 }, | |
771 | { "genroms/kvmvapic.bin", 55 }, | |
772 | { "genroms/linuxboot.bin", 60 }, | |
773 | { }, /* VGA ROMs from pc_vga_init come here, 70. */ | |
774 | { }, /* NIC option ROMs from pc_nic_init come here, 80. */ | |
775 | { "etc/system-states", 90 }, | |
776 | { }, /* User ROMs come here, 100. */ | |
777 | { }, /* Device FW comes here, 110. */ | |
778 | { "etc/extra-pci-roots", 120 }, | |
779 | { "etc/acpi/tables", 130 }, | |
780 | { "etc/table-loader", 140 }, | |
781 | { "etc/tpm/log", 150 }, | |
782 | { "etc/acpi/rsdp", 160 }, | |
783 | { "bootorder", 170 }, | |
784 | ||
785 | #define FW_CFG_ORDER_OVERRIDE_LAST 200 | |
786 | }; | |
787 | ||
788 | static int get_fw_cfg_order(FWCfgState *s, const char *name) | |
789 | { | |
790 | int i; | |
791 | ||
a8d38f3b C |
792 | if (s->fw_cfg_order_override > 0) { |
793 | return s->fw_cfg_order_override; | |
794 | } | |
bab47d9a GH |
795 | |
796 | for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) { | |
a8d38f3b C |
797 | if (fw_cfg_order[i].name == NULL) { |
798 | continue; | |
799 | } | |
800 | ||
801 | if (strcmp(name, fw_cfg_order[i].name) == 0) { | |
802 | return fw_cfg_order[i].order; | |
803 | } | |
bab47d9a | 804 | } |
a8d38f3b | 805 | |
bab47d9a | 806 | /* Stick unknown stuff at the end. */ |
3dc6f869 | 807 | warn_report("Unknown firmware file in legacy mode: %s", name); |
bab47d9a GH |
808 | return FW_CFG_ORDER_OVERRIDE_LAST; |
809 | } | |
810 | ||
d87072ce | 811 | void fw_cfg_add_file_callback(FWCfgState *s, const char *filename, |
6f6f4aec | 812 | FWCfgCallback select_cb, |
5f9252f7 | 813 | FWCfgWriteCallback write_cb, |
6f6f4aec | 814 | void *callback_opaque, |
baf2d5bf | 815 | void *data, size_t len, bool read_only) |
abe147e0 | 816 | { |
bab47d9a | 817 | int i, index, count; |
089da572 | 818 | size_t dsize; |
bab47d9a GH |
819 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
820 | int order = 0; | |
abe147e0 GH |
821 | |
822 | if (!s->files) { | |
e12f3a13 | 823 | dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s); |
7267c094 | 824 | s->files = g_malloc0(dsize); |
089da572 | 825 | fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize); |
abe147e0 GH |
826 | } |
827 | ||
bab47d9a | 828 | count = be32_to_cpu(s->files->count); |
e12f3a13 | 829 | assert(count < fw_cfg_file_slots(s)); |
bab47d9a GH |
830 | |
831 | /* Find the insertion point. */ | |
832 | if (mc->legacy_fw_cfg_order) { | |
833 | /* | |
834 | * Sort by order. For files with the same order, we keep them | |
835 | * in the sequence in which they were added. | |
836 | */ | |
837 | order = get_fw_cfg_order(s, filename); | |
838 | for (index = count; | |
839 | index > 0 && order < s->entry_order[index - 1]; | |
840 | index--); | |
841 | } else { | |
842 | /* Sort by file name. */ | |
843 | for (index = count; | |
844 | index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0; | |
845 | index--); | |
846 | } | |
847 | ||
848 | /* | |
849 | * Move all the entries from the index point and after down one | |
850 | * to create a slot for the new entry. Because calculations are | |
851 | * being done with the index, make it so that "i" is the current | |
852 | * index and "i - 1" is the one being copied from, thus the | |
853 | * unusual start and end in the for statement. | |
854 | */ | |
d6b6abc5 | 855 | for (i = count; i > index; i--) { |
bab47d9a GH |
856 | s->files->f[i] = s->files->f[i - 1]; |
857 | s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i); | |
858 | s->entries[0][FW_CFG_FILE_FIRST + i] = | |
859 | s->entries[0][FW_CFG_FILE_FIRST + i - 1]; | |
860 | s->entry_order[i] = s->entry_order[i - 1]; | |
861 | } | |
862 | ||
863 | memset(&s->files->f[index], 0, sizeof(FWCfgFile)); | |
864 | memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry)); | |
abe147e0 | 865 | |
bab47d9a GH |
866 | pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename); |
867 | for (i = 0; i <= count; i++) { | |
868 | if (i != index && | |
869 | strcmp(s->files->f[index].name, s->files->f[i].name) == 0) { | |
0eb973f9 GS |
870 | error_report("duplicate fw_cfg file name: %s", |
871 | s->files->f[index].name); | |
872 | exit(1); | |
de9352bc | 873 | } |
abe147e0 | 874 | } |
de9352bc | 875 | |
6f6f4aec | 876 | fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index, |
5f9252f7 | 877 | select_cb, write_cb, |
6f6f4aec MAL |
878 | callback_opaque, data, len, |
879 | read_only); | |
0eb973f9 | 880 | |
abe147e0 GH |
881 | s->files->f[index].size = cpu_to_be32(len); |
882 | s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index); | |
bab47d9a | 883 | s->entry_order[index] = order; |
f6e35343 | 884 | trace_fw_cfg_add_file(s, index, s->files->f[index].name, len); |
abe147e0 | 885 | |
bab47d9a | 886 | s->files->count = cpu_to_be32(count+1); |
abe147e0 GH |
887 | } |
888 | ||
d87072ce MT |
889 | void fw_cfg_add_file(FWCfgState *s, const char *filename, |
890 | void *data, size_t len) | |
891 | { | |
5f9252f7 | 892 | fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); |
d87072ce MT |
893 | } |
894 | ||
bdbb5b17 GA |
895 | void *fw_cfg_modify_file(FWCfgState *s, const char *filename, |
896 | void *data, size_t len) | |
897 | { | |
898 | int i, index; | |
f3b37668 | 899 | void *ptr = NULL; |
bdbb5b17 GA |
900 | |
901 | assert(s->files); | |
902 | ||
903 | index = be32_to_cpu(s->files->count); | |
bdbb5b17 GA |
904 | |
905 | for (i = 0; i < index; i++) { | |
906 | if (strcmp(filename, s->files->f[i].name) == 0) { | |
f3b37668 GA |
907 | ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i, |
908 | data, len); | |
909 | s->files->f[i].size = cpu_to_be32(len); | |
910 | return ptr; | |
bdbb5b17 GA |
911 | } |
912 | } | |
d6b6abc5 MA |
913 | |
914 | assert(index < fw_cfg_file_slots(s)); | |
915 | ||
bdbb5b17 | 916 | /* add new one */ |
5f9252f7 | 917 | fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true); |
bdbb5b17 GA |
918 | return NULL; |
919 | } | |
920 | ||
921 | static void fw_cfg_machine_reset(void *opaque) | |
962630f2 | 922 | { |
bdbb5b17 | 923 | void *ptr; |
0e7a7592 | 924 | size_t len; |
bdbb5b17 | 925 | FWCfgState *s = opaque; |
907aac2f | 926 | char *bootindex = get_boot_devices_list(&len); |
962630f2 | 927 | |
bdbb5b17 GA |
928 | ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len); |
929 | g_free(ptr); | |
930 | } | |
931 | ||
932 | static void fw_cfg_machine_ready(struct Notifier *n, void *data) | |
933 | { | |
934 | FWCfgState *s = container_of(n, FWCfgState, machine_ready); | |
935 | qemu_register_reset(fw_cfg_machine_reset, s); | |
962630f2 GN |
936 | } |
937 | ||
3cce6243 | 938 | |
3a5c16fc | 939 | |
38f3adc3 | 940 | static void fw_cfg_common_realize(DeviceState *dev, Error **errp) |
5712db6a LE |
941 | { |
942 | FWCfgState *s = FW_CFG(dev); | |
cfc58cf3 | 943 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c1aa733 | 944 | uint32_t version = FW_CFG_VERSION; |
3cce6243 | 945 | |
38f3adc3 MCA |
946 | if (!fw_cfg_find()) { |
947 | error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG); | |
948 | return; | |
949 | } | |
10a584b2 | 950 | |
089da572 | 951 | fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4); |
9c5ce8db | 952 | fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16); |
cfc58cf3 | 953 | fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics); |
95387491 | 954 | fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); |
3d3b8303 | 955 | fw_cfg_bootsplash(s); |
ac05f349 | 956 | fw_cfg_reboot(s); |
962630f2 | 957 | |
3c1aa733 MCA |
958 | if (s->dma_enabled) { |
959 | version |= FW_CFG_VERSION_DMA; | |
960 | } | |
961 | ||
962 | fw_cfg_add_i32(s, FW_CFG_ID, version); | |
963 | ||
962630f2 GN |
964 | s->machine_ready.notify = fw_cfg_machine_ready; |
965 | qemu_add_machine_init_done_notifier(&s->machine_ready); | |
3cce6243 | 966 | } |
3a5c16fc | 967 | |
a4c0d1de MM |
968 | FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, |
969 | AddressSpace *dma_as) | |
3a5c16fc | 970 | { |
5712db6a | 971 | DeviceState *dev; |
91685323 MCA |
972 | SysBusDevice *sbd; |
973 | FWCfgIoState *ios; | |
a4c0d1de | 974 | FWCfgState *s; |
e6915b5f | 975 | bool dma_requested = dma_iobase && dma_as; |
3a5c16fc | 976 | |
5712db6a | 977 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
e6915b5f LE |
978 | if (!dma_requested) { |
979 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
980 | } | |
a4c0d1de | 981 | |
38f3adc3 MCA |
982 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
983 | OBJECT(dev), NULL); | |
984 | qdev_init_nofail(dev); | |
91685323 MCA |
985 | |
986 | sbd = SYS_BUS_DEVICE(dev); | |
987 | ios = FW_CFG_IO(dev); | |
988 | sysbus_add_io(sbd, iobase, &ios->comb_iomem); | |
989 | ||
a4c0d1de MM |
990 | s = FW_CFG(dev); |
991 | ||
e6915b5f | 992 | if (s->dma_enabled) { |
a4c0d1de MM |
993 | /* 64 bits for the address field */ |
994 | s->dma_as = dma_as; | |
995 | s->dma_addr = 0; | |
91685323 | 996 | sysbus_add_io(sbd, dma_iobase, &s->dma_iomem); |
a4c0d1de MM |
997 | } |
998 | ||
a4c0d1de MM |
999 | return s; |
1000 | } | |
1001 | ||
1002 | FWCfgState *fw_cfg_init_io(uint32_t iobase) | |
1003 | { | |
1004 | return fw_cfg_init_io_dma(iobase, 0, NULL); | |
56383955 HT |
1005 | } |
1006 | ||
a4c0d1de MM |
1007 | FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, |
1008 | hwaddr data_addr, uint32_t data_width, | |
1009 | hwaddr dma_addr, AddressSpace *dma_as) | |
56383955 | 1010 | { |
5712db6a LE |
1011 | DeviceState *dev; |
1012 | SysBusDevice *sbd; | |
a4c0d1de | 1013 | FWCfgState *s; |
e6915b5f | 1014 | bool dma_requested = dma_addr && dma_as; |
56383955 | 1015 | |
5712db6a | 1016 | dev = qdev_create(NULL, TYPE_FW_CFG_MEM); |
6c87e3d5 | 1017 | qdev_prop_set_uint32(dev, "data_width", data_width); |
e6915b5f LE |
1018 | if (!dma_requested) { |
1019 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1020 | } | |
cfaadf0e | 1021 | |
38f3adc3 MCA |
1022 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
1023 | OBJECT(dev), NULL); | |
1024 | qdev_init_nofail(dev); | |
5712db6a LE |
1025 | |
1026 | sbd = SYS_BUS_DEVICE(dev); | |
1027 | sysbus_mmio_map(sbd, 0, ctl_addr); | |
1028 | sysbus_mmio_map(sbd, 1, data_addr); | |
1029 | ||
a4c0d1de MM |
1030 | s = FW_CFG(dev); |
1031 | ||
e6915b5f | 1032 | if (s->dma_enabled) { |
a4c0d1de MM |
1033 | s->dma_as = dma_as; |
1034 | s->dma_addr = 0; | |
1035 | sysbus_mmio_map(sbd, 2, dma_addr); | |
a4c0d1de MM |
1036 | } |
1037 | ||
a4c0d1de | 1038 | return s; |
5712db6a LE |
1039 | } |
1040 | ||
6c87e3d5 LE |
1041 | FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr) |
1042 | { | |
1043 | return fw_cfg_init_mem_wide(ctl_addr, data_addr, | |
a4c0d1de MM |
1044 | fw_cfg_data_mem_ops.valid.max_access_size, |
1045 | 0, NULL); | |
6c87e3d5 LE |
1046 | } |
1047 | ||
5712db6a | 1048 | |
600c60b7 MT |
1049 | FWCfgState *fw_cfg_find(void) |
1050 | { | |
6e99c075 MCA |
1051 | /* Returns NULL unless there is exactly one fw_cfg device */ |
1052 | return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL)); | |
600c60b7 MT |
1053 | } |
1054 | ||
38f3adc3 | 1055 | |
999e12bb AL |
1056 | static void fw_cfg_class_init(ObjectClass *klass, void *data) |
1057 | { | |
39bffca2 | 1058 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1059 | |
39bffca2 AL |
1060 | dc->reset = fw_cfg_reset; |
1061 | dc->vmsd = &vmstate_fw_cfg; | |
999e12bb AL |
1062 | } |
1063 | ||
8c43a6f0 | 1064 | static const TypeInfo fw_cfg_info = { |
600c60b7 | 1065 | .name = TYPE_FW_CFG, |
39bffca2 | 1066 | .parent = TYPE_SYS_BUS_DEVICE, |
e061fa3c | 1067 | .abstract = true, |
39bffca2 AL |
1068 | .instance_size = sizeof(FWCfgState), |
1069 | .class_init = fw_cfg_class_init, | |
3a5c16fc BS |
1070 | }; |
1071 | ||
e12f3a13 LE |
1072 | static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp) |
1073 | { | |
1074 | uint16_t file_slots_max; | |
1075 | ||
1076 | if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) { | |
1077 | error_setg(errp, "\"file_slots\" must be at least 0x%x", | |
1078 | FW_CFG_FILE_SLOTS_MIN); | |
1079 | return; | |
1080 | } | |
1081 | ||
1082 | /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value | |
1083 | * that we permit. The actual (exclusive) value coming from the | |
1084 | * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */ | |
1085 | file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1; | |
1086 | if (fw_cfg_file_slots(s) > file_slots_max) { | |
1087 | error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16, | |
1088 | file_slots_max); | |
1089 | return; | |
1090 | } | |
1091 | ||
1092 | s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); | |
1093 | s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s)); | |
1094 | s->entry_order = g_new0(int, fw_cfg_max_entry(s)); | |
1095 | } | |
5712db6a LE |
1096 | |
1097 | static Property fw_cfg_io_properties[] = { | |
a4c0d1de | 1098 | DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, |
e6915b5f | 1099 | true), |
e12f3a13 | 1100 | DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, |
a5b3ebfd | 1101 | FW_CFG_FILE_SLOTS_DFLT), |
5712db6a LE |
1102 | DEFINE_PROP_END_OF_LIST(), |
1103 | }; | |
1104 | ||
1105 | static void fw_cfg_io_realize(DeviceState *dev, Error **errp) | |
1106 | { | |
1107 | FWCfgIoState *s = FW_CFG_IO(dev); | |
e12f3a13 LE |
1108 | Error *local_err = NULL; |
1109 | ||
1110 | fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); | |
1111 | if (local_err) { | |
1112 | error_propagate(errp, local_err); | |
1113 | return; | |
1114 | } | |
5712db6a | 1115 | |
ce9a2aa3 GS |
1116 | /* when using port i/o, the 8-bit data register ALWAYS overlaps |
1117 | * with half of the 16-bit control register. Hence, the total size | |
1118 | * of the i/o region used is FW_CFG_CTL_SIZE */ | |
5712db6a | 1119 | memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops, |
a4c0d1de | 1120 | FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE); |
a4c0d1de MM |
1121 | |
1122 | if (FW_CFG(s)->dma_enabled) { | |
1123 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
1124 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
1125 | sizeof(dma_addr_t)); | |
a4c0d1de | 1126 | } |
38f3adc3 MCA |
1127 | |
1128 | fw_cfg_common_realize(dev, errp); | |
5712db6a LE |
1129 | } |
1130 | ||
1131 | static void fw_cfg_io_class_init(ObjectClass *klass, void *data) | |
1132 | { | |
1133 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1134 | ||
1135 | dc->realize = fw_cfg_io_realize; | |
1136 | dc->props = fw_cfg_io_properties; | |
1137 | } | |
1138 | ||
1139 | static const TypeInfo fw_cfg_io_info = { | |
1140 | .name = TYPE_FW_CFG_IO, | |
1141 | .parent = TYPE_FW_CFG, | |
1142 | .instance_size = sizeof(FWCfgIoState), | |
1143 | .class_init = fw_cfg_io_class_init, | |
1144 | }; | |
1145 | ||
1146 | ||
cfaadf0e LE |
1147 | static Property fw_cfg_mem_properties[] = { |
1148 | DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), | |
a4c0d1de | 1149 | DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, |
e6915b5f | 1150 | true), |
e12f3a13 | 1151 | DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, |
a5b3ebfd | 1152 | FW_CFG_FILE_SLOTS_DFLT), |
cfaadf0e LE |
1153 | DEFINE_PROP_END_OF_LIST(), |
1154 | }; | |
1155 | ||
5712db6a LE |
1156 | static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) |
1157 | { | |
1158 | FWCfgMemState *s = FW_CFG_MEM(dev); | |
1159 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
cfaadf0e | 1160 | const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops; |
e12f3a13 LE |
1161 | Error *local_err = NULL; |
1162 | ||
1163 | fw_cfg_file_slots_allocate(FW_CFG(s), &local_err); | |
1164 | if (local_err) { | |
1165 | error_propagate(errp, local_err); | |
1166 | return; | |
1167 | } | |
5712db6a LE |
1168 | |
1169 | memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops, | |
a4c0d1de | 1170 | FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE); |
5712db6a LE |
1171 | sysbus_init_mmio(sbd, &s->ctl_iomem); |
1172 | ||
cfaadf0e | 1173 | if (s->data_width > data_ops->valid.max_access_size) { |
695e2fc2 | 1174 | s->wide_data_ops = *data_ops; |
cfaadf0e LE |
1175 | |
1176 | s->wide_data_ops.valid.max_access_size = s->data_width; | |
1177 | s->wide_data_ops.impl.max_access_size = s->data_width; | |
1178 | data_ops = &s->wide_data_ops; | |
1179 | } | |
1180 | memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s), | |
1181 | "fwcfg.data", data_ops->valid.max_access_size); | |
5712db6a | 1182 | sysbus_init_mmio(sbd, &s->data_iomem); |
a4c0d1de MM |
1183 | |
1184 | if (FW_CFG(s)->dma_enabled) { | |
1185 | memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s), | |
1186 | &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma", | |
1187 | sizeof(dma_addr_t)); | |
1188 | sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem); | |
1189 | } | |
38f3adc3 MCA |
1190 | |
1191 | fw_cfg_common_realize(dev, errp); | |
5712db6a LE |
1192 | } |
1193 | ||
1194 | static void fw_cfg_mem_class_init(ObjectClass *klass, void *data) | |
1195 | { | |
1196 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1197 | ||
1198 | dc->realize = fw_cfg_mem_realize; | |
cfaadf0e | 1199 | dc->props = fw_cfg_mem_properties; |
5712db6a LE |
1200 | } |
1201 | ||
1202 | static const TypeInfo fw_cfg_mem_info = { | |
1203 | .name = TYPE_FW_CFG_MEM, | |
1204 | .parent = TYPE_FW_CFG, | |
1205 | .instance_size = sizeof(FWCfgMemState), | |
1206 | .class_init = fw_cfg_mem_class_init, | |
1207 | }; | |
1208 | ||
1209 | ||
83f7d43a | 1210 | static void fw_cfg_register_types(void) |
3a5c16fc | 1211 | { |
39bffca2 | 1212 | type_register_static(&fw_cfg_info); |
5712db6a LE |
1213 | type_register_static(&fw_cfg_io_info); |
1214 | type_register_static(&fw_cfg_mem_info); | |
3a5c16fc BS |
1215 | } |
1216 | ||
83f7d43a | 1217 | type_init(fw_cfg_register_types) |