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Commit | Line | Data |
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502a5395 | 1 | /* |
cd3fdb7f | 2 | * QEMU i440FX PCI Bridge Emulation |
502a5395 PB |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
b6a0aa05 | 25 | #include "qemu/osdep.h" |
51eae1e7 | 26 | #include "qemu/units.h" |
9a571161 | 27 | #include "qemu/range.h" |
0d09e41a | 28 | #include "hw/i386/pc.h" |
83c9f4ca PB |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_host.h" | |
0fd61a2d | 31 | #include "hw/pci-host/i440fx.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
da34e65c | 34 | #include "qapi/error.h" |
d6454270 | 35 | #include "migration/vmstate.h" |
39848901 | 36 | #include "qapi/visitor.h" |
8d211f62 | 37 | #include "qemu/error-report.h" |
87ecb68b | 38 | |
56594fe3 IY |
39 | /* |
40 | * I440FX chipset data sheet. | |
9b178f0e | 41 | * https://wiki.qemu.org/File:29054901.pdf |
56594fe3 IY |
42 | */ |
43 | ||
1d0d4aa4 IM |
44 | #define I440FX_PCI_HOST_BRIDGE(obj) \ |
45 | OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE) | |
46 | ||
67c332fd AF |
47 | typedef struct I440FXState { |
48 | PCIHostState parent_obj; | |
01c9742d | 49 | Range pci_hole; |
39848901 | 50 | uint64_t pci_hole64_size; |
9fa99d25 | 51 | bool pci_hole64_fix; |
04c7d8b8 | 52 | uint32_t short_root_bus; |
67c332fd | 53 | } I440FXState; |
502a5395 | 54 | |
f2c688bb IY |
55 | #define I440FX_PAM 0x59 |
56 | #define I440FX_PAM_SIZE 7 | |
57 | #define I440FX_SMRAM 0x72 | |
58 | ||
9fa99d25 MA |
59 | /* Keep it 2G to comply with older win32 guests */ |
60 | #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) | |
61 | ||
e33d22fa EH |
62 | /* Older coreboot versions (4.0 and older) read a config register that doesn't |
63 | * exist in real hardware, to get the RAM size from QEMU. | |
64 | */ | |
65 | #define I440FX_COREBOOT_RAM_SIZE 0x57 | |
66 | ||
0a3bacf3 | 67 | static void i440fx_update_memory_mappings(PCII440FXState *d) |
ee0ea1d0 | 68 | { |
410edd92 | 69 | int i; |
2aedfa46 | 70 | PCIDevice *pd = PCI_DEVICE(d); |
84631fd7 | 71 | |
72124c01 | 72 | memory_region_transaction_begin(); |
0118c01c | 73 | for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { |
410edd92 | 74 | pam_update(&d->pam_regions[i], i, |
66175626 | 75 | pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); |
ee0ea1d0 | 76 | } |
3de70c08 PB |
77 | memory_region_set_enabled(&d->smram_region, |
78 | !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); | |
fe6567d5 PB |
79 | memory_region_set_enabled(&d->smram, |
80 | pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); | |
72124c01 | 81 | memory_region_transaction_commit(); |
ee0ea1d0 FB |
82 | } |
83 | ||
ee0ea1d0 | 84 | |
0a3bacf3 | 85 | static void i440fx_write_config(PCIDevice *dev, |
ee0ea1d0 FB |
86 | uint32_t address, uint32_t val, int len) |
87 | { | |
57a0f0c6 | 88 | PCII440FXState *d = I440FX_PCI_DEVICE(dev); |
0a3bacf3 | 89 | |
ee0ea1d0 | 90 | /* XXX: implement SMRAM.D_LOCK */ |
0a3bacf3 | 91 | pci_default_write_config(dev, address, val, len); |
4da5fcd3 IY |
92 | if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || |
93 | range_covers_byte(address, len, I440FX_SMRAM)) { | |
ee0ea1d0 | 94 | i440fx_update_memory_mappings(d); |
4da5fcd3 | 95 | } |
ee0ea1d0 FB |
96 | } |
97 | ||
e59fb374 | 98 | static int i440fx_post_load(void *opaque, int version_id) |
0c7d19e5 JQ |
99 | { |
100 | PCII440FXState *d = opaque; | |
101 | ||
102 | i440fx_update_memory_mappings(d); | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static const VMStateDescription vmstate_i440fx = { | |
107 | .name = "I440FX", | |
108 | .version_id = 3, | |
109 | .minimum_version_id = 3, | |
752ff2fa | 110 | .post_load = i440fx_post_load, |
d49805ae | 111 | .fields = (VMStateField[]) { |
2aedfa46 | 112 | VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), |
f809c605 PB |
113 | /* Used to be smm_enabled, which was basically always zero because |
114 | * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. | |
115 | */ | |
116 | VMSTATE_UNUSED(1), | |
0c7d19e5 JQ |
117 | VMSTATE_END_OF_LIST() |
118 | } | |
119 | }; | |
120 | ||
39848901 | 121 | static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, |
d7bce999 | 122 | const char *name, void *opaque, |
39848901 IM |
123 | Error **errp) |
124 | { | |
125 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
a0efbf16 MA |
126 | uint64_t val64; |
127 | uint32_t value; | |
39848901 | 128 | |
a0efbf16 MA |
129 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); |
130 | value = val64; | |
131 | assert(value == val64); | |
51e72bc1 | 132 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
133 | } |
134 | ||
135 | static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, | |
d7bce999 | 136 | const char *name, void *opaque, |
39848901 IM |
137 | Error **errp) |
138 | { | |
139 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); | |
a0efbf16 MA |
140 | uint64_t val64; |
141 | uint32_t value; | |
39848901 | 142 | |
a0efbf16 MA |
143 | val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; |
144 | value = val64; | |
145 | assert(value == val64); | |
51e72bc1 | 146 | visit_type_uint32(v, name, &value, errp); |
39848901 IM |
147 | } |
148 | ||
9fa99d25 MA |
149 | /* |
150 | * The 64bit PCI hole start is set by the Guest firmware | |
151 | * as the address of the first 64bit PCI MEM resource. | |
152 | * If no PCI device has resources on the 64bit area, | |
153 | * the 64bit PCI hole will start after "over 4G RAM" and the | |
154 | * reserved space for memory hotplug if any. | |
155 | */ | |
ccef5b1f | 156 | static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) |
39848901 | 157 | { |
2028fdf3 | 158 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
9fa99d25 | 159 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
2028fdf3 | 160 | Range w64; |
a0efbf16 | 161 | uint64_t value; |
2028fdf3 MT |
162 | |
163 | pci_bus_get_w64_range(h->bus, &w64); | |
a0efbf16 | 164 | value = range_is_empty(&w64) ? 0 : range_lob(&w64); |
9fa99d25 MA |
165 | if (!value && s->pci_hole64_fix) { |
166 | value = pc_pci_hole64_start(); | |
167 | } | |
ccef5b1f LE |
168 | return value; |
169 | } | |
170 | ||
171 | static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, | |
172 | const char *name, | |
173 | void *opaque, Error **errp) | |
174 | { | |
175 | uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); | |
176 | ||
177 | visit_type_uint64(v, name, &hole64_start, errp); | |
39848901 IM |
178 | } |
179 | ||
9fa99d25 MA |
180 | /* |
181 | * The 64bit PCI hole end is set by the Guest firmware | |
182 | * as the address of the last 64bit PCI MEM resource. | |
183 | * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE | |
184 | * that can be configured by the user. | |
185 | */ | |
39848901 | 186 | static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, |
d7bce999 | 187 | const char *name, void *opaque, |
39848901 IM |
188 | Error **errp) |
189 | { | |
2028fdf3 | 190 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
9fa99d25 | 191 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); |
ed6bb4b5 | 192 | uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); |
2028fdf3 | 193 | Range w64; |
9fa99d25 | 194 | uint64_t value, hole64_end; |
2028fdf3 MT |
195 | |
196 | pci_bus_get_w64_range(h->bus, &w64); | |
a0efbf16 | 197 | value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; |
9fa99d25 MA |
198 | hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); |
199 | if (s->pci_hole64_fix && value < hole64_end) { | |
200 | value = hole64_end; | |
201 | } | |
a0efbf16 | 202 | visit_type_uint64(v, name, &value, errp); |
39848901 IM |
203 | } |
204 | ||
a3560fbf | 205 | static void i440fx_pcihost_initfn(Object *obj) |
502a5395 | 206 | { |
a3560fbf | 207 | PCIHostState *s = PCI_HOST_BRIDGE(obj); |
502a5395 | 208 | |
a3560fbf | 209 | memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, |
d0ed8076 | 210 | "pci-conf-idx", 4); |
a3560fbf | 211 | memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, |
d0ed8076 | 212 | "pci-conf-data", 4); |
39848901 | 213 | |
1e507bb0 | 214 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", |
39848901 | 215 | i440fx_pcihost_get_pci_hole_start, |
d2623129 | 216 | NULL, NULL, NULL); |
39848901 | 217 | |
1e507bb0 | 218 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", |
39848901 | 219 | i440fx_pcihost_get_pci_hole_end, |
d2623129 | 220 | NULL, NULL, NULL); |
39848901 | 221 | |
1e507bb0 | 222 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", |
39848901 | 223 | i440fx_pcihost_get_pci_hole64_start, |
d2623129 | 224 | NULL, NULL, NULL); |
39848901 | 225 | |
1e507bb0 | 226 | object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", |
39848901 | 227 | i440fx_pcihost_get_pci_hole64_end, |
d2623129 | 228 | NULL, NULL, NULL); |
a3560fbf | 229 | } |
502a5395 | 230 | |
a3560fbf HT |
231 | static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) |
232 | { | |
233 | PCIHostState *s = PCI_HOST_BRIDGE(dev); | |
234 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
235 | ||
236 | sysbus_add_io(sbd, 0xcf8, &s->conf_mem); | |
237 | sysbus_init_ioports(sbd, 0xcf8, 4); | |
238 | ||
239 | sysbus_add_io(sbd, 0xcfc, &s->data_mem); | |
240 | sysbus_init_ioports(sbd, 0xcfc, 4); | |
37abf8d2 PH |
241 | |
242 | /* register i440fx 0xcf8 port as coalesced pio */ | |
243 | memory_region_set_flush_coalesced(&s->data_mem); | |
244 | memory_region_add_coalescing(&s->conf_mem, 0, 4); | |
8a14daa5 | 245 | } |
502a5395 | 246 | |
9af21dbe | 247 | static void i440fx_realize(PCIDevice *dev, Error **errp) |
8a14daa5 | 248 | { |
2aedfa46 | 249 | dev->config[I440FX_SMRAM] = 0x02; |
8d211f62 BD |
250 | |
251 | if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { | |
3dc6f869 | 252 | warn_report("i440fx doesn't support emulated iommu"); |
8d211f62 | 253 | } |
8a14daa5 GH |
254 | } |
255 | ||
7bb836e4 MT |
256 | PCIBus *i440fx_init(const char *host_type, const char *pci_type, |
257 | PCII440FXState **pi440fx_state, | |
44fc8c5e IM |
258 | MemoryRegion *address_space_mem, |
259 | MemoryRegion *address_space_io, | |
260 | ram_addr_t ram_size, | |
ddaaefb4 | 261 | ram_addr_t below_4g_mem_size, |
39848901 | 262 | ram_addr_t above_4g_mem_size, |
44fc8c5e IM |
263 | MemoryRegion *pci_address_space, |
264 | MemoryRegion *ram_memory) | |
8a14daa5 GH |
265 | { |
266 | DeviceState *dev; | |
267 | PCIBus *b; | |
268 | PCIDevice *d; | |
8558d942 | 269 | PCIHostState *s; |
ae0a5466 | 270 | PCII440FXState *f; |
2725aec7 | 271 | unsigned i; |
39848901 | 272 | I440FXState *i440fx; |
8a14daa5 | 273 | |
3e80f690 | 274 | dev = qdev_new(host_type); |
8558d942 | 275 | s = PCI_HOST_BRIDGE(dev); |
1115ff6d DG |
276 | b = pci_root_bus_new(dev, NULL, pci_address_space, |
277 | address_space_io, 0, TYPE_PCI_BUS); | |
8a14daa5 | 278 | s->bus = b; |
d2623129 | 279 | object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); |
3e80f690 | 280 | qdev_realize_and_unref(dev, NULL, &error_fatal); |
8a14daa5 | 281 | |
7bb836e4 | 282 | d = pci_create_simple(b, 0, pci_type); |
57a0f0c6 | 283 | *pi440fx_state = I440FX_PCI_DEVICE(d); |
ae0a5466 AK |
284 | f = *pi440fx_state; |
285 | f->system_memory = address_space_mem; | |
286 | f->pci_address_space = pci_address_space; | |
287 | f->ram_memory = ram_memory; | |
39848901 IM |
288 | |
289 | i440fx = I440FX_PCI_HOST_BRIDGE(dev); | |
a0efbf16 MA |
290 | range_set_bounds(&i440fx->pci_hole, below_4g_mem_size, |
291 | IO_APIC_DEFAULT_ADDRESS - 1); | |
39848901 | 292 | |
83d08f26 MT |
293 | /* setup pci memory mapping */ |
294 | pc_pci_as_mapping_init(OBJECT(f), f->system_memory, | |
295 | f->pci_address_space); | |
296 | ||
fe6567d5 | 297 | /* if *disabled* show SMRAM to all CPUs */ |
40c5dce9 | 298 | memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", |
ae0a5466 | 299 | f->pci_address_space, 0xa0000, 0x20000); |
b41e1ed4 AK |
300 | memory_region_add_subregion_overlap(f->system_memory, 0xa0000, |
301 | &f->smram_region, 1); | |
fe6567d5 PB |
302 | memory_region_set_enabled(&f->smram_region, true); |
303 | ||
304 | /* smram, as seen by SMM CPUs */ | |
51eae1e7 | 305 | memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); |
fe6567d5 PB |
306 | memory_region_set_enabled(&f->smram, true); |
307 | memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", | |
f809c605 | 308 | f->ram_memory, 0xa0000, 0x20000); |
fe6567d5 PB |
309 | memory_region_set_enabled(&f->low_smram, true); |
310 | memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram); | |
311 | object_property_add_const_link(qdev_get_machine(), "smram", | |
d2623129 | 312 | OBJECT(&f->smram)); |
fe6567d5 | 313 | |
3cd2cf43 | 314 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 | 315 | &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); |
0118c01c | 316 | for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { |
3cd2cf43 | 317 | init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space, |
410edd92 IY |
318 | &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, |
319 | PAM_EXPAN_SIZE); | |
2725aec7 | 320 | } |
8a14daa5 | 321 | |
ec5f92ce | 322 | ram_size = ram_size / 8 / 1024 / 1024; |
2aedfa46 | 323 | if (ram_size > 255) { |
ec5f92ce | 324 | ram_size = 255; |
2aedfa46 | 325 | } |
e33d22fa | 326 | d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; |
ec5f92ce | 327 | |
ae0a5466 AK |
328 | i440fx_update_memory_mappings(f); |
329 | ||
502a5395 PB |
330 | return b; |
331 | } | |
332 | ||
277e9340 MT |
333 | PCIBus *find_i440fx(void) |
334 | { | |
335 | PCIHostState *s = OBJECT_CHECK(PCIHostState, | |
336 | object_resolve_path("/machine/i440fx", NULL), | |
337 | TYPE_PCI_HOST_BRIDGE); | |
338 | return s ? s->bus : NULL; | |
339 | } | |
340 | ||
40021f08 AL |
341 | static void i440fx_class_init(ObjectClass *klass, void *data) |
342 | { | |
39bffca2 | 343 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
344 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
345 | ||
9af21dbe | 346 | k->realize = i440fx_realize; |
40021f08 AL |
347 | k->config_write = i440fx_write_config; |
348 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
349 | k->device_id = PCI_DEVICE_ID_INTEL_82441; | |
350 | k->revision = 0x02; | |
351 | k->class_id = PCI_CLASS_BRIDGE_HOST; | |
39bffca2 | 352 | dc->desc = "Host bridge"; |
39bffca2 | 353 | dc->vmsd = &vmstate_i440fx; |
08c58f92 MA |
354 | /* |
355 | * PCI-facing part of the host bridge, not usable without the | |
356 | * host-facing part, which can't be device_add'ed, yet. | |
357 | */ | |
e90f2a8c | 358 | dc->user_creatable = false; |
2897ae02 | 359 | dc->hotpluggable = false; |
40021f08 AL |
360 | } |
361 | ||
4240abff | 362 | static const TypeInfo i440fx_info = { |
57a0f0c6 | 363 | .name = TYPE_I440FX_PCI_DEVICE, |
39bffca2 AL |
364 | .parent = TYPE_PCI_DEVICE, |
365 | .instance_size = sizeof(PCII440FXState), | |
366 | .class_init = i440fx_class_init, | |
fd3b02c8 EH |
367 | .interfaces = (InterfaceInfo[]) { |
368 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
369 | { }, | |
370 | }, | |
8a14daa5 GH |
371 | }; |
372 | ||
568f0690 DG |
373 | static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, |
374 | PCIBus *rootbus) | |
375 | { | |
04c7d8b8 CR |
376 | I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge); |
377 | ||
568f0690 | 378 | /* For backwards compat with old device paths */ |
04c7d8b8 CR |
379 | if (s->short_root_bus) { |
380 | return "0000"; | |
381 | } | |
382 | return "0000:00"; | |
568f0690 DG |
383 | } |
384 | ||
39848901 IM |
385 | static Property i440fx_props[] = { |
386 | DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, | |
9fa99d25 | 387 | pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), |
04c7d8b8 | 388 | DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), |
9fa99d25 | 389 | DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), |
39848901 IM |
390 | DEFINE_PROP_END_OF_LIST(), |
391 | }; | |
392 | ||
999e12bb AL |
393 | static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
394 | { | |
39bffca2 | 395 | DeviceClass *dc = DEVICE_CLASS(klass); |
568f0690 | 396 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); |
999e12bb | 397 | |
568f0690 | 398 | hc->root_bus_path = i440fx_pcihost_root_bus_path; |
a3560fbf | 399 | dc->realize = i440fx_pcihost_realize; |
39bffca2 | 400 | dc->fw_name = "pci"; |
4f67d30b | 401 | device_class_set_props(dc, i440fx_props); |
bf8d4924 | 402 | /* Reason: needs to be wired up by pc_init1 */ |
e90f2a8c | 403 | dc->user_creatable = false; |
999e12bb AL |
404 | } |
405 | ||
4240abff | 406 | static const TypeInfo i440fx_pcihost_info = { |
1d0d4aa4 | 407 | .name = TYPE_I440FX_PCI_HOST_BRIDGE, |
8558d942 | 408 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 | 409 | .instance_size = sizeof(I440FXState), |
a3560fbf | 410 | .instance_init = i440fx_pcihost_initfn, |
39bffca2 | 411 | .class_init = i440fx_pcihost_class_init, |
8a14daa5 GH |
412 | }; |
413 | ||
83f7d43a | 414 | static void i440fx_register_types(void) |
8a14daa5 | 415 | { |
39bffca2 | 416 | type_register_static(&i440fx_info); |
39bffca2 | 417 | type_register_static(&i440fx_pcihost_info); |
8a14daa5 | 418 | } |
83f7d43a AF |
419 | |
420 | type_init(i440fx_register_types) |