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Commit | Line | Data |
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74c62ba8 AJ |
1 | /* |
2 | * QEMU PowerPC E500 embedded processors pci controller emulation | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc4xx_pci.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
97d5408f | 17 | #include "qemu/osdep.h" |
64552b6b | 18 | #include "hw/irq.h" |
3eddc1be | 19 | #include "hw/ppc/e500-ccsr.h" |
a27bd6c7 | 20 | #include "hw/qdev-properties.h" |
d6454270 | 21 | #include "migration/vmstate.h" |
83c9f4ca PB |
22 | #include "hw/pci/pci.h" |
23 | #include "hw/pci/pci_host.h" | |
1de7afc9 | 24 | #include "qemu/bswap.h" |
0b8fa32f | 25 | #include "qemu/module.h" |
0d09e41a | 26 | #include "hw/pci-host/ppce500.h" |
db1015e9 | 27 | #include "qom/object.h" |
74c62ba8 AJ |
28 | |
29 | #ifdef DEBUG_PCI | |
001faf32 | 30 | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
74c62ba8 | 31 | #else |
001faf32 | 32 | #define pci_debug(fmt, ...) |
74c62ba8 AJ |
33 | #endif |
34 | ||
35 | #define PCIE500_CFGADDR 0x0 | |
36 | #define PCIE500_CFGDATA 0x4 | |
37 | #define PCIE500_REG_BASE 0xC00 | |
be13cc7a AG |
38 | #define PCIE500_ALL_SIZE 0x1000 |
39 | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) | |
74c62ba8 | 40 | |
a1bc20df AG |
41 | #define PCIE500_PCI_IOLEN 0x10000ULL |
42 | ||
74c62ba8 AJ |
43 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
44 | #define PPCE500_PCI_CONFIG_DATA 0x4 | |
45 | #define PPCE500_PCI_INTACK 0x8 | |
46 | ||
47 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) | |
48 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) | |
49 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) | |
50 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) | |
51 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) | |
52 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) | |
53 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) | |
54 | ||
55 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) | |
56 | ||
57 | #define PCI_POTAR 0x0 | |
58 | #define PCI_POTEAR 0x4 | |
59 | #define PCI_POWBAR 0x8 | |
60 | #define PCI_POWAR 0x10 | |
61 | ||
62 | #define PCI_PITAR 0x0 | |
63 | #define PCI_PIWBAR 0x8 | |
64 | #define PCI_PIWBEAR 0xC | |
65 | #define PCI_PIWAR 0x10 | |
66 | ||
67 | #define PPCE500_PCI_NR_POBS 5 | |
68 | #define PPCE500_PCI_NR_PIBS 3 | |
69 | ||
cb3778a0 AG |
70 | #define PIWAR_EN 0x80000000 /* Enable */ |
71 | #define PIWAR_PF 0x20000000 /* prefetch */ | |
72 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ | |
73 | #define PIWAR_READ_SNOOP 0x00050000 | |
74 | #define PIWAR_WRITE_SNOOP 0x00005000 | |
75 | #define PIWAR_SZ_MASK 0x0000003f | |
76 | ||
74c62ba8 AJ |
77 | struct pci_outbound { |
78 | uint32_t potar; | |
79 | uint32_t potear; | |
80 | uint32_t powbar; | |
81 | uint32_t powar; | |
cb3778a0 | 82 | MemoryRegion mem; |
74c62ba8 AJ |
83 | }; |
84 | ||
85 | struct pci_inbound { | |
86 | uint32_t pitar; | |
87 | uint32_t piwbar; | |
88 | uint32_t piwbear; | |
89 | uint32_t piwar; | |
cb3778a0 | 90 | MemoryRegion mem; |
74c62ba8 AJ |
91 | }; |
92 | ||
9c1a61f0 AF |
93 | #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" |
94 | ||
db1015e9 | 95 | typedef struct PPCE500PCIState PPCE500PCIState; |
9c1a61f0 AF |
96 | #define PPC_E500_PCI_HOST_BRIDGE(obj) \ |
97 | OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) | |
98 | ||
74c62ba8 | 99 | struct PPCE500PCIState { |
67c332fd | 100 | PCIHostState parent_obj; |
9c1a61f0 | 101 | |
74c62ba8 AJ |
102 | struct pci_outbound pob[PPCE500_PCI_NR_POBS]; |
103 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; | |
104 | uint32_t gasket_time; | |
d575a6ce | 105 | qemu_irq irq[PCI_NUM_PINS]; |
3016dca0 | 106 | uint32_t irq_num[PCI_NUM_PINS]; |
eafb325f | 107 | uint32_t first_slot; |
3016dca0 | 108 | uint32_t first_pin_irq; |
cb3778a0 AG |
109 | AddressSpace bm_as; |
110 | MemoryRegion bm; | |
be13cc7a | 111 | /* mmio maps */ |
cb4e15c7 | 112 | MemoryRegion container; |
cd5cba79 | 113 | MemoryRegion iomem; |
a1bc20df | 114 | MemoryRegion pio; |
cb3778a0 | 115 | MemoryRegion busmem; |
74c62ba8 AJ |
116 | }; |
117 | ||
3eddc1be | 118 | #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" |
db1015e9 | 119 | typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; |
3eddc1be BB |
120 | #define PPC_E500_PCI_BRIDGE(obj) \ |
121 | OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) | |
122 | ||
123 | struct PPCE500PCIBridgeState { | |
124 | /*< private >*/ | |
125 | PCIDevice parent; | |
126 | /*< public >*/ | |
127 | ||
128 | MemoryRegion bar0; | |
129 | }; | |
130 | ||
74c62ba8 | 131 | |
a8170e5e | 132 | static uint64_t pci_reg_read4(void *opaque, hwaddr addr, |
cd5cba79 | 133 | unsigned size) |
74c62ba8 AJ |
134 | { |
135 | PPCE500PCIState *pci = opaque; | |
136 | unsigned long win; | |
137 | uint32_t value = 0; | |
eeae2e7b | 138 | int idx; |
74c62ba8 AJ |
139 | |
140 | win = addr & 0xfe0; | |
141 | ||
142 | switch (win) { | |
143 | case PPCE500_PCI_OW1: | |
144 | case PPCE500_PCI_OW2: | |
145 | case PPCE500_PCI_OW3: | |
146 | case PPCE500_PCI_OW4: | |
eeae2e7b | 147 | idx = (addr >> 5) & 0x7; |
e7f08320 | 148 | switch (addr & 0x1F) { |
6875dc8e | 149 | case PCI_POTAR: |
eeae2e7b | 150 | value = pci->pob[idx].potar; |
6875dc8e LY |
151 | break; |
152 | case PCI_POTEAR: | |
eeae2e7b | 153 | value = pci->pob[idx].potear; |
6875dc8e LY |
154 | break; |
155 | case PCI_POWBAR: | |
eeae2e7b | 156 | value = pci->pob[idx].powbar; |
6875dc8e LY |
157 | break; |
158 | case PCI_POWAR: | |
eeae2e7b | 159 | value = pci->pob[idx].powar; |
6875dc8e LY |
160 | break; |
161 | default: | |
162 | break; | |
74c62ba8 AJ |
163 | } |
164 | break; | |
165 | ||
166 | case PPCE500_PCI_IW3: | |
167 | case PPCE500_PCI_IW2: | |
168 | case PPCE500_PCI_IW1: | |
eeae2e7b | 169 | idx = ((addr >> 5) & 0x3) - 1; |
e7f08320 | 170 | switch (addr & 0x1F) { |
6875dc8e | 171 | case PCI_PITAR: |
eeae2e7b | 172 | value = pci->pib[idx].pitar; |
6875dc8e LY |
173 | break; |
174 | case PCI_PIWBAR: | |
eeae2e7b | 175 | value = pci->pib[idx].piwbar; |
6875dc8e LY |
176 | break; |
177 | case PCI_PIWBEAR: | |
eeae2e7b | 178 | value = pci->pib[idx].piwbear; |
6875dc8e LY |
179 | break; |
180 | case PCI_PIWAR: | |
eeae2e7b | 181 | value = pci->pib[idx].piwar; |
6875dc8e LY |
182 | break; |
183 | default: | |
184 | break; | |
74c62ba8 AJ |
185 | }; |
186 | break; | |
187 | ||
188 | case PPCE500_PCI_GASKET_TIMR: | |
189 | value = pci->gasket_time; | |
190 | break; | |
191 | ||
192 | default: | |
193 | break; | |
194 | } | |
195 | ||
c0a2a096 BS |
196 | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
197 | win, addr, value); | |
74c62ba8 AJ |
198 | return value; |
199 | } | |
200 | ||
cb3778a0 AG |
201 | /* DMA mapping */ |
202 | static void e500_update_piw(PPCE500PCIState *pci, int idx) | |
203 | { | |
204 | uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; | |
205 | uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; | |
206 | uint64_t war = pci->pib[idx].piwar; | |
207 | uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); | |
208 | MemoryRegion *address_space_mem = get_system_memory(); | |
209 | MemoryRegion *mem = &pci->pib[idx].mem; | |
210 | MemoryRegion *bm = &pci->bm; | |
211 | char *name; | |
212 | ||
213 | if (memory_region_is_mapped(mem)) { | |
214 | /* Before we modify anything, unmap and destroy the region */ | |
215 | memory_region_del_subregion(bm, mem); | |
216 | object_unparent(OBJECT(mem)); | |
217 | } | |
218 | ||
219 | if (!(war & PIWAR_EN)) { | |
220 | /* Not enabled, nothing to do */ | |
221 | return; | |
222 | } | |
223 | ||
224 | name = g_strdup_printf("PCI Inbound Window %d", idx); | |
225 | memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, | |
226 | size); | |
227 | memory_region_add_subregion_overlap(bm, wbar, mem, -1); | |
228 | g_free(name); | |
229 | ||
230 | pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", | |
231 | __func__, size, wbar, tar); | |
232 | } | |
233 | ||
234 | /* BAR mapping */ | |
235 | static void e500_update_pow(PPCE500PCIState *pci, int idx) | |
236 | { | |
237 | uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; | |
238 | uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; | |
239 | uint64_t war = pci->pob[idx].powar; | |
240 | uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); | |
241 | MemoryRegion *mem = &pci->pob[idx].mem; | |
242 | MemoryRegion *address_space_mem = get_system_memory(); | |
243 | char *name; | |
244 | ||
245 | if (memory_region_is_mapped(mem)) { | |
246 | /* Before we modify anything, unmap and destroy the region */ | |
247 | memory_region_del_subregion(address_space_mem, mem); | |
248 | object_unparent(OBJECT(mem)); | |
249 | } | |
250 | ||
251 | if (!(war & PIWAR_EN)) { | |
252 | /* Not enabled, nothing to do */ | |
253 | return; | |
254 | } | |
255 | ||
256 | name = g_strdup_printf("PCI Outbound Window %d", idx); | |
257 | memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, | |
258 | size); | |
259 | memory_region_add_subregion(address_space_mem, wbar, mem); | |
260 | g_free(name); | |
261 | ||
262 | pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", | |
263 | __func__, size, wbar, tar); | |
264 | } | |
265 | ||
a8170e5e | 266 | static void pci_reg_write4(void *opaque, hwaddr addr, |
cd5cba79 | 267 | uint64_t value, unsigned size) |
74c62ba8 AJ |
268 | { |
269 | PPCE500PCIState *pci = opaque; | |
270 | unsigned long win; | |
eeae2e7b | 271 | int idx; |
74c62ba8 AJ |
272 | |
273 | win = addr & 0xfe0; | |
274 | ||
c0a2a096 | 275 | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
cd5cba79 | 276 | __func__, (unsigned)value, win, addr); |
74c62ba8 AJ |
277 | |
278 | switch (win) { | |
279 | case PPCE500_PCI_OW1: | |
280 | case PPCE500_PCI_OW2: | |
281 | case PPCE500_PCI_OW3: | |
282 | case PPCE500_PCI_OW4: | |
eeae2e7b | 283 | idx = (addr >> 5) & 0x7; |
cb3778a0 | 284 | switch (addr & 0x1F) { |
6875dc8e | 285 | case PCI_POTAR: |
eeae2e7b | 286 | pci->pob[idx].potar = value; |
cb3778a0 | 287 | e500_update_pow(pci, idx); |
6875dc8e LY |
288 | break; |
289 | case PCI_POTEAR: | |
eeae2e7b | 290 | pci->pob[idx].potear = value; |
cb3778a0 | 291 | e500_update_pow(pci, idx); |
6875dc8e LY |
292 | break; |
293 | case PCI_POWBAR: | |
eeae2e7b | 294 | pci->pob[idx].powbar = value; |
cb3778a0 | 295 | e500_update_pow(pci, idx); |
6875dc8e LY |
296 | break; |
297 | case PCI_POWAR: | |
eeae2e7b | 298 | pci->pob[idx].powar = value; |
cb3778a0 | 299 | e500_update_pow(pci, idx); |
6875dc8e LY |
300 | break; |
301 | default: | |
302 | break; | |
74c62ba8 AJ |
303 | }; |
304 | break; | |
305 | ||
306 | case PPCE500_PCI_IW3: | |
307 | case PPCE500_PCI_IW2: | |
308 | case PPCE500_PCI_IW1: | |
eeae2e7b | 309 | idx = ((addr >> 5) & 0x3) - 1; |
cb3778a0 | 310 | switch (addr & 0x1F) { |
6875dc8e | 311 | case PCI_PITAR: |
eeae2e7b | 312 | pci->pib[idx].pitar = value; |
cb3778a0 | 313 | e500_update_piw(pci, idx); |
6875dc8e LY |
314 | break; |
315 | case PCI_PIWBAR: | |
eeae2e7b | 316 | pci->pib[idx].piwbar = value; |
cb3778a0 | 317 | e500_update_piw(pci, idx); |
6875dc8e LY |
318 | break; |
319 | case PCI_PIWBEAR: | |
eeae2e7b | 320 | pci->pib[idx].piwbear = value; |
cb3778a0 | 321 | e500_update_piw(pci, idx); |
6875dc8e LY |
322 | break; |
323 | case PCI_PIWAR: | |
eeae2e7b | 324 | pci->pib[idx].piwar = value; |
cb3778a0 | 325 | e500_update_piw(pci, idx); |
6875dc8e LY |
326 | break; |
327 | default: | |
328 | break; | |
74c62ba8 AJ |
329 | }; |
330 | break; | |
331 | ||
332 | case PPCE500_PCI_GASKET_TIMR: | |
333 | pci->gasket_time = value; | |
334 | break; | |
335 | ||
336 | default: | |
337 | break; | |
338 | }; | |
339 | } | |
340 | ||
cd5cba79 AK |
341 | static const MemoryRegionOps e500_pci_reg_ops = { |
342 | .read = pci_reg_read4, | |
343 | .write = pci_reg_write4, | |
344 | .endianness = DEVICE_BIG_ENDIAN, | |
74c62ba8 AJ |
345 | }; |
346 | ||
d575a6ce | 347 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) |
74c62ba8 | 348 | { |
05f57d9d AG |
349 | int devno = pci_dev->devfn >> 3; |
350 | int ret; | |
74c62ba8 | 351 | |
d575a6ce | 352 | ret = ppce500_pci_map_irq_slot(devno, pin); |
74c62ba8 AJ |
353 | |
354 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, | |
d575a6ce | 355 | pci_dev->devfn, pin, ret, devno); |
74c62ba8 AJ |
356 | |
357 | return ret; | |
358 | } | |
359 | ||
d575a6ce | 360 | static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) |
74c62ba8 | 361 | { |
3016dca0 BB |
362 | PPCE500PCIState *s = opaque; |
363 | qemu_irq *pic = s->irq; | |
5d4e84c8 | 364 | |
d575a6ce | 365 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); |
74c62ba8 | 366 | |
d575a6ce | 367 | qemu_set_irq(pic[pin], level); |
74c62ba8 AJ |
368 | } |
369 | ||
3016dca0 BB |
370 | static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) |
371 | { | |
372 | PCIINTxRoute route; | |
373 | PPCE500PCIState *s = opaque; | |
374 | ||
375 | route.mode = PCI_INTX_ENABLED; | |
376 | route.irq = s->irq_num[pin]; | |
377 | ||
378 | pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); | |
379 | return route; | |
380 | } | |
381 | ||
e0433ecc JQ |
382 | static const VMStateDescription vmstate_pci_outbound = { |
383 | .name = "pci_outbound", | |
384 | .version_id = 0, | |
385 | .minimum_version_id = 0, | |
3aff6c2f | 386 | .fields = (VMStateField[]) { |
e0433ecc JQ |
387 | VMSTATE_UINT32(potar, struct pci_outbound), |
388 | VMSTATE_UINT32(potear, struct pci_outbound), | |
389 | VMSTATE_UINT32(powbar, struct pci_outbound), | |
390 | VMSTATE_UINT32(powar, struct pci_outbound), | |
391 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 392 | } |
e0433ecc | 393 | }; |
74c62ba8 | 394 | |
e0433ecc JQ |
395 | static const VMStateDescription vmstate_pci_inbound = { |
396 | .name = "pci_inbound", | |
397 | .version_id = 0, | |
398 | .minimum_version_id = 0, | |
3aff6c2f | 399 | .fields = (VMStateField[]) { |
e0433ecc JQ |
400 | VMSTATE_UINT32(pitar, struct pci_inbound), |
401 | VMSTATE_UINT32(piwbar, struct pci_inbound), | |
402 | VMSTATE_UINT32(piwbear, struct pci_inbound), | |
403 | VMSTATE_UINT32(piwar, struct pci_inbound), | |
404 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 405 | } |
e0433ecc | 406 | }; |
74c62ba8 | 407 | |
e0433ecc JQ |
408 | static const VMStateDescription vmstate_ppce500_pci = { |
409 | .name = "ppce500_pci", | |
410 | .version_id = 1, | |
411 | .minimum_version_id = 1, | |
3aff6c2f | 412 | .fields = (VMStateField[]) { |
e0433ecc JQ |
413 | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, |
414 | vmstate_pci_outbound, struct pci_outbound), | |
415 | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, | |
f2e2bc9c | 416 | vmstate_pci_inbound, struct pci_inbound), |
e0433ecc JQ |
417 | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
418 | VMSTATE_END_OF_LIST() | |
74c62ba8 | 419 | } |
e0433ecc | 420 | }; |
74c62ba8 | 421 | |
022c62cb | 422 | #include "exec/address-spaces.h" |
1e39101c | 423 | |
9af21dbe | 424 | static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) |
3eddc1be BB |
425 | { |
426 | PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); | |
427 | PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), | |
428 | "/e500-ccsr")); | |
429 | ||
40c5dce9 | 430 | memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, |
3eddc1be BB |
431 | 0, int128_get64(ccsr->ccsr_space.size)); |
432 | pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); | |
3eddc1be BB |
433 | } |
434 | ||
cb3778a0 AG |
435 | static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, |
436 | int devfn) | |
437 | { | |
438 | PPCE500PCIState *s = opaque; | |
439 | ||
440 | return &s->bm_as; | |
441 | } | |
442 | ||
73785b32 | 443 | static void e500_pcihost_realize(DeviceState *dev, Error **errp) |
be13cc7a | 444 | { |
73785b32 | 445 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
be13cc7a AG |
446 | PCIHostState *h; |
447 | PPCE500PCIState *s; | |
448 | PCIBus *b; | |
449 | int i; | |
450 | ||
8558d942 | 451 | h = PCI_HOST_BRIDGE(dev); |
9c1a61f0 | 452 | s = PPC_E500_PCI_HOST_BRIDGE(dev); |
be13cc7a AG |
453 | |
454 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
73785b32 | 455 | sysbus_init_irq(sbd, &s->irq[i]); |
be13cc7a AG |
456 | } |
457 | ||
3016dca0 BB |
458 | for (i = 0; i < PCI_NUM_PINS; i++) { |
459 | s->irq_num[i] = s->first_pin_irq + i; | |
460 | } | |
461 | ||
40c5dce9 | 462 | memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); |
cb3778a0 AG |
463 | memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); |
464 | ||
465 | /* PIO lives at the bottom of our bus space */ | |
466 | memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); | |
a1bc20df | 467 | |
73785b32 | 468 | b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq, |
1115ff6d DG |
469 | mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, |
470 | PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); | |
9c1a61f0 | 471 | h->bus = b; |
be13cc7a | 472 | |
cb3778a0 AG |
473 | /* Set up PCI view of memory */ |
474 | memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); | |
475 | memory_region_add_subregion(&s->bm, 0x0, &s->busmem); | |
476 | address_space_init(&s->bm_as, &s->bm, "pci-bm"); | |
477 | pci_setup_iommu(b, e500_pcihost_set_iommu, s); | |
478 | ||
be13cc7a AG |
479 | pci_create_simple(b, 0, "e500-host-bridge"); |
480 | ||
40c5dce9 PB |
481 | memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); |
482 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, | |
d0ed8076 | 483 | "pci-conf-idx", 4); |
40c5dce9 | 484 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, |
d0ed8076 | 485 | "pci-conf-data", 4); |
40c5dce9 | 486 | memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, |
cd5cba79 | 487 | "pci.reg", PCIE500_REG_SIZE); |
cb4e15c7 BC |
488 | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
489 | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); | |
490 | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); | |
73785b32 | 491 | sysbus_init_mmio(sbd, &s->container); |
3016dca0 | 492 | pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); |
be13cc7a AG |
493 | } |
494 | ||
40021f08 AL |
495 | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
496 | { | |
39bffca2 | 497 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
498 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
499 | ||
9af21dbe | 500 | k->realize = e500_pcihost_bridge_realize; |
40021f08 AL |
501 | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
502 | k->device_id = PCI_DEVICE_ID_MPC8533E; | |
503 | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; | |
39bffca2 | 504 | dc->desc = "Host bridge"; |
08c58f92 MA |
505 | /* |
506 | * PCI-facing part of the host bridge, not usable without the | |
507 | * host-facing part, which can't be device_add'ed, yet. | |
508 | */ | |
e90f2a8c | 509 | dc->user_creatable = false; |
40021f08 AL |
510 | } |
511 | ||
4240abff | 512 | static const TypeInfo e500_host_bridge_info = { |
8c2eedce | 513 | .name = TYPE_PPC_E500_PCI_BRIDGE, |
39bffca2 | 514 | .parent = TYPE_PCI_DEVICE, |
3eddc1be | 515 | .instance_size = sizeof(PPCE500PCIBridgeState), |
39bffca2 | 516 | .class_init = e500_host_bridge_class_init, |
fd3b02c8 EH |
517 | .interfaces = (InterfaceInfo[]) { |
518 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
519 | { }, | |
520 | }, | |
be13cc7a AG |
521 | }; |
522 | ||
eafb325f AG |
523 | static Property pcihost_properties[] = { |
524 | DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), | |
3016dca0 | 525 | DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), |
eafb325f AG |
526 | DEFINE_PROP_END_OF_LIST(), |
527 | }; | |
528 | ||
999e12bb AL |
529 | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
530 | { | |
39bffca2 | 531 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 532 | |
73785b32 | 533 | dc->realize = e500_pcihost_realize; |
125ee0ed | 534 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4f67d30b | 535 | device_class_set_props(dc, pcihost_properties); |
39bffca2 | 536 | dc->vmsd = &vmstate_ppce500_pci; |
999e12bb AL |
537 | } |
538 | ||
4240abff | 539 | static const TypeInfo e500_pcihost_info = { |
9c1a61f0 | 540 | .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, |
8558d942 | 541 | .parent = TYPE_PCI_HOST_BRIDGE, |
39bffca2 AL |
542 | .instance_size = sizeof(PPCE500PCIState), |
543 | .class_init = e500_pcihost_class_init, | |
be13cc7a AG |
544 | }; |
545 | ||
83f7d43a | 546 | static void e500_pci_register_types(void) |
74c62ba8 | 547 | { |
39bffca2 AL |
548 | type_register_static(&e500_pcihost_info); |
549 | type_register_static(&e500_host_bridge_info); | |
74c62ba8 | 550 | } |
83f7d43a AF |
551 | |
552 | type_init(e500_pci_register_types) |