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sysbus: Convert to sysbus_realize() etc. with Coccinelle
[thirdparty/qemu.git] / hw / ppc / pnv.c
CommitLineData
9e933f4a
BH		 1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
fc6b3cf9 22#include "qemu/units.h"
9e933f4a
BH		 23#include "qapi/error.h"
24#include "sysemu/sysemu.h"
25#include "sysemu/numa.h"
71e8a915 26#include "sysemu/reset.h"
54d31236 27#include "sysemu/runstate.h"
d2528bdc 28#include "sysemu/cpus.h"
8d409261 29#include "sysemu/device_tree.h"
01b552b0 30#include "sysemu/hw_accel.h"
fcf5ef2a 31#include "target/ppc/cpu.h"
9e933f4a
BH		 32#include "qemu/log.h"
33#include "hw/ppc/fdt.h"
34#include "hw/ppc/ppc.h"
35#include "hw/ppc/pnv.h"
d2fd9612 36#include "hw/ppc/pnv_core.h"
9e933f4a 37#include "hw/loader.h"
01b552b0 38#include "hw/nmi.h"
9e933f4a 39#include "exec/address-spaces.h"
e997040e 40#include "qapi/visitor.h"
47fea43a
CLG		 41#include "monitor/monitor.h"
42#include "hw/intc/intc.h"
aeaef83d 43#include "hw/ipmi/ipmi.h"
58969eee 44#include "target/ppc/mmu-hash64.h"
4f9924c4 45#include "hw/pci/msi.h"
9e933f4a 46
36fc6f08 47#include "hw/ppc/xics.h"
a27bd6c7 48#include "hw/qdev-properties.h"
967b7523 49#include "hw/ppc/pnv_xscom.h"
35dde576 50#include "hw/ppc/pnv_pnor.h"
967b7523 51
3495b6b6 52#include "hw/isa/isa.h"
12e9493d 53#include "hw/boards.h"
3495b6b6 54#include "hw/char/serial.h"
bcdb9064 55#include "hw/rtc/mc146818rtc.h"
3495b6b6 56
9e933f4a
BH		 57#include <libfdt.h>
58
b268a616 59#define FDT_MAX_SIZE (1 * MiB)
9e933f4a
BH		 60
61#define FW_FILE_NAME "skiboot.lid"
62#define FW_LOAD_ADDR 0x0
b268a616 63#define FW_MAX_SIZE (4 * MiB)
9e933f4a
BH		 64
65#define KERNEL_LOAD_ADDR 0x20000000
b45b56ba 66#define KERNEL_MAX_SIZE (256 * MiB)
fef592f9 67#define INITRD_LOAD_ADDR 0x60000000
584ea7e7 68#define INITRD_MAX_SIZE (256 * MiB)
9e933f4a 69
40abf43f
IM		 70static const char *pnv_chip_core_typename(const PnvChip *o)
71{
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78}
79
9e933f4a
BH		 80/*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85#define MAX_CPUS 2048
86
87/*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
b168a138 92static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
9e933f4a
BH		 93{
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109}
110
d2fd9612
CLG		 111static int get_cpus_node(void *fdt)
112{
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
a4f3885c 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
d2fd9612
CLG		 117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124}
125
126/*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
b168a138 133static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
d2fd9612 134{
08304a86
DG		 135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
d2fd9612 137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
8bd9530e 138 int smt_threads = CPU_CORE(pc)->nr_threads;
d2fd9612
CLG		 139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
3dc6f869 183 warn_report("Unknown L1 dcache size for cpu");
d2fd9612
CLG		 184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
3dc6f869 189 warn_report("Unknown L1 icache size for cpu");
d2fd9612
CLG		 190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
59b7c1c2
B		 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
d2fd9612
CLG		 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (env->spr_cb[SPR_PURR].oea_read) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
58969eee 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
d2fd9612
CLG		 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
59b7c1c2
B		 208 /*
209 * Advertise VMX/VSX (vector extensions) if available
d2fd9612
CLG		 210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
59b7c1c2
B		 212 * 2 == VSX available
213 */
d2fd9612
CLG		 214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
59b7c1c2
B		 220 /*
221 * Advertise DFP (Decimal Floating Point) if available
d2fd9612 222 * 0 / no property == no DFP
59b7c1c2
B		 223 * 1 == DFP available
224 */
d2fd9612
CLG		 225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
644a2c99
DG		 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
d2fd9612
CLG		 231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
d2fd9612
CLG		 239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245}
246
b168a138
CLG		 247static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
bf5615e7
CLG		 249{
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282}
283
eb859a27 284static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
e997040e 285{
c396c58a 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
d2fd9612
CLG		 287 int i;
288
3f5b45ca
GK		 289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
c396c58a
GK		 291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
967b7523 293
d2fd9612 294 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 295 PnvCore *pnv_core = chip->cores[i];
d2fd9612 296
b168a138 297 pnv_dt_core(chip, pnv_core, fdt);
bf5615e7
CLG		 298
299 /* Interrupt Control Presenters (ICP). One per core. */
b168a138 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
d2fd9612
CLG		 301 }
302
e997040e 303 if (chip->ram_size) {
b168a138 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
e997040e
CLG		 305 }
306}
307
eb859a27
CLG		 308static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309{
c396c58a 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
eb859a27
CLG		 311 int i;
312
3f5b45ca
GK		 313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
c396c58a
GK		 315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
eb859a27
CLG		 317
318 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 319 PnvCore *pnv_core = chip->cores[i];
eb859a27
CLG		 320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
15376c66 327
2661f6ab 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
eb859a27
CLG		 329}
330
2b548a42
CLG		 331static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332{
c396c58a 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
2b548a42
CLG		 334 int i;
335
3f5b45ca
GK		 336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
c396c58a
GK		 338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
2b548a42
CLG		 340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
2661f6ab
CLG		 350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
2b548a42
CLG		 352}
353
b168a138 354static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
c5ffdcae
CLG		 355{
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372}
373
b168a138 374static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cb228f5a
CLG		 375{
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 char *name;
384 int node;
385
386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
387 node = fdt_add_subnode(fdt, lpc_off, name);
388 _FDT(node);
389 g_free(name);
390
391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
392 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
393 sizeof(compatible))));
394
395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
399 fdt_get_phandle(fdt, lpc_off))));
400
401 /* This is needed by Linux */
402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
403}
404
b168a138 405static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
04f6c8b2
CLG		 406{
407 const char compatible[] = "bt\0ipmi-bt";
408 uint32_t io_base;
409 uint32_t io_regs[] = {
410 cpu_to_be32(1),
411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
412 cpu_to_be32(3)
413 };
414 uint32_t irq;
415 char *name;
416 int node;
417
418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
419 io_regs[1] = cpu_to_be32(io_base);
420
421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
422
423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
424 node = fdt_add_subnode(fdt, lpc_off, name);
425 _FDT(node);
426 g_free(name);
427
7032d92a
CLG		 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
429 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
430 sizeof(compatible))));
04f6c8b2
CLG		 431
432 /* Mark it as reserved to avoid Linux trying to claim it */
433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
436 fdt_get_phandle(fdt, lpc_off))));
437}
438
e7a3fee3
CLG		 439typedef struct ForeachPopulateArgs {
440 void *fdt;
441 int offset;
442} ForeachPopulateArgs;
443
b168a138 444static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
e7a3fee3 445{
c5ffdcae
CLG		 446 ForeachPopulateArgs *args = opaque;
447 ISADevice *d = ISA_DEVICE(dev);
448
449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
b168a138 450 pnv_dt_rtc(d, args->fdt, args->offset);
cb228f5a 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
b168a138 452 pnv_dt_serial(d, args->fdt, args->offset);
04f6c8b2 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
b168a138 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
c5ffdcae
CLG		 455 } else {
456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
457 d->ioport_id);
458 }
459
e7a3fee3
CLG		 460 return 0;
461}
462
59b7c1c2
B		 463/*
464 * The default LPC bus of a multichip system is on chip 0. It's
bb7ab95c
CLG		 465 * recognized by the firmware (skiboot) using a "primary" property.
466 */
467static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
468{
64d011d5 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
e7a3fee3
CLG		 470 ForeachPopulateArgs args = {
471 .fdt = fdt,
bb7ab95c 472 .offset = isa_offset,
e7a3fee3 473 };
f47a08d1 474 uint32_t phandle;
e7a3fee3 475
bb7ab95c
CLG		 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
477
f47a08d1
CLG		 478 phandle = qemu_fdt_alloc_phandle(fdt);
479 assert(phandle > 0);
480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
481
59b7c1c2
B		 482 /*
483 * ISA devices are not necessarily parented to the ISA bus so we
484 * can not use object_child_foreach()
485 */
bb7ab95c
CLG		 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
487 &args);
e7a3fee3
CLG		 488}
489
7a90c6a1 490static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
e5694793
CLG		 491{
492 int off;
493
494 off = fdt_add_subnode(fdt, 0, "ibm,opal");
495 off = fdt_add_subnode(fdt, off, "power-mgt");
496
497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
498}
499
b168a138 500static void *pnv_dt_create(MachineState *machine)
9e933f4a 501{
d76f2da7 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
b168a138 503 PnvMachineState *pnv = PNV_MACHINE(machine);
9e933f4a
BH		 504 void *fdt;
505 char *buf;
506 int off;
e997040e 507 int i;
9e933f4a
BH		 508
509 fdt = g_malloc0(FDT_MAX_SIZE);
510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
511
ccb099b3
CLG		 512 /* /qemu node */
513 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
514
9e933f4a
BH		 515 /* Root node */
516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
518 _FDT((fdt_setprop_string(fdt, 0, "model",
519 "IBM PowerNV (emulated by qemu)")));
d76f2da7 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
9e933f4a
BH		 521
522 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
524 if (qemu_uuid_set) {
525 _FDT((fdt_property_string(fdt, "system-id", buf)));
526 }
527 g_free(buf);
528
529 off = fdt_add_subnode(fdt, 0, "chosen");
530 if (machine->kernel_cmdline) {
531 _FDT((fdt_setprop_string(fdt, off, "bootargs",
532 machine->kernel_cmdline)));
533 }
534
535 if (pnv->initrd_size) {
536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
538
539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
540 &start_prop, sizeof(start_prop))));
541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
542 &end_prop, sizeof(end_prop))));
543 }
544
e997040e
CLG		 545 /* Populate device tree for each chip */
546 for (i = 0; i < pnv->num_chips; i++) {
eb859a27 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
e997040e 548 }
e7a3fee3
CLG		 549
550 /* Populate ISA devices on chip 0 */
bb7ab95c 551 pnv_dt_isa(pnv, fdt);
aeaef83d
CLG		 552
553 if (pnv->bmc) {
b168a138 554 pnv_dt_bmc_sensors(pnv->bmc, fdt);
aeaef83d
CLG		 555 }
556
7a90c6a1
GK		 557 /* Create an extra node for power management on machines that support it */
558 if (pmc->dt_power_mgt) {
559 pmc->dt_power_mgt(pnv, fdt);
e5694793
CLG		 560 }
561
9e933f4a
BH		 562 return fdt;
563}
564
bce0b691
CLG		 565static void pnv_powerdown_notify(Notifier *n, void *opaque)
566{
8f06e370 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
bce0b691
CLG		 568
569 if (pnv->bmc) {
570 pnv_bmc_powerdown(pnv->bmc);
571 }
572}
573
a0628599 574static void pnv_reset(MachineState *machine)
9e933f4a 575{
25f3170b
CLG		 576 PnvMachineState *pnv = PNV_MACHINE(machine);
577 IPMIBmc *bmc;
9e933f4a
BH		 578 void *fdt;
579
580 qemu_devices_reset();
581
25f3170b
CLG		 582 /*
583 * The machine should provide by default an internal BMC simulator.
584 * If not, try to use the BMC device that was provided on the command
585 * line.
586 */
587 bmc = pnv_bmc_find(&error_fatal);
588 if (!pnv->bmc) {
589 if (!bmc) {
590 warn_report("machine has no BMC device. Use '-device "
591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
592 "to define one");
593 } else {
594 pnv_bmc_set_pnor(bmc, pnv->pnor);
595 pnv->bmc = bmc;
596 }
597 }
598
b168a138 599 fdt = pnv_dt_create(machine);
9e933f4a
BH		 600
601 /* Pack resulting tree */
602 _FDT((fdt_pack(fdt)));
603
8d409261 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
9e933f4a 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
b2fb7a43
PN		 606
607 g_free(fdt);
9e933f4a
BH		 608}
609
04026890 610static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
3495b6b6 611{
77864267
CLG		 612 Pnv8Chip *chip8 = PNV8_CHIP(chip);
613 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
04026890 614}
3495b6b6 615
04026890
CLG		 616static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
617{
77864267
CLG		 618 Pnv8Chip *chip8 = PNV8_CHIP(chip);
619 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
04026890 620}
3495b6b6 621
04026890
CLG		 622static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
623{
15376c66
CLG		 624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
04026890 626}
3495b6b6 627
2b548a42
CLG		 628static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
629{
2661f6ab
CLG		 630 Pnv10Chip *chip10 = PNV10_CHIP(chip);
631 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
2b548a42
CLG		 632}
633
04026890
CLG		 634static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
635{
636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
3495b6b6
CLG		 637}
638
d8e4aad5
CLG		 639static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
640{
641 Pnv8Chip *chip8 = PNV8_CHIP(chip);
9ae1329e 642 int i;
d8e4aad5
CLG		 643
644 ics_pic_print_info(&chip8->psi.ics, mon);
9ae1329e
CLG		 645 for (i = 0; i < chip->num_phbs; i++) {
646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
647 ics_pic_print_info(&chip8->phbs[i].lsis, mon);
648 }
d8e4aad5
CLG		 649}
650
651static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
652{
653 Pnv9Chip *chip9 = PNV9_CHIP(chip);
4f9924c4 654 int i, j;
d8e4aad5
CLG		 655
656 pnv_xive_pic_print_info(&chip9->xive, mon);
c38536bc 657 pnv_psi_pic_print_info(&chip9->psi, mon);
4f9924c4
BH		 658
659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
660 PnvPhb4PecState *pec = &chip9->pecs[i];
661 for (j = 0; j < pec->num_stacks; j++) {
662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
663 }
664 }
d8e4aad5
CLG		 665}
666
c4b2c40c
GK		 667static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
668 uint32_t core_id)
669{
670 return PNV_XSCOM_EX_BASE(core_id);
671}
672
673static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
674 uint32_t core_id)
675{
676 return PNV9_XSCOM_EC_BASE(core_id);
677}
678
679static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
680 uint32_t core_id)
681{
682 return PNV10_XSCOM_EC_BASE(core_id);
683}
684
f30c843c
CLG		 685static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
686{
687 PowerPCCPUClass *ppc_default =
688 POWERPC_CPU_CLASS(object_class_by_name(default_type));
689 PowerPCCPUClass *ppc =
690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
691
692 return ppc_default->pvr_match(ppc_default, ppc->pvr);
693}
694
e2392d43
CLG		 695static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
696{
c23e0561 697 ISADevice *dev = isa_new("isa-ipmi-bt");
e2392d43 698
c23e0561
MA		 699 object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal);
700 object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal);
701 isa_realize_and_unref(dev, bus, &error_fatal);
e2392d43
CLG		 702}
703
2b548a42
CLG		 704static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
705{
8b50ce85
CLG		 706 Pnv10Chip *chip10 = PNV10_CHIP(chip);
707
708 pnv_psi_pic_print_info(&chip10->psi, mon);
2b548a42
CLG		 709}
710
b168a138 711static void pnv_init(MachineState *machine)
9e933f4a 712{
b168a138 713 PnvMachineState *pnv = PNV_MACHINE(machine);
f30c843c 714 MachineClass *mc = MACHINE_GET_CLASS(machine);
9e933f4a
BH		 715 char *fw_filename;
716 long fw_size;
e997040e
CLG		 717 int i;
718 char *chip_typename;
35dde576
CLG		 719 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
720 DeviceState *dev;
9e933f4a
BH		 721
722 /* allocate RAM */
d23b6caa 723 if (machine->ram_size < (1 * GiB)) {
3dc6f869 724 warn_report("skiboot may not work with < 1GB of RAM");
9e933f4a 725 }
173a36d8 726 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
9e933f4a 727
35dde576
CLG		 728 /*
729 * Create our simple PNOR device
730 */
3e80f690 731 dev = qdev_new(TYPE_PNV_PNOR);
35dde576
CLG		 732 if (pnor) {
733 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
734 &error_abort);
735 }
3c6ef471 736 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
35dde576
CLG		 737 pnv->pnor = PNV_PNOR(dev);
738
9e933f4a
BH		 739 /* load skiboot firmware */
740 if (bios_name == NULL) {
741 bios_name = FW_FILE_NAME;
742 }
743
744 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
15fcedb2
CLG		 745 if (!fw_filename) {
746 error_report("Could not find OPAL firmware '%s'", bios_name);
747 exit(1);
748 }
9e933f4a 749
08c3f3a7 750 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
9e933f4a 751 if (fw_size < 0) {
15fcedb2 752 error_report("Could not load OPAL firmware '%s'", fw_filename);
9e933f4a
BH		 753 exit(1);
754 }
755 g_free(fw_filename);
756
757 /* load kernel */
758 if (machine->kernel_filename) {
759 long kernel_size;
760
761 kernel_size = load_image_targphys(machine->kernel_filename,
b45b56ba 762 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
9e933f4a 763 if (kernel_size < 0) {
802fc7ab 764 error_report("Could not load kernel '%s'",
7c6e8797 765 machine->kernel_filename);
9e933f4a
BH		 766 exit(1);
767 }
768 }
769
770 /* load initrd */
771 if (machine->initrd_filename) {
772 pnv->initrd_base = INITRD_LOAD_ADDR;
773 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
584ea7e7 774 pnv->initrd_base, INITRD_MAX_SIZE);
9e933f4a 775 if (pnv->initrd_size < 0) {
802fc7ab 776 error_report("Could not load initial ram disk '%s'",
9e933f4a
BH		 777 machine->initrd_filename);
778 exit(1);
779 }
780 }
e997040e 781
4f9924c4
BH		 782 /* MSIs are supported on this platform */
783 msi_nonbroken = true;
784
f30c843c
CLG		 785 /*
786 * Check compatibility of the specified CPU with the machine
787 * default.
788 */
789 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
790 error_report("invalid CPU model '%s' for %s machine",
791 machine->cpu_type, mc->name);
792 exit(1);
793 }
794
e997040e 795 /* Create the processor chips */
4a12c699 796 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
7fd544d8 797 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
4a12c699 798 i, machine->cpu_type);
e997040e 799 if (!object_class_by_name(chip_typename)) {
f30c843c
CLG		 800 error_report("invalid chip model '%.*s' for %s machine",
801 i, machine->cpu_type, mc->name);
e997040e
CLG		 802 exit(1);
803 }
804
e44acde2
GK		 805 pnv->num_chips =
806 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
807 /*
808 * TODO: should we decide on how many chips we can create based
809 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
810 */
811 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
812 error_report("invalid number of chips: '%d'", pnv->num_chips);
813 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
814 exit(1);
815 }
816
e997040e
CLG		 817 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
818 for (i = 0; i < pnv->num_chips; i++) {
819 char chip_name[32];
df707969 820 Object *chip = OBJECT(qdev_new(chip_typename));
e997040e
CLG		 821
822 pnv->chips[i] = PNV_CHIP(chip);
823
59b7c1c2
B		 824 /*
825 * TODO: put all the memory in one node on chip 0 until we find a
e997040e
CLG		 826 * way to specify different ranges for each chip
827 */
828 if (i == 0) {
829 object_property_set_int(chip, machine->ram_size, "ram-size",
830 &error_fatal);
831 }
832
833 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
d2623129 834 object_property_add_child(OBJECT(pnv), chip_name, chip);
e997040e
CLG		 835 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
836 &error_fatal);
fe6b6346
LX		 837 object_property_set_int(chip, machine->smp.cores,
838 "nr-cores", &error_fatal);
764f9b25
GK		 839 object_property_set_int(chip, machine->smp.threads,
840 "nr-threads", &error_fatal);
245cdb7f
CLG		 841 /*
842 * The POWER8 machine use the XICS interrupt interface.
843 * Propagate the XICS fabric to the chip and its controllers.
844 */
845 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
846 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
847 }
d1214b81
GK		 848 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
849 object_property_set_link(chip, OBJECT(pnv), "xive-fabric",
850 &error_abort);
851 }
3c6ef471 852 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
e997040e
CLG		 853 }
854 g_free(chip_typename);
3495b6b6
CLG		 855
856 /* Instantiate ISA bus on chip 0 */
04026890 857 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
3495b6b6
CLG		 858
859 /* Create serial port */
def337ff 860 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
3495b6b6
CLG		 861
862 /* Create an RTC ISA device too */
6c646a11 863 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
bce0b691 864
25f3170b
CLG		 865 /*
866 * Create the machine BMC simulator and the IPMI BT device for
867 * communication with the BMC
868 */
869 if (defaults_enabled()) {
870 pnv->bmc = pnv_bmc_create(pnv->pnor);
871 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
872 }
e2392d43 873
59b7c1c2
B		 874 /*
875 * OpenPOWER systems use a IPMI SEL Event message to notify the
876 * host to powerdown
877 */
bce0b691
CLG		 878 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
879 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
e997040e
CLG		 880}
881
631adaff
CLG		 882/*
883 * 0:21 Reserved - Read as zeros
884 * 22:24 Chip ID
885 * 25:28 Core number
886 * 29:31 Thread ID
887 */
888static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
889{
890 return (chip->chip_id << 7) | (core_id << 3);
891}
892
8fa1f4ef
CLG		 893static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
894 Error **errp)
d35aefa9 895{
245cdb7f 896 Pnv8Chip *chip8 = PNV8_CHIP(chip);
8fa1f4ef
CLG		 897 Error *local_err = NULL;
898 Object *obj;
8907fc25 899 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8fa1f4ef 900
245cdb7f 901 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
8fa1f4ef
CLG		 902 if (local_err) {
903 error_propagate(errp, local_err);
904 return;
905 }
906
956b8f46 907 pnv_cpu->intc = obj;
d35aefa9
CLG		 908}
909
0990ce6a 910
d49e8a9b
CLG		 911static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
912{
913 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
914
915 icp_reset(ICP(pnv_cpu->intc));
916}
917
0990ce6a
GK		 918static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
919{
920 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
921
922 icp_destroy(ICP(pnv_cpu->intc));
923 pnv_cpu->intc = NULL;
924}
925
85913070
GK		 926static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
927 Monitor *mon)
928{
929 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
930}
931
631adaff
CLG		 932/*
933 * 0:48 Reserved - Read as zeroes
934 * 49:52 Node ID
935 * 53:55 Chip ID
936 * 56 Reserved - Read as zero
937 * 57:61 Core number
938 * 62:63 Thread ID
939 *
940 * We only care about the lower bits. uint32_t is fine for the moment.
941 */
942static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
943{
944 return (chip->chip_id << 8) | (core_id << 2);
945}
946
2b548a42
CLG		 947static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
948{
949 return (chip->chip_id << 8) | (core_id << 2);
950}
951
8fa1f4ef
CLG		 952static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
953 Error **errp)
d35aefa9 954{
2dfa91a2
CLG		 955 Pnv9Chip *chip9 = PNV9_CHIP(chip);
956 Error *local_err = NULL;
957 Object *obj;
958 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
959
960 /*
961 * The core creates its interrupt presenter but the XIVE interrupt
962 * controller object is initialized afterwards. Hopefully, it's
963 * only used at runtime.
964 */
47950946
CLG		 965 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
966 &local_err);
2dfa91a2
CLG		 967 if (local_err) {
968 error_propagate(errp, local_err);
969 return;
970 }
971
972 pnv_cpu->intc = obj;
d35aefa9
CLG		 973}
974
d49e8a9b
CLG		 975static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
976{
977 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
978
979 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
980}
981
0990ce6a
GK		 982static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
983{
984 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
985
986 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
987 pnv_cpu->intc = NULL;
988}
989
85913070
GK		 990static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
991 Monitor *mon)
992{
993 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
994}
995
2b548a42
CLG		 996static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
997 Error **errp)
998{
999 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1000
1001 /* Will be defined when the interrupt controller is */
1002 pnv_cpu->intc = NULL;
1003}
1004
1005static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1006{
1007 ;
1008}
1009
1010static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1011{
1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1013
1014 pnv_cpu->intc = NULL;
1015}
1016
85913070
GK		 1017static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1018 Monitor *mon)
1019{
1020}
1021
59b7c1c2
B		 1022/*
1023 * Allowed core identifiers on a POWER8 Processor Chip :
397a79e7
CLG		 1024 *
1025 * <EX0 reserved>
1026 * EX1 - Venice only
1027 * EX2 - Venice only
1028 * EX3 - Venice only
1029 * EX4
1030 * EX5
1031 * EX6
1032 * <EX7,8 reserved> <reserved>
1033 * EX9 - Venice only
1034 * EX10 - Venice only
1035 * EX11 - Venice only
1036 * EX12
1037 * EX13
1038 * EX14
1039 * <EX15 reserved>
1040 */
1041#define POWER8E_CORE_MASK (0x7070ull)
1042#define POWER8_CORE_MASK (0x7e7eull)
1043
1044/*
09279d7e 1045 * POWER9 has 24 cores, ids starting at 0x0
397a79e7 1046 */
09279d7e 1047#define POWER9_CORE_MASK (0xffffffffffffffull)
397a79e7 1048
2b548a42
CLG		 1049
1050#define POWER10_CORE_MASK (0xffffffffffffffull)
1051
77864267
CLG		 1052static void pnv_chip_power8_instance_init(Object *obj)
1053{
9ae1329e 1054 PnvChip *chip = PNV_CHIP(obj);
77864267 1055 Pnv8Chip *chip8 = PNV8_CHIP(obj);
9ae1329e
CLG		 1056 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1057 int i;
77864267 1058
245cdb7f
CLG		 1059 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1060 (Object **)&chip8->xics,
1061 object_property_allow_set_link,
d2623129 1062 OBJ_PROP_LINK_STRONG);
245cdb7f 1063
9fc7fc4d 1064 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
77864267 1065
9fc7fc4d 1066 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
77864267 1067
9fc7fc4d 1068 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
3887d241 1069
9fc7fc4d 1070 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
9ae1329e
CLG		 1071
1072 for (i = 0; i < pcc->num_phbs; i++) {
9fc7fc4d 1073 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
9ae1329e
CLG		 1074 }
1075
1076 /*
1077 * Number of PHBs is the chip default
1078 */
1079 chip->num_phbs = pcc->num_phbs;
77864267
CLG		 1080}
1081
1082static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1083 {
1084 PnvChip *chip = PNV_CHIP(chip8);
1085 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
77864267
CLG		 1086 int i, j;
1087 char *name;
77864267
CLG		 1088
1089 name = g_strdup_printf("icp-%x", chip->chip_id);
1090 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1091 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1092 g_free(name);
1093
1094 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1095
1096 /* Map the ICP registers for each thread */
1097 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 1098 PnvCore *pnv_core = chip->cores[i];
77864267
CLG		 1099 int core_hwid = CPU_CORE(pnv_core)->core_id;
1100
1101 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1102 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
245cdb7f 1103 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
77864267
CLG		 1104
1105 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1106 &icp->mmio);
1107 }
1108 }
1109}
1110
1111static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1112{
1113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1114 PnvChip *chip = PNV_CHIP(dev);
1115 Pnv8Chip *chip8 = PNV8_CHIP(dev);
ae856055 1116 Pnv8Psi *psi8 = &chip8->psi;
77864267 1117 Error *local_err = NULL;
9ae1329e 1118 int i;
77864267 1119
245cdb7f
CLG		 1120 assert(chip8->xics);
1121
709044fd
CLG		 1122 /* XSCOM bridge is first */
1123 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1124 if (local_err) {
1125 error_propagate(errp, local_err);
1126 return;
1127 }
1128 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1129
77864267
CLG		 1130 pcc->parent_realize(dev, &local_err);
1131 if (local_err) {
1132 error_propagate(errp, local_err);
1133 return;
1134 }
1135
1136 /* Processor Service Interface (PSI) Host Bridge */
1137 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1138 "bar", &error_fatal);
245cdb7f 1139 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
34bdca8f 1140 ICS_PROP_XICS, &error_abort);
77864267
CLG		 1141 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1142 if (local_err) {
1143 error_propagate(errp, local_err);
1144 return;
1145 }
ae856055
CLG		 1146 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1147 &PNV_PSI(psi8)->xscom_regs);
77864267
CLG		 1148
1149 /* Create LPC controller */
b63f3893
GK		 1150 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1151 &error_abort);
77864267
CLG		 1152 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1153 &error_fatal);
1154 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1155
64d011d5
CLG		 1156 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1157 (uint64_t) PNV_XSCOM_BASE(chip),
1158 PNV_XSCOM_LPC_BASE);
1159
59b7c1c2
B		 1160 /*
1161 * Interrupt Management Area. This is the memory region holding
1162 * all the Interrupt Control Presenter (ICP) registers
1163 */
77864267
CLG		 1164 pnv_chip_icp_realize(chip8, &local_err);
1165 if (local_err) {
1166 error_propagate(errp, local_err);
1167 return;
1168 }
1169
1170 /* Create the simplified OCC model */
ee3d2713
GK		 1171 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1172 &error_abort);
77864267
CLG		 1173 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1174 if (local_err) {
1175 error_propagate(errp, local_err);
1176 return;
1177 }
1178 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
f3db8266
B		 1179
1180 /* OCC SRAM model */
3a1b70b6 1181 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
f3db8266 1182 &chip8->occ.sram_regs);
3887d241
B		 1183
1184 /* HOMER */
f2582acf
GK		 1185 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1186 &error_abort);
3887d241
B		 1187 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1188 &local_err);
1189 if (local_err) {
1190 error_propagate(errp, local_err);
1191 return;
1192 }
8f092316
CLG		 1193 /* Homer Xscom region */
1194 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1195
1196 /* Homer mmio region */
3887d241
B		 1197 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1198 &chip8->homer.regs);
9ae1329e
CLG		 1199
1200 /* PHB3 controllers */
1201 for (i = 0; i < chip->num_phbs; i++) {
1202 PnvPHB3 *phb = &chip8->phbs[i];
1203 PnvPBCQState *pbcq = &phb->pbcq;
1204
1205 object_property_set_int(OBJECT(phb), i, "index", &error_fatal);
1206 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id",
1207 &error_fatal);
3c6ef471 1208 sysbus_realize(SYS_BUS_DEVICE(phb), &local_err);
9ae1329e
CLG		 1209 if (local_err) {
1210 error_propagate(errp, local_err);
1211 return;
1212 }
9ae1329e
CLG		 1213
1214 /* Populate the XSCOM address space. */
1215 pnv_xscom_add_subregion(chip,
1216 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
1217 &pbcq->xscom_nest_regs);
1218 pnv_xscom_add_subregion(chip,
1219 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
1220 &pbcq->xscom_pci_regs);
1221 pnv_xscom_add_subregion(chip,
1222 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
1223 &pbcq->xscom_spci_regs);
1224 }
77864267
CLG		 1225}
1226
70c059e9
GK		 1227static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1228{
1229 addr &= (PNV_XSCOM_SIZE - 1);
1230 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1231}
1232
e997040e
CLG		 1233static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1234{
1235 DeviceClass *dc = DEVICE_CLASS(klass);
1236 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1237
e997040e 1238 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
397a79e7 1239 k->cores_mask = POWER8E_CORE_MASK;
9ae1329e 1240 k->num_phbs = 3;
631adaff 1241 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1242 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1243 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1244 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1245 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1246 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1247 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1248 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1249 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1250 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1251 dc->desc = "PowerNV Chip POWER8E";
77864267
CLG		 1252
1253 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1254 &k->parent_realize);
e997040e
CLG		 1255}
1256
e997040e
CLG		 1257static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1258{
1259 DeviceClass *dc = DEVICE_CLASS(klass);
1260 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1261
e997040e 1262 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
397a79e7 1263 k->cores_mask = POWER8_CORE_MASK;
9ae1329e 1264 k->num_phbs = 3;
631adaff 1265 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1266 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1267 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1268 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1269 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1270 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1271 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1272 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1273 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1274 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1275 dc->desc = "PowerNV Chip POWER8";
77864267
CLG		 1276
1277 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1278 &k->parent_realize);
e997040e
CLG		 1279}
1280
e997040e
CLG		 1281static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1282{
1283 DeviceClass *dc = DEVICE_CLASS(klass);
1284 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1285
e997040e 1286 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
397a79e7 1287 k->cores_mask = POWER8_CORE_MASK;
9ae1329e 1288 k->num_phbs = 3;
631adaff 1289 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1290 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1291 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1292 k->intc_destroy = pnv_chip_power8_intc_destroy;
85913070 1293 k->intc_print_info = pnv_chip_power8_intc_print_info;
04026890 1294 k->isa_create = pnv_chip_power8nvl_isa_create;
eb859a27 1295 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1296 k->pic_print_info = pnv_chip_power8_pic_print_info;
c4b2c40c 1297 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
70c059e9 1298 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
e997040e 1299 dc->desc = "PowerNV Chip POWER8NVL";
77864267
CLG		 1300
1301 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1302 &k->parent_realize);
1303}
1304
1305static void pnv_chip_power9_instance_init(Object *obj)
1306{
4f9924c4 1307 PnvChip *chip = PNV_CHIP(obj);
2dfa91a2 1308 Pnv9Chip *chip9 = PNV9_CHIP(obj);
4f9924c4
BH		 1309 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1310 int i;
2dfa91a2 1311
9354eaaf
MA		 1312 sysbus_init_child_obj(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1313 TYPE_PNV_XIVE);
d1214b81 1314 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
d2623129 1315 "xive-fabric");
c38536bc 1316
9fc7fc4d 1317 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
15376c66 1318
9fc7fc4d 1319 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
6598a70d 1320
9fc7fc4d 1321 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
3887d241 1322
9fc7fc4d 1323 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
4f9924c4
BH		 1324
1325 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1326 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
9fc7fc4d 1327 TYPE_PNV_PHB4_PEC);
4f9924c4
BH		 1328 }
1329
1330 /*
1331 * Number of PHBs is the chip default
1332 */
1333 chip->num_phbs = pcc->num_phbs;
77864267
CLG		 1334}
1335
5dad902c
CLG		 1336static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1337{
1338 PnvChip *chip = PNV_CHIP(chip9);
5dad902c
CLG		 1339 int i;
1340
1341 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1342 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1343
1344 for (i = 0; i < chip9->nr_quads; i++) {
1345 char eq_name[32];
1346 PnvQuad *eq = &chip9->quads[i];
4fa28f23 1347 PnvCore *pnv_core = chip->cores[i * 4];
5dad902c
CLG		 1348 int core_id = CPU_CORE(pnv_core)->core_id;
1349
5dad902c 1350 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
9fc7fc4d
MA		 1351 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1352 sizeof(*eq), TYPE_PNV_QUAD,
1353 &error_fatal, NULL);
5dad902c 1354
5dad902c
CLG		 1355 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1356 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
5dad902c
CLG		 1357
1358 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1359 &eq->xscom_regs);
1360 }
1361}
1362
4f9924c4
BH		 1363static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
1364{
1365 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1366 Error *local_err = NULL;
1367 int i, j;
1368 int phb_id = 0;
1369
1370 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1371 PnvPhb4PecState *pec = &chip9->pecs[i];
1372 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1373 uint32_t pec_nest_base;
1374 uint32_t pec_pci_base;
1375
1376 object_property_set_int(OBJECT(pec), i, "index", &error_fatal);
1377 /*
1378 * PEC0 -> 1 stack
1379 * PEC1 -> 2 stacks
1380 * PEC2 -> 3 stacks
1381 */
1382 object_property_set_int(OBJECT(pec), i + 1, "num-stacks",
1383 &error_fatal);
1384 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id",
1385 &error_fatal);
1386 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()),
1387 "system-memory", &error_abort);
1388 object_property_set_bool(OBJECT(pec), true, "realized", &local_err);
1389 if (local_err) {
1390 error_propagate(errp, local_err);
1391 return;
1392 }
1393
1394 pec_nest_base = pecc->xscom_nest_base(pec);
1395 pec_pci_base = pecc->xscom_pci_base(pec);
1396
1397 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1398 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1399
1400 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
1401 j++, phb_id++) {
1402 PnvPhb4PecStack *stack = &pec->stacks[j];
1403 Object *obj = OBJECT(&stack->phb);
1404
1405 object_property_set_int(obj, phb_id, "index", &error_fatal);
1406 object_property_set_int(obj, chip->chip_id, "chip-id",
1407 &error_fatal);
1408 object_property_set_int(obj, PNV_PHB4_VERSION, "version",
1409 &error_fatal);
1410 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id",
1411 &error_fatal);
1412 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort);
3c6ef471 1413 sysbus_realize(SYS_BUS_DEVICE(obj), &local_err);
4f9924c4
BH		 1414 if (local_err) {
1415 error_propagate(errp, local_err);
1416 return;
1417 }
4f9924c4
BH		 1418
1419 /* Populate the XSCOM address space. */
1420 pnv_xscom_add_subregion(chip,
1421 pec_nest_base + 0x40 * (stack->stack_no + 1),
1422 &stack->nest_regs_mr);
1423 pnv_xscom_add_subregion(chip,
1424 pec_pci_base + 0x40 * (stack->stack_no + 1),
1425 &stack->pci_regs_mr);
1426 pnv_xscom_add_subregion(chip,
1427 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1428 0x40 * stack->stack_no,
1429 &stack->phb_regs_mr);
1430 }
1431 }
1432}
1433
77864267
CLG		 1434static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1435{
1436 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2dfa91a2
CLG		 1437 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1438 PnvChip *chip = PNV_CHIP(dev);
c38536bc 1439 Pnv9Psi *psi9 = &chip9->psi;
77864267
CLG		 1440 Error *local_err = NULL;
1441
709044fd
CLG		 1442 /* XSCOM bridge is first */
1443 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1444 if (local_err) {
1445 error_propagate(errp, local_err);
1446 return;
1447 }
1448 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1449
77864267
CLG		 1450 pcc->parent_realize(dev, &local_err);
1451 if (local_err) {
1452 error_propagate(errp, local_err);
1453 return;
1454 }
2dfa91a2 1455
5dad902c
CLG		 1456 pnv_chip_quad_realize(chip9, &local_err);
1457 if (local_err) {
1458 error_propagate(errp, local_err);
1459 return;
1460 }
1461
2dfa91a2
CLG		 1462 /* XIVE interrupt controller (POWER9) */
1463 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1464 "ic-bar", &error_fatal);
1465 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1466 "vc-bar", &error_fatal);
1467 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1468 "pc-bar", &error_fatal);
1469 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1470 "tm-bar", &error_fatal);
7ae54cc3
GK		 1471 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1472 &error_abort);
2dfa91a2
CLG		 1473 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1474 &local_err);
1475 if (local_err) {
1476 error_propagate(errp, local_err);
1477 return;
1478 }
1479 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1480 &chip9->xive.xscom_regs);
c38536bc
CLG		 1481
1482 /* Processor Service Interface (PSI) Host Bridge */
1483 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1484 "bar", &error_fatal);
1485 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1486 if (local_err) {
1487 error_propagate(errp, local_err);
1488 return;
1489 }
1490 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1491 &PNV_PSI(psi9)->xscom_regs);
15376c66
CLG		 1492
1493 /* LPC */
b63f3893
GK		 1494 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1495 &error_abort);
15376c66
CLG		 1496 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1497 if (local_err) {
1498 error_propagate(errp, local_err);
1499 return;
1500 }
1501 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1502 &chip9->lpc.xscom_regs);
1503
1504 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1505 (uint64_t) PNV9_LPCM_BASE(chip));
6598a70d
CLG		 1506
1507 /* Create the simplified OCC model */
ee3d2713
GK		 1508 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1509 &error_abort);
6598a70d
CLG		 1510 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1511 if (local_err) {
1512 error_propagate(errp, local_err);
1513 return;
1514 }
1515 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
f3db8266
B		 1516
1517 /* OCC SRAM model */
3a1b70b6 1518 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
f3db8266 1519 &chip9->occ.sram_regs);
3887d241
B		 1520
1521 /* HOMER */
f2582acf
GK		 1522 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1523 &error_abort);
3887d241
B		 1524 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1525 &local_err);
1526 if (local_err) {
1527 error_propagate(errp, local_err);
1528 return;
1529 }
8f092316
CLG		 1530 /* Homer Xscom region */
1531 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1532
1533 /* Homer mmio region */
3887d241
B		 1534 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1535 &chip9->homer.regs);
4f9924c4
BH		 1536
1537 /* PHBs */
1538 pnv_chip_power9_phb_realize(chip, &local_err);
1539 if (local_err) {
1540 error_propagate(errp, local_err);
1541 return;
1542 }
e997040e
CLG		 1543}
1544
70c059e9
GK		 1545static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1546{
1547 addr &= (PNV9_XSCOM_SIZE - 1);
1548 return addr >> 3;
1549}
1550
e997040e
CLG		 1551static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1552{
1553 DeviceClass *dc = DEVICE_CLASS(klass);
1554 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1555
83028a2b 1556 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
397a79e7 1557 k->cores_mask = POWER9_CORE_MASK;
631adaff 1558 k->core_pir = pnv_chip_core_pir_p9;
d35aefa9 1559 k->intc_create = pnv_chip_power9_intc_create;
d49e8a9b 1560 k->intc_reset = pnv_chip_power9_intc_reset;
0990ce6a 1561 k->intc_destroy = pnv_chip_power9_intc_destroy;
85913070 1562 k->intc_print_info = pnv_chip_power9_intc_print_info;
04026890 1563 k->isa_create = pnv_chip_power9_isa_create;
eb859a27 1564 k->dt_populate = pnv_chip_power9_dt_populate;
d8e4aad5 1565 k->pic_print_info = pnv_chip_power9_pic_print_info;
c4b2c40c 1566 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
70c059e9 1567 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
e997040e 1568 dc->desc = "PowerNV Chip POWER9";
4f9924c4 1569 k->num_phbs = 6;
77864267
CLG		 1570
1571 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1572 &k->parent_realize);
e997040e
CLG		 1573}
1574
2b548a42
CLG		 1575static void pnv_chip_power10_instance_init(Object *obj)
1576{
8b50ce85
CLG		 1577 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1578
9fc7fc4d
MA		 1579 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1580 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
2b548a42
CLG		 1581}
1582
1583static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1584{
1585 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1586 PnvChip *chip = PNV_CHIP(dev);
8b50ce85 1587 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2b548a42
CLG		 1588 Error *local_err = NULL;
1589
1590 /* XSCOM bridge is first */
1591 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1592 if (local_err) {
1593 error_propagate(errp, local_err);
1594 return;
1595 }
1596 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1597
1598 pcc->parent_realize(dev, &local_err);
1599 if (local_err) {
1600 error_propagate(errp, local_err);
1601 return;
1602 }
8b50ce85
CLG		 1603
1604 /* Processor Service Interface (PSI) Host Bridge */
1605 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1606 "bar", &error_fatal);
1607 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1608 &local_err);
1609 if (local_err) {
1610 error_propagate(errp, local_err);
1611 return;
1612 }
1613 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1614 &PNV_PSI(&chip10->psi)->xscom_regs);
2661f6ab
CLG		 1615
1616 /* LPC */
1617 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1618 &error_abort);
1619 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1620 &local_err);
1621 if (local_err) {
1622 error_propagate(errp, local_err);
1623 return;
1624 }
1625 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1626 &chip10->lpc.xscom_regs);
1627
1628 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1629 (uint64_t) PNV10_LPCM_BASE(chip));
2b548a42
CLG		 1630}
1631
70c059e9
GK		 1632static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1633{
1634 addr &= (PNV10_XSCOM_SIZE - 1);
1635 return addr >> 3;
1636}
1637
2b548a42
CLG		 1638static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1639{
1640 DeviceClass *dc = DEVICE_CLASS(klass);
1641 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1642
2b548a42
CLG		 1643 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1644 k->cores_mask = POWER10_CORE_MASK;
1645 k->core_pir = pnv_chip_core_pir_p10;
1646 k->intc_create = pnv_chip_power10_intc_create;
1647 k->intc_reset = pnv_chip_power10_intc_reset;
1648 k->intc_destroy = pnv_chip_power10_intc_destroy;
85913070 1649 k->intc_print_info = pnv_chip_power10_intc_print_info;
2b548a42
CLG		 1650 k->isa_create = pnv_chip_power10_isa_create;
1651 k->dt_populate = pnv_chip_power10_dt_populate;
1652 k->pic_print_info = pnv_chip_power10_pic_print_info;
c4b2c40c 1653 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
70c059e9 1654 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
2b548a42
CLG		 1655 dc->desc = "PowerNV Chip POWER10";
1656
1657 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1658 &k->parent_realize);
1659}
1660
397a79e7
CLG		 1661static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1662{
1663 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1664 int cores_max;
1665
1666 /*
1667 * No custom mask for this chip, let's use the default one from *
1668 * the chip class
1669 */
1670 if (!chip->cores_mask) {
1671 chip->cores_mask = pcc->cores_mask;
1672 }
1673
1674 /* filter alien core ids ! some are reserved */
1675 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1676 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1677 chip->cores_mask);
1678 return;
1679 }
1680 chip->cores_mask &= pcc->cores_mask;
1681
1682 /* now that we have a sane layout, let check the number of cores */
27d9ffd4 1683 cores_max = ctpop64(chip->cores_mask);
397a79e7
CLG		 1684 if (chip->nr_cores > cores_max) {
1685 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1686 cores_max);
1687 return;
1688 }
1689}
1690
51c04728 1691static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
e997040e 1692{
397a79e7 1693 Error *error = NULL;
d2fd9612 1694 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
40abf43f 1695 const char *typename = pnv_chip_core_typename(chip);
d2fd9612 1696 int i, core_hwid;
08c3f3a7 1697 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
d2fd9612
CLG		 1698
1699 if (!object_class_by_name(typename)) {
1700 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1701 return;
1702 }
397a79e7 1703
d2fd9612 1704 /* Cores */
397a79e7
CLG		 1705 pnv_chip_core_sanitize(chip, &error);
1706 if (error) {
1707 error_propagate(errp, error);
1708 return;
1709 }
d2fd9612 1710
4fa28f23 1711 chip->cores = g_new0(PnvCore *, chip->nr_cores);
d2fd9612
CLG		 1712
1713 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1714 && (i < chip->nr_cores); core_hwid++) {
1715 char core_name[32];
4fa28f23 1716 PnvCore *pnv_core;
c035851a 1717 uint64_t xscom_core_base;
d2fd9612
CLG		 1718
1719 if (!(chip->cores_mask & (1ull << core_hwid))) {
1720 continue;
1721 }
1722
4fa28f23
GK		 1723 pnv_core = PNV_CORE(object_new(typename));
1724
d2fd9612 1725 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
d2623129 1726 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
4fa28f23 1727 chip->cores[i] = pnv_core;
764f9b25
GK		 1728 object_property_set_int(OBJECT(pnv_core), chip->nr_threads,
1729 "nr-threads", &error_fatal);
d2fd9612
CLG		 1730 object_property_set_int(OBJECT(pnv_core), core_hwid,
1731 CPU_CORE_PROP_CORE_ID, &error_fatal);
1732 object_property_set_int(OBJECT(pnv_core),
1733 pcc->core_pir(chip, core_hwid),
1734 "pir", &error_fatal);
08c3f3a7
CLG		 1735 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr,
1736 "hrmor", &error_fatal);
158e17a6
GK		 1737 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1738 &error_abort);
d2fd9612
CLG		 1739 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1740 &error_fatal);
24ece072
CLG		 1741
1742 /* Each core has an XSCOM MMIO region */
c4b2c40c 1743 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
c035851a
CLG		 1744
1745 pnv_xscom_add_subregion(chip, xscom_core_base,
4fa28f23 1746 &pnv_core->xscom_regs);
d2fd9612
CLG		 1747 i++;
1748 }
51c04728
CLG		 1749}
1750
1751static void pnv_chip_realize(DeviceState *dev, Error **errp)
1752{
1753 PnvChip *chip = PNV_CHIP(dev);
1754 Error *error = NULL;
1755
51c04728
CLG		 1756 /* Cores */
1757 pnv_chip_core_realize(chip, &error);
1758 if (error) {
1759 error_propagate(errp, error);
1760 return;
1761 }
e997040e
CLG		 1762}
1763
1764static Property pnv_chip_properties[] = {
1765 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1766 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1767 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
397a79e7
CLG		 1768 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1769 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
764f9b25 1770 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
4f9924c4 1771 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0),
e997040e
CLG		 1772 DEFINE_PROP_END_OF_LIST(),
1773};
1774
1775static void pnv_chip_class_init(ObjectClass *klass, void *data)
1776{
1777 DeviceClass *dc = DEVICE_CLASS(klass);
1778
9d169fb3 1779 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
e997040e 1780 dc->realize = pnv_chip_realize;
4f67d30b 1781 device_class_set_props(dc, pnv_chip_properties);
e997040e
CLG		 1782 dc->desc = "PowerNV Chip";
1783}
1784
119eaa9d
CLG		 1785PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1786{
1787 int i, j;
1788
1789 for (i = 0; i < chip->nr_cores; i++) {
1790 PnvCore *pc = chip->cores[i];
1791 CPUCore *cc = CPU_CORE(pc);
1792
1793 for (j = 0; j < cc->nr_threads; j++) {
1794 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1795 return pc->threads[j];
1796 }
1797 }
1798 }
1799 return NULL;
1800}
1801
54f59d78
CLG		 1802static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1803{
b168a138 1804 PnvMachineState *pnv = PNV_MACHINE(xi);
9ae1329e 1805 int i, j;
54f59d78
CLG		 1806
1807 for (i = 0; i < pnv->num_chips; i++) {
9ae1329e 1808 PnvChip *chip = pnv->chips[i];
77864267
CLG		 1809 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1810
1811 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1812 return &chip8->psi.ics;
54f59d78 1813 }
9ae1329e
CLG		 1814 for (j = 0; j < chip->num_phbs; j++) {
1815 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
1816 return &chip8->phbs[j].lsis;
1817 }
1818 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
1819 return ICS(&chip8->phbs[j].msis);
1820 }
1821 }
54f59d78
CLG		 1822 }
1823 return NULL;
1824}
1825
1826static void pnv_ics_resend(XICSFabric *xi)
1827{
b168a138 1828 PnvMachineState *pnv = PNV_MACHINE(xi);
9ae1329e 1829 int i, j;
54f59d78
CLG		 1830
1831 for (i = 0; i < pnv->num_chips; i++) {
9ae1329e 1832 PnvChip *chip = pnv->chips[i];
77864267 1833 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
9ae1329e 1834
77864267 1835 ics_resend(&chip8->psi.ics);
9ae1329e
CLG		 1836 for (j = 0; j < chip->num_phbs; j++) {
1837 ics_resend(&chip8->phbs[j].lsis);
1838 ics_resend(ICS(&chip8->phbs[j].msis));
1839 }
54f59d78
CLG		 1840 }
1841}
1842
36fc6f08
CLG		 1843static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1844{
1845 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1846
956b8f46 1847 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
36fc6f08
CLG		 1848}
1849
47fea43a
CLG		 1850static void pnv_pic_print_info(InterruptStatsProvider *obj,
1851 Monitor *mon)
1852{
b168a138 1853 PnvMachineState *pnv = PNV_MACHINE(obj);
54f59d78 1854 int i;
47fea43a
CLG		 1855 CPUState *cs;
1856
1857 CPU_FOREACH(cs) {
1858 PowerPCCPU *cpu = POWERPC_CPU(cs);
1859
85913070
GK		 1860 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1861 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1862 mon);
47fea43a 1863 }
54f59d78
CLG		 1864
1865 for (i = 0; i < pnv->num_chips; i++) {
d8e4aad5 1866 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
54f59d78 1867 }
47fea43a
CLG		 1868}
1869
c722579e
CLG		 1870static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1871 uint8_t nvt_blk, uint32_t nvt_idx,
1872 bool cam_ignore, uint8_t priority,
1873 uint32_t logic_serv,
1874 XiveTCTXMatch *match)
1875{
1876 PnvMachineState *pnv = PNV_MACHINE(xfb);
1877 int total_count = 0;
1878 int i;
1879
1880 for (i = 0; i < pnv->num_chips; i++) {
1881 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1882 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1883 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1884 int count;
1885
1886 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1887 priority, logic_serv, match);
1888
1889 if (count < 0) {
1890 return count;
1891 }
1892
1893 total_count += count;
1894 }
1895
1896 return total_count;
1897}
1898
f30c843c 1899static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
9e933f4a
BH		 1900{
1901 MachineClass *mc = MACHINE_CLASS(oc);
36fc6f08 1902 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
d76f2da7
GK		 1903 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1904 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
f30c843c
CLG		 1905
1906 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1907 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1908
1909 xic->icp_get = pnv_icp_get;
1910 xic->ics_get = pnv_ics_get;
1911 xic->ics_resend = pnv_ics_resend;
d76f2da7
GK		 1912
1913 pmc->compat = compat;
1914 pmc->compat_size = sizeof(compat);
f30c843c
CLG		 1915}
1916
1917static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1918{
1919 MachineClass *mc = MACHINE_CLASS(oc);
c722579e 1920 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
d76f2da7
GK		 1921 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1922 static const char compat[] = "qemu,powernv9\0ibm,powernv";
f30c843c
CLG		 1923
1924 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1925 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
c722579e 1926 xfc->match_nvt = pnv_match_nvt;
f30c843c
CLG		 1927
1928 mc->alias = "powernv";
d76f2da7
GK		 1929
1930 pmc->compat = compat;
1931 pmc->compat_size = sizeof(compat);
7a90c6a1 1932 pmc->dt_power_mgt = pnv_dt_power_mgt;
f30c843c
CLG		 1933}
1934
2b548a42
CLG		 1935static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1936{
1937 MachineClass *mc = MACHINE_CLASS(oc);
d76f2da7
GK		 1938 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1939 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2b548a42
CLG		 1940
1941 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1942 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
d76f2da7
GK		 1943
1944 pmc->compat = compat;
1945 pmc->compat_size = sizeof(compat);
7a90c6a1 1946 pmc->dt_power_mgt = pnv_dt_power_mgt;
2b548a42
CLG		 1947}
1948
08c3f3a7
CLG		 1949static bool pnv_machine_get_hb(Object *obj, Error **errp)
1950{
1951 PnvMachineState *pnv = PNV_MACHINE(obj);
1952
1953 return !!pnv->fw_load_addr;
1954}
1955
1956static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
1957{
1958 PnvMachineState *pnv = PNV_MACHINE(obj);
1959
1960 if (value) {
1961 pnv->fw_load_addr = 0x8000000;
1962 }
1963}
1964
01b552b0
NP		 1965static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
1966{
1967 PowerPCCPU *cpu = POWERPC_CPU(cs);
1968 CPUPPCState *env = &cpu->env;
1969
1970 cpu_synchronize_state(cs);
1971 ppc_cpu_do_system_reset(cs);
0911a60c 1972 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
fe837714
NP		 1973 /*
1974 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
1975 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
1976 * (PPC_BIT(43)).
1977 */
0911a60c 1978 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
fe837714 1979 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
0911a60c 1980 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
fe837714
NP		 1981 }
1982 } else {
1983 /*
1984 * For non-powersave system resets, SRR1[42:45] are defined to be
1985 * implementation-dependent. The POWER9 User Manual specifies that
1986 * an external (SCOM driven, which may come from a BMC nmi command or
1987 * another CPU requesting a NMI IPI) system reset exception should be
1988 * 0b0010 (PPC_BIT(44)).
1989 */
0911a60c 1990 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
fe837714 1991 }
01b552b0
NP		 1992}
1993
1994static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
1995{
1996 CPUState *cs;
1997
1998 CPU_FOREACH(cs) {
1999 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2000 }
2001}
2002
f30c843c
CLG		 2003static void pnv_machine_class_init(ObjectClass *oc, void *data)
2004{
2005 MachineClass *mc = MACHINE_CLASS(oc);
47fea43a 2006 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
01b552b0 2007 NMIClass *nc = NMI_CLASS(oc);
9e933f4a
BH		 2008
2009 mc->desc = "IBM PowerNV (Non-Virtualized)";
b168a138
CLG		 2010 mc->init = pnv_init;
2011 mc->reset = pnv_reset;
9e933f4a 2012 mc->max_cpus = MAX_CPUS;
59b7c1c2
B		 2013 /* Pnv provides a AHCI device for storage */
2014 mc->block_default_type = IF_IDE;
9e933f4a
BH		 2015 mc->no_parallel = 1;
2016 mc->default_boot_order = NULL;
f1d18b0a
JS		 2017 /*
2018 * RAM defaults to less than 2048 for 32-bit hosts, and large
2019 * enough to fit the maximum initrd size at it's load address
2020 */
2021 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
173a36d8 2022 mc->default_ram_id = "pnv.ram";
47fea43a 2023 ispc->print_info = pnv_pic_print_info;
01b552b0 2024 nc->nmi_monitor_handler = pnv_nmi;
08c3f3a7
CLG		 2025
2026 object_class_property_add_bool(oc, "hb-mode",
d2623129 2027 pnv_machine_get_hb, pnv_machine_set_hb);
08c3f3a7 2028 object_class_property_set_description(oc, "hb-mode",
7eecec7d 2029 "Use a hostboot like boot loader");
9e933f4a
BH		 2030}
2031
77864267
CLG		 2032#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2033 { \
2034 .name = type, \
2035 .class_init = class_initfn, \
2036 .parent = TYPE_PNV8_CHIP, \
2037 }
2038
2039#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2040 { \
2041 .name = type, \
2042 .class_init = class_initfn, \
2043 .parent = TYPE_PNV9_CHIP, \
beba5c0f
IM		 2044 }
2045
2b548a42
CLG		 2046#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2047 { \
2048 .name = type, \
2049 .class_init = class_initfn, \
2050 .parent = TYPE_PNV10_CHIP, \
2051 }
2052
beba5c0f 2053static const TypeInfo types[] = {
2b548a42
CLG		 2054 {
2055 .name = MACHINE_TYPE_NAME("powernv10"),
2056 .parent = TYPE_PNV_MACHINE,
2057 .class_init = pnv_machine_power10_class_init,
2058 },
1aba8716
CLG		 2059 {
2060 .name = MACHINE_TYPE_NAME("powernv9"),
2061 .parent = TYPE_PNV_MACHINE,
2062 .class_init = pnv_machine_power9_class_init,
c722579e
CLG		 2063 .interfaces = (InterfaceInfo[]) {
2064 { TYPE_XIVE_FABRIC },
2065 { },
2066 },
1aba8716
CLG		 2067 },
2068 {
2069 .name = MACHINE_TYPE_NAME("powernv8"),
2070 .parent = TYPE_PNV_MACHINE,
2071 .class_init = pnv_machine_power8_class_init,
2072 .interfaces = (InterfaceInfo[]) {
2073 { TYPE_XICS_FABRIC },
2074 { },
2075 },
2076 },
beba5c0f 2077 {
b168a138 2078 .name = TYPE_PNV_MACHINE,
beba5c0f 2079 .parent = TYPE_MACHINE,
f30c843c 2080 .abstract = true,
beba5c0f 2081 .instance_size = sizeof(PnvMachineState),
b168a138 2082 .class_init = pnv_machine_class_init,
d76f2da7 2083 .class_size = sizeof(PnvMachineClass),
beba5c0f 2084 .interfaces = (InterfaceInfo[]) {
beba5c0f 2085 { TYPE_INTERRUPT_STATS_PROVIDER },
01b552b0 2086 { TYPE_NMI },
beba5c0f
IM		 2087 { },
2088 },
36fc6f08 2089 },
beba5c0f
IM		 2090 {
2091 .name = TYPE_PNV_CHIP,
2092 .parent = TYPE_SYS_BUS_DEVICE,
2093 .class_init = pnv_chip_class_init,
beba5c0f
IM		 2094 .instance_size = sizeof(PnvChip),
2095 .class_size = sizeof(PnvChipClass),
2096 .abstract = true,
2097 },
77864267 2098
2b548a42
CLG		 2099 /*
2100 * P10 chip and variants
2101 */
2102 {
2103 .name = TYPE_PNV10_CHIP,
2104 .parent = TYPE_PNV_CHIP,
2105 .instance_init = pnv_chip_power10_instance_init,
2106 .instance_size = sizeof(Pnv10Chip),
2107 },
2108 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2109
77864267
CLG		 2110 /*
2111 * P9 chip and variants
2112 */
2113 {
2114 .name = TYPE_PNV9_CHIP,
2115 .parent = TYPE_PNV_CHIP,
2116 .instance_init = pnv_chip_power9_instance_init,
2117 .instance_size = sizeof(Pnv9Chip),
2118 },
2119 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2120
2121 /*
2122 * P8 chip and variants
2123 */
2124 {
2125 .name = TYPE_PNV8_CHIP,
2126 .parent = TYPE_PNV_CHIP,
2127 .instance_init = pnv_chip_power8_instance_init,
2128 .instance_size = sizeof(Pnv8Chip),
2129 },
2130 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2131 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2132 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2133 pnv_chip_power8nvl_class_init),
9e933f4a
BH		 2134};
2135
beba5c0f 2136DEFINE_TYPES(types)
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