]> git.ipfire.org Git - thirdparty/qemu.git/blame - hw/ppc/pnv_lpc.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Include hw/irq.h a lot less
[thirdparty/qemu.git] / hw / ppc / pnv_lpc.c
CommitLineData
a3980bf5
BH		 1/*
2 * QEMU PowerPC PowerNV LPC controller
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "sysemu/sysemu.h"
fcf5ef2a 22#include "target/ppc/cpu.h"
a3980bf5
BH		 23#include "qapi/error.h"
24#include "qemu/log.h"
0b8fa32f 25#include "qemu/module.h"
64552b6b 26#include "hw/irq.h"
04026890 27#include "hw/isa/isa.h"
a3980bf5 28
a3980bf5 29#include "hw/ppc/pnv.h"
ec575aa0
CLG		 30#include "hw/ppc/pnv_lpc.h"
31#include "hw/ppc/pnv_xscom.h"
a3980bf5
BH		 32#include "hw/ppc/fdt.h"
33
34#include <libfdt.h>
35
36enum {
37 ECCB_CTL = 0,
38 ECCB_RESET = 1,
39 ECCB_STAT = 2,
40 ECCB_DATA = 3,
41};
42
43/* OPB Master LS registers */
8207b906
CLG		 44#define OPB_MASTER_LS_ROUTE0 0x8
45#define OPB_MASTER_LS_ROUTE1 0xC
a3980bf5
BH		 46#define OPB_MASTER_LS_IRQ_STAT 0x50
47#define OPB_MASTER_IRQ_LPC 0x00000800
48#define OPB_MASTER_LS_IRQ_MASK 0x54
49#define OPB_MASTER_LS_IRQ_POL 0x58
50#define OPB_MASTER_LS_IRQ_INPUT 0x5c
51
52/* LPC HC registers */
53#define LPC_HC_FW_SEG_IDSEL 0x24
54#define LPC_HC_FW_RD_ACC_SIZE 0x28
55#define LPC_HC_FW_RD_1B 0x00000000
56#define LPC_HC_FW_RD_2B 0x01000000
57#define LPC_HC_FW_RD_4B 0x02000000
58#define LPC_HC_FW_RD_16B 0x04000000
59#define LPC_HC_FW_RD_128B 0x07000000
60#define LPC_HC_IRQSER_CTRL 0x30
61#define LPC_HC_IRQSER_EN 0x80000000
62#define LPC_HC_IRQSER_QMODE 0x40000000
63#define LPC_HC_IRQSER_START_MASK 0x03000000
64#define LPC_HC_IRQSER_START_4CLK 0x00000000
65#define LPC_HC_IRQSER_START_6CLK 0x01000000
66#define LPC_HC_IRQSER_START_8CLK 0x02000000
67#define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */
68#define LPC_HC_IRQSTAT 0x38
69#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */
70#define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
71#define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000
72#define LPC_HC_IRQ_LRESET 0x00000400
73#define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080
74#define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040
75#define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020
76#define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010
77#define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008
78#define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004
79#define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002
80#define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001
81#define LPC_HC_ERROR_ADDRESS 0x40
82
83#define LPC_OPB_SIZE 0x100000000ull
84
85#define ISA_IO_SIZE 0x00010000
86#define ISA_MEM_SIZE 0x10000000
d61c2857 87#define ISA_FW_SIZE 0x10000000
a3980bf5
BH		 88#define LPC_IO_OPB_ADDR 0xd0010000
89#define LPC_IO_OPB_SIZE 0x00010000
90#define LPC_MEM_OPB_ADDR 0xe0010000
91#define LPC_MEM_OPB_SIZE 0x10000000
92#define LPC_FW_OPB_ADDR 0xf0000000
93#define LPC_FW_OPB_SIZE 0x10000000
94
95#define LPC_OPB_REGS_OPB_ADDR 0xc0010000
6f89f48e
CLG		 96#define LPC_OPB_REGS_OPB_SIZE 0x00000060
97#define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
98#define LPC_OPB_REGS_OPBA_SIZE 0x00000008
a3980bf5 99#define LPC_HC_REGS_OPB_ADDR 0xc0012000
6f89f48e 100#define LPC_HC_REGS_OPB_SIZE 0x00000100
a3980bf5 101
b168a138 102static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
a3980bf5
BH		 103{
104 const char compat[] = "ibm,power8-lpc\0ibm,lpc";
105 char *name;
106 int offset;
107 uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
108 uint32_t reg[] = {
109 cpu_to_be32(lpc_pcba),
110 cpu_to_be32(PNV_XSCOM_LPC_SIZE)
111 };
112
113 name = g_strdup_printf("isa@%x", lpc_pcba);
114 offset = fdt_add_subnode(fdt, xscom_offset, name);
115 _FDT(offset);
116 g_free(name);
117
118 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
119 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
120 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
a3980bf5
BH		 121 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
122 return 0;
123}
124
15376c66
CLG		 125/* POWER9 only */
126int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
127{
128 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
129 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
130 char *name;
131 int offset, lpcm_offset;
132 uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
133 uint32_t opb_ranges[8] = { 0,
134 cpu_to_be32(lpcm_addr >> 32),
135 cpu_to_be32((uint32_t)lpcm_addr),
136 cpu_to_be32(PNV9_LPCM_SIZE / 2),
137 cpu_to_be32(PNV9_LPCM_SIZE / 2),
138 cpu_to_be32(lpcm_addr >> 32),
139 cpu_to_be32(PNV9_LPCM_SIZE / 2),
140 cpu_to_be32(PNV9_LPCM_SIZE / 2),
141 };
142 uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
143 cpu_to_be32((uint32_t)lpcm_addr),
144 cpu_to_be32(PNV9_LPCM_SIZE >> 32),
145 cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
146 };
147 uint32_t reg[2];
148
149 /*
150 * OPB bus
151 */
152 name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr);
153 lpcm_offset = fdt_add_subnode(fdt, root_offset, name);
154 _FDT(lpcm_offset);
155 g_free(name);
156
157 _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg))));
158 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1)));
159 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1)));
160 _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat))));
161 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id)));
162 _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges,
163 sizeof(opb_ranges))));
164
165 /*
166 * OPB Master registers
167 */
168 name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR);
169 offset = fdt_add_subnode(fdt, lpcm_offset, name);
170 _FDT(offset);
171 g_free(name);
172
173 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR);
174 reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE);
175 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
176 _FDT((fdt_setprop_string(fdt, offset, "compatible",
177 "ibm,power9-lpcm-opb-master")));
178
179 /*
180 * OPB arbitrer registers
181 */
182 name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR);
183 offset = fdt_add_subnode(fdt, lpcm_offset, name);
184 _FDT(offset);
185 g_free(name);
186
187 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR);
188 reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE);
189 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
190 _FDT((fdt_setprop_string(fdt, offset, "compatible",
191 "ibm,power9-lpcm-opb-arbiter")));
192
193 /*
194 * LPC Host Controller registers
195 */
196 name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR);
197 offset = fdt_add_subnode(fdt, lpcm_offset, name);
198 _FDT(offset);
199 g_free(name);
200
201 reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR);
202 reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE);
203 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
204 _FDT((fdt_setprop_string(fdt, offset, "compatible",
205 "ibm,power9-lpc-controller")));
206
207 name = g_strdup_printf("lpc@0");
208 offset = fdt_add_subnode(fdt, lpcm_offset, name);
209 _FDT(offset);
210 g_free(name);
211 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
212 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
213 _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
214 sizeof(lpc_compat))));
215
216 return 0;
217}
218
a3980bf5
BH		 219/*
220 * These read/write handlers of the OPB address space should be common
221 * with the P9 LPC Controller which uses direct MMIOs.
222 *
223 * TODO: rework to use address_space_stq() and address_space_ldq()
224 * instead.
225 */
226static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
227 int sz)
228{
a3980bf5 229 /* XXX Handle access size limits and FW read caching here */
4a4ff4c5
LV		 230 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
231 data, sz, false);
a3980bf5
BH		 232}
233
234static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
235 int sz)
236{
a3980bf5 237 /* XXX Handle access size limits here */
4a4ff4c5
LV		 238 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
239 data, sz, true);
a3980bf5
BH		 240}
241
a6a444a8 242#define ECCB_CTL_READ PPC_BIT(15)
a3980bf5 243#define ECCB_CTL_SZ_LSH (63 - 7)
a6a444a8
CLG		 244#define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
245#define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
a3980bf5 246
a6a444a8
CLG		 247#define ECCB_STAT_OP_DONE PPC_BIT(52)
248#define ECCB_STAT_OP_ERR PPC_BIT(52)
a3980bf5
BH		 249#define ECCB_STAT_RD_DATA_LSH (63 - 37)
250#define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH)
251
252static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
253{
254 /* XXX Check for magic bits at the top, addr size etc... */
255 unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
256 uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
d07945e7 257 uint8_t data[8];
a3980bf5
BH		 258 bool success;
259
d07945e7
PP		 260 if (sz > sizeof(data)) {
261 qemu_log_mask(LOG_GUEST_ERROR,
262 "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz);
263 return;
264 }
265
a3980bf5
BH		 266 if (cmd & ECCB_CTL_READ) {
267 success = opb_read(lpc, opb_addr, data, sz);
268 if (success) {
269 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
270 (((uint64_t)data[0]) << 24 |
271 ((uint64_t)data[1]) << 16 |
272 ((uint64_t)data[2]) << 8 |
273 ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
274 } else {
275 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
276 (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
277 }
278 } else {
279 data[0] = lpc->eccb_data_reg >> 24;
280 data[1] = lpc->eccb_data_reg >> 16;
281 data[2] = lpc->eccb_data_reg >> 8;
282 data[3] = lpc->eccb_data_reg;
283
284 success = opb_write(lpc, opb_addr, data, sz);
285 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
286 }
287 /* XXX Which error bit (if any) to signal OPB error ? */
288}
289
290static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
291{
292 PnvLpcController *lpc = PNV_LPC(opaque);
293 uint32_t offset = addr >> 3;
294 uint64_t val = 0;
295
296 switch (offset & 3) {
297 case ECCB_CTL:
298 case ECCB_RESET:
299 val = 0;
300 break;
301 case ECCB_STAT:
302 val = lpc->eccb_stat_reg;
303 lpc->eccb_stat_reg = 0;
304 break;
305 case ECCB_DATA:
306 val = ((uint64_t)lpc->eccb_data_reg) << 32;
307 break;
308 }
309 return val;
310}
311
312static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
313 uint64_t val, unsigned size)
314{
315 PnvLpcController *lpc = PNV_LPC(opaque);
316 uint32_t offset = addr >> 3;
317
318 switch (offset & 3) {
319 case ECCB_CTL:
320 pnv_lpc_do_eccb(lpc, val);
321 break;
322 case ECCB_RESET:
323 /* XXXX */
324 break;
325 case ECCB_STAT:
326 break;
327 case ECCB_DATA:
328 lpc->eccb_data_reg = val >> 32;
329 break;
330 }
331}
332
333static const MemoryRegionOps pnv_lpc_xscom_ops = {
334 .read = pnv_lpc_xscom_read,
335 .write = pnv_lpc_xscom_write,
336 .valid.min_access_size = 8,
337 .valid.max_access_size = 8,
338 .impl.min_access_size = 8,
339 .impl.max_access_size = 8,
340 .endianness = DEVICE_BIG_ENDIAN,
341};
342
15376c66
CLG		 343static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
344{
345 PnvLpcController *lpc = PNV_LPC(opaque);
346 uint64_t val = 0;
347 uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
348 MemTxResult result;
349
350 switch (size) {
351 case 4:
352 val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
353 &result);
354 break;
355 case 1:
356 val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED,
357 &result);
358 break;
359 default:
360 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
361 HWADDR_PRIx " invalid size %d\n", addr, size);
362 return 0;
363 }
364
365 if (result != MEMTX_OK) {
366 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
367 HWADDR_PRIx "\n", addr);
368 }
369
370 return val;
371}
372
373static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
374 uint64_t val, unsigned size)
375{
376 PnvLpcController *lpc = PNV_LPC(opaque);
377 uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
378 MemTxResult result;
379
380 switch (size) {
381 case 4:
382 address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
383 &result);
384 break;
385 case 1:
386 address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED,
387 &result);
388 break;
389 default:
390 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
391 HWADDR_PRIx " invalid size %d\n", addr, size);
392 return;
393 }
394
395 if (result != MEMTX_OK) {
396 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
397 HWADDR_PRIx "\n", addr);
398 }
399}
400
401static const MemoryRegionOps pnv_lpc_mmio_ops = {
402 .read = pnv_lpc_mmio_read,
403 .write = pnv_lpc_mmio_write,
404 .impl = {
405 .min_access_size = 1,
406 .max_access_size = 4,
407 },
408 .endianness = DEVICE_BIG_ENDIAN,
409};
410
4d1df88b
BH		 411static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
412{
413 bool lpc_to_opb_irq = false;
82514be2 414 PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
4d1df88b
BH		 415
416 /* Update LPC controller to OPB line */
417 if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
418 uint32_t irqs;
419
420 irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
421 lpc_to_opb_irq = (irqs != 0);
422 }
423
424 /* We don't honor the polarity register, it's pointless and unused
425 * anyway
426 */
427 if (lpc_to_opb_irq) {
428 lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
429 } else {
430 lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
431 }
432
433 /* Update OPB internal latch */
434 lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
435
436 /* Reflect the interrupt */
82514be2 437 pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
4d1df88b
BH		 438}
439
a3980bf5
BH		 440static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
441{
442 PnvLpcController *lpc = opaque;
443 uint64_t val = 0xfffffffffffffffful;
444
445 switch (addr) {
446 case LPC_HC_FW_SEG_IDSEL:
447 val = lpc->lpc_hc_fw_seg_idsel;
448 break;
449 case LPC_HC_FW_RD_ACC_SIZE:
450 val = lpc->lpc_hc_fw_rd_acc_size;
451 break;
452 case LPC_HC_IRQSER_CTRL:
453 val = lpc->lpc_hc_irqser_ctrl;
454 break;
455 case LPC_HC_IRQMASK:
456 val = lpc->lpc_hc_irqmask;
457 break;
458 case LPC_HC_IRQSTAT:
459 val = lpc->lpc_hc_irqstat;
460 break;
461 case LPC_HC_ERROR_ADDRESS:
462 val = lpc->lpc_hc_error_addr;
463 break;
464 default:
cdbaf8cd 465 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
a3980bf5
BH		 466 HWADDR_PRIx "\n", addr);
467 }
468 return val;
469}
470
471static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
472 unsigned size)
473{
474 PnvLpcController *lpc = opaque;
475
476 /* XXX Filter out reserved bits */
477
478 switch (addr) {
479 case LPC_HC_FW_SEG_IDSEL:
480 /* XXX Actually figure out how that works as this impact
481 * memory regions/aliases
482 */
483 lpc->lpc_hc_fw_seg_idsel = val;
484 break;
485 case LPC_HC_FW_RD_ACC_SIZE:
486 lpc->lpc_hc_fw_rd_acc_size = val;
487 break;
488 case LPC_HC_IRQSER_CTRL:
489 lpc->lpc_hc_irqser_ctrl = val;
4d1df88b 490 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 491 break;
492 case LPC_HC_IRQMASK:
493 lpc->lpc_hc_irqmask = val;
4d1df88b 494 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 495 break;
496 case LPC_HC_IRQSTAT:
497 lpc->lpc_hc_irqstat &= ~val;
4d1df88b 498 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 499 break;
500 case LPC_HC_ERROR_ADDRESS:
501 break;
502 default:
cdbaf8cd 503 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%"
a3980bf5
BH		 504 HWADDR_PRIx "\n", addr);
505 }
506}
507
508static const MemoryRegionOps lpc_hc_ops = {
509 .read = lpc_hc_read,
510 .write = lpc_hc_write,
511 .endianness = DEVICE_BIG_ENDIAN,
512 .valid = {
513 .min_access_size = 4,
514 .max_access_size = 4,
515 },
516 .impl = {
517 .min_access_size = 4,
518 .max_access_size = 4,
519 },
520};
521
522static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
523{
524 PnvLpcController *lpc = opaque;
525 uint64_t val = 0xfffffffffffffffful;
526
527 switch (addr) {
8207b906
CLG		 528 case OPB_MASTER_LS_ROUTE0: /* TODO */
529 val = lpc->opb_irq_route0;
530 break;
531 case OPB_MASTER_LS_ROUTE1: /* TODO */
532 val = lpc->opb_irq_route1;
533 break;
a3980bf5
BH		 534 case OPB_MASTER_LS_IRQ_STAT:
535 val = lpc->opb_irq_stat;
536 break;
537 case OPB_MASTER_LS_IRQ_MASK:
538 val = lpc->opb_irq_mask;
539 break;
540 case OPB_MASTER_LS_IRQ_POL:
541 val = lpc->opb_irq_pol;
542 break;
543 case OPB_MASTER_LS_IRQ_INPUT:
544 val = lpc->opb_irq_input;
545 break;
546 default:
cdbaf8cd 547 qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%"
a3980bf5
BH		 548 HWADDR_PRIx "\n", addr);
549 }
550
551 return val;
552}
553
554static void opb_master_write(void *opaque, hwaddr addr,
555 uint64_t val, unsigned size)
556{
557 PnvLpcController *lpc = opaque;
558
559 switch (addr) {
8207b906
CLG		 560 case OPB_MASTER_LS_ROUTE0: /* TODO */
561 lpc->opb_irq_route0 = val;
562 break;
563 case OPB_MASTER_LS_ROUTE1: /* TODO */
564 lpc->opb_irq_route1 = val;
565 break;
a3980bf5
BH		 566 case OPB_MASTER_LS_IRQ_STAT:
567 lpc->opb_irq_stat &= ~val;
4d1df88b 568 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 569 break;
570 case OPB_MASTER_LS_IRQ_MASK:
a3980bf5 571 lpc->opb_irq_mask = val;
4d1df88b 572 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 573 break;
574 case OPB_MASTER_LS_IRQ_POL:
a3980bf5 575 lpc->opb_irq_pol = val;
4d1df88b 576 pnv_lpc_eval_irqs(lpc);
a3980bf5
BH		 577 break;
578 case OPB_MASTER_LS_IRQ_INPUT:
579 /* Read only */
580 break;
581 default:
cdbaf8cd
CLG		 582 qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%"
583 HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val);
a3980bf5
BH		 584 }
585}
586
587static const MemoryRegionOps opb_master_ops = {
588 .read = opb_master_read,
589 .write = opb_master_write,
590 .endianness = DEVICE_BIG_ENDIAN,
591 .valid = {
592 .min_access_size = 4,
593 .max_access_size = 4,
594 },
595 .impl = {
596 .min_access_size = 4,
597 .max_access_size = 4,
598 },
599};
600
82514be2
CLG		 601static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp)
602{
603 PnvLpcController *lpc = PNV_LPC(dev);
604 PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
605 Error *local_err = NULL;
606
607 plc->parent_realize(dev, &local_err);
608 if (local_err) {
609 error_propagate(errp, local_err);
610 return;
611 }
612
613 /* P8 uses a XSCOM region for LPC registers */
614 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc),
615 &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
616 PNV_XSCOM_LPC_SIZE);
617}
618
619static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
620{
621 DeviceClass *dc = DEVICE_CLASS(klass);
622 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
623 PnvLpcClass *plc = PNV_LPC_CLASS(klass);
624
625 dc->desc = "PowerNV LPC Controller POWER8";
626
627 xdc->dt_xscom = pnv_lpc_dt_xscom;
628
629 plc->psi_irq = PSIHB_IRQ_LPC_I2C;
630
631 device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
632 &plc->parent_realize);
633}
634
635static const TypeInfo pnv_lpc_power8_info = {
636 .name = TYPE_PNV8_LPC,
637 .parent = TYPE_PNV_LPC,
638 .instance_size = sizeof(PnvLpcController),
639 .class_init = pnv_lpc_power8_class_init,
640 .interfaces = (InterfaceInfo[]) {
641 { TYPE_PNV_XSCOM_INTERFACE },
642 { }
643 }
644};
645
15376c66
CLG		 646static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
647{
648 PnvLpcController *lpc = PNV_LPC(dev);
649 PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
650 Error *local_err = NULL;
651
652 plc->parent_realize(dev, &local_err);
653 if (local_err) {
654 error_propagate(errp, local_err);
655 return;
656 }
657
658 /* P9 uses a MMIO region */
659 memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops,
660 lpc, "lpcm", PNV9_LPCM_SIZE);
661}
662
663static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
664{
665 DeviceClass *dc = DEVICE_CLASS(klass);
666 PnvLpcClass *plc = PNV_LPC_CLASS(klass);
667
668 dc->desc = "PowerNV LPC Controller POWER9";
669
670 plc->psi_irq = PSIHB9_IRQ_LPCHC;
671
672 device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
673 &plc->parent_realize);
674}
675
676static const TypeInfo pnv_lpc_power9_info = {
677 .name = TYPE_PNV9_LPC,
678 .parent = TYPE_PNV_LPC,
679 .instance_size = sizeof(PnvLpcController),
680 .class_init = pnv_lpc_power9_class_init,
681};
682
a3980bf5
BH		 683static void pnv_lpc_realize(DeviceState *dev, Error **errp)
684{
685 PnvLpcController *lpc = PNV_LPC(dev);
4d1df88b 686 Object *obj;
82514be2
CLG		 687 Error *local_err = NULL;
688
689 obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
690 if (!obj) {
691 error_propagate(errp, local_err);
692 error_prepend(errp, "required link 'psi' not found: ");
693 return;
694 }
695 /* The LPC controller needs PSI to generate interrupts */
696 lpc->psi = PNV_PSI(obj);
a3980bf5
BH		 697
698 /* Reg inits */
699 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
700
701 /* Create address space and backing MR for the OPB bus */
702 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
703 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
704
705 /* Create ISA IO and Mem space regions which are the root of
706 * the ISA bus (ie, ISA address spaces). We don't create a
707 * separate one for FW which we alias to memory.
708 */
709 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
710 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
d61c2857 711 memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE);
a3980bf5
BH		 712
713 /* Create windows from the OPB space to the ISA space */
714 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
715 &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
716 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
717 &lpc->opb_isa_io);
718 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
719 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
720 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
721 &lpc->opb_isa_mem);
722 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
d61c2857 723 &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
a3980bf5
BH		 724 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
725 &lpc->opb_isa_fw);
726
727 /* Create MMIO regions for LPC HC and OPB registers */
728 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
729 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
730 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
731 &lpc->opb_master_regs);
732 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
733 "lpc-hc", LPC_HC_REGS_OPB_SIZE);
734 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
735 &lpc->lpc_hc_regs);
a3980bf5
BH		 736}
737
738static void pnv_lpc_class_init(ObjectClass *klass, void *data)
739{
740 DeviceClass *dc = DEVICE_CLASS(klass);
a3980bf5
BH		 741
742 dc->realize = pnv_lpc_realize;
82514be2 743 dc->desc = "PowerNV LPC Controller";
a3980bf5
BH		 744}
745
746static const TypeInfo pnv_lpc_info = {
747 .name = TYPE_PNV_LPC,
748 .parent = TYPE_DEVICE,
a3980bf5 749 .class_init = pnv_lpc_class_init,
82514be2
CLG		 750 .class_size = sizeof(PnvLpcClass),
751 .abstract = true,
a3980bf5
BH		 752};
753
754static void pnv_lpc_register_types(void)
755{
756 type_register_static(&pnv_lpc_info);
82514be2 757 type_register_static(&pnv_lpc_power8_info);
15376c66 758 type_register_static(&pnv_lpc_power9_info);
a3980bf5
BH		 759}
760
761type_init(pnv_lpc_register_types)
4d1df88b
BH		 762
763/* If we don't use the built-in LPC interrupt deserializer, we need
764 * to provide a set of qirqs for the ISA bus or things will go bad.
765 *
766 * Most machines using pre-Naples chips (without said deserializer)
767 * have a CPLD that will collect the SerIRQ and shoot them as a
768 * single level interrupt to the P8 chip. So let's setup a hook
769 * for doing just that.
770 */
771static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
772{
b168a138 773 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
4d1df88b
BH		 774 uint32_t old_state = pnv->cpld_irqstate;
775 PnvLpcController *lpc = PNV_LPC(opaque);
776
777 if (level) {
778 pnv->cpld_irqstate |= 1u << n;
779 } else {
780 pnv->cpld_irqstate &= ~(1u << n);
781 }
782
783 if (pnv->cpld_irqstate != old_state) {
784 pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
785 }
786}
787
788static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
789{
790 PnvLpcController *lpc = PNV_LPC(opaque);
791
792 /* The Naples HW latches the 1 levels, clearing is done by SW */
793 if (level) {
794 lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
795 pnv_lpc_eval_irqs(lpc);
796 }
797}
798
04026890 799ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
4d1df88b 800{
04026890
CLG		 801 Error *local_err = NULL;
802 ISABus *isa_bus;
803 qemu_irq *irqs;
804 qemu_irq_handler handler;
805
806 /* let isa_bus_new() create its own bridge on SysBus otherwise
807 * devices speficied on the command line won't find the bus and
808 * will fail to create.
809 */
810 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
811 if (local_err) {
812 error_propagate(errp, local_err);
813 return NULL;
814 }
815
4d1df88b
BH		 816 /* Not all variants have a working serial irq decoder. If not,
817 * handling of LPC interrupts becomes a platform issue (some
818 * platforms have a CPLD to do it).
819 */
04026890
CLG		 820 if (use_cpld) {
821 handler = pnv_lpc_isa_irq_handler_cpld;
4d1df88b 822 } else {
04026890 823 handler = pnv_lpc_isa_irq_handler;
4d1df88b 824 }
04026890
CLG		 825
826 irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
827
828 isa_bus_irqs(isa_bus, irqs);
829 return isa_bus;
4d1df88b 830}
Mirror of https://git.qemu.org/git/qemu.git