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88a07990 MC |
1 | /* |
2 | * QEMU SiFive Test Finisher | |
3 | * | |
4 | * Copyright (c) 2018 SiFive, Inc. | |
5 | * | |
6 | * Test finisher memory mapped device used to exit simulation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2 or later, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "hw/sysbus.h" | |
0b8fa32f | 23 | #include "qemu/module.h" |
88a07990 | 24 | #include "target/riscv/cpu.h" |
650d103d | 25 | #include "hw/hw.h" |
88a07990 MC |
26 | #include "hw/riscv/sifive_test.h" |
27 | ||
28 | static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) | |
29 | { | |
30 | return 0; | |
31 | } | |
32 | ||
33 | static void sifive_test_write(void *opaque, hwaddr addr, | |
34 | uint64_t val64, unsigned int size) | |
35 | { | |
36 | if (addr == 0) { | |
37 | int status = val64 & 0xffff; | |
38 | int code = (val64 >> 16) & 0xffff; | |
39 | switch (status) { | |
40 | case FINISHER_FAIL: | |
41 | exit(code); | |
42 | case FINISHER_PASS: | |
43 | exit(0); | |
44 | default: | |
45 | break; | |
46 | } | |
47 | } | |
48 | hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", | |
49 | __func__, (int)addr, val64); | |
50 | } | |
51 | ||
52 | static const MemoryRegionOps sifive_test_ops = { | |
53 | .read = sifive_test_read, | |
54 | .write = sifive_test_write, | |
55 | .endianness = DEVICE_NATIVE_ENDIAN, | |
56 | .valid = { | |
57 | .min_access_size = 4, | |
58 | .max_access_size = 4 | |
59 | } | |
60 | }; | |
61 | ||
62 | static void sifive_test_init(Object *obj) | |
63 | { | |
64 | SiFiveTestState *s = SIFIVE_TEST(obj); | |
65 | ||
66 | memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s, | |
67 | TYPE_SIFIVE_TEST, 0x1000); | |
68 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | |
69 | } | |
70 | ||
71 | static const TypeInfo sifive_test_info = { | |
72 | .name = TYPE_SIFIVE_TEST, | |
73 | .parent = TYPE_SYS_BUS_DEVICE, | |
74 | .instance_size = sizeof(SiFiveTestState), | |
75 | .instance_init = sifive_test_init, | |
76 | }; | |
77 | ||
78 | static void sifive_test_register_types(void) | |
79 | { | |
80 | type_register_static(&sifive_test_info); | |
81 | } | |
82 | ||
83 | type_init(sifive_test_register_types) | |
84 | ||
85 | ||
86 | /* | |
87 | * Create Test device. | |
88 | */ | |
89 | DeviceState *sifive_test_create(hwaddr addr) | |
90 | { | |
91 | DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST); | |
92 | qdev_init_nofail(dev); | |
93 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); | |
94 | return dev; | |
95 | } |