]> git.ipfire.org Git - thirdparty/qemu.git/blame - hw/rtc/sun4v-rtc.c
Move QOM typedefs and add missing includes
[thirdparty/qemu.git] / hw / rtc / sun4v-rtc.c
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1/*
2 * QEMU sun4v Real Time Clock device
3 *
4 * The sun4v_rtc device (sun4v tod clock)
5 *
6 * Copyright (c) 2016 Artyom Tarasenko
7 *
8 * This code is licensed under the GNU GPL v3 or (at your option) any later
9 * version.
10 */
11
12#include "qemu/osdep.h"
a0e89303 13#include "hw/sysbus.h"
3e80f690 14#include "qapi/error.h"
0b8fa32f 15#include "qemu/module.h"
a0e89303 16#include "qemu/timer.h"
2811ac30 17#include "hw/rtc/sun4v-rtc.h"
252bfbde 18#include "trace.h"
db1015e9 19#include "qom/object.h"
a0e89303 20
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21
22#define TYPE_SUN4V_RTC "sun4v_rtc"
db1015e9 23typedef struct Sun4vRtc Sun4vRtc;
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24#define SUN4V_RTC(obj) OBJECT_CHECK(Sun4vRtc, (obj), TYPE_SUN4V_RTC)
25
db1015e9 26struct Sun4vRtc {
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27 SysBusDevice parent_obj;
28
29 MemoryRegion iomem;
db1015e9 30};
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31
32static uint64_t sun4v_rtc_read(void *opaque, hwaddr addr,
33 unsigned size)
34{
fff54d22 35 uint64_t val = get_clock_realtime() / NANOSECONDS_PER_SECOND;
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36 if (!(addr & 4ULL)) {
37 /* accessing the high 32 bits */
38 val >>= 32;
39 }
252bfbde 40 trace_sun4v_rtc_read(addr, val);
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41 return val;
42}
43
44static void sun4v_rtc_write(void *opaque, hwaddr addr,
45 uint64_t val, unsigned size)
46{
51809286 47 trace_sun4v_rtc_write(addr, val);
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48}
49
50static const MemoryRegionOps sun4v_rtc_ops = {
51 .read = sun4v_rtc_read,
52 .write = sun4v_rtc_write,
53 .endianness = DEVICE_NATIVE_ENDIAN,
54};
55
56void sun4v_rtc_init(hwaddr addr)
57{
58 DeviceState *dev;
59 SysBusDevice *s;
60
3e80f690 61 dev = qdev_new(TYPE_SUN4V_RTC);
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62 s = SYS_BUS_DEVICE(dev);
63
3c6ef471 64 sysbus_realize_and_unref(s, &error_fatal);
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65
66 sysbus_mmio_map(s, 0, addr);
67}
68
e871972e 69static void sun4v_rtc_realize(DeviceState *dev, Error **errp)
a0e89303 70{
e871972e 71 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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72 Sun4vRtc *s = SUN4V_RTC(dev);
73
74 memory_region_init_io(&s->iomem, OBJECT(s), &sun4v_rtc_ops, s,
75 "sun4v-rtc", 0x08ULL);
e871972e 76 sysbus_init_mmio(sbd, &s->iomem);
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77}
78
79static void sun4v_rtc_class_init(ObjectClass *klass, void *data)
80{
e871972e 81 DeviceClass *dc = DEVICE_CLASS(klass);
a0e89303 82
e871972e 83 dc->realize = sun4v_rtc_realize;
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84}
85
86static const TypeInfo sun4v_rtc_info = {
87 .name = TYPE_SUN4V_RTC,
88 .parent = TYPE_SYS_BUS_DEVICE,
89 .instance_size = sizeof(Sun4vRtc),
90 .class_init = sun4v_rtc_class_init,
91};
92
93static void sun4v_rtc_register_types(void)
94{
95 type_register_static(&sun4v_rtc_info);
96}
97
98type_init(sun4v_rtc_register_types)