[thirdparty/qemu.git] / hw / scsi / esp-pci.c

/*
 * QEMU ESP/NCR53C9x emulation
 *
 * Copyright (c) 2005-2006 Fabrice Bellard
 * Copyright (c) 2012 Herve Poussineau
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/pci/pci.h"
#include "hw/nvram/eeprom93xx.h"
#include "hw/scsi/esp.h"
#include "trace.h"
#include "qemu/log.h"

#define TYPE_AM53C974_DEVICE "am53c974"

#define PCI_ESP(obj) \
    OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)

#define DMA_CMD   0x0
#define DMA_STC   0x1
#define DMA_SPA   0x2
#define DMA_WBC   0x3
#define DMA_WAC   0x4
#define DMA_STAT  0x5
#define DMA_SMDLA 0x6
#define DMA_WMAC  0x7

#define DMA_CMD_MASK   0x03
#define DMA_CMD_DIAG   0x04
#define DMA_CMD_MDL    0x10
#define DMA_CMD_INTE_P 0x20
#define DMA_CMD_INTE_D 0x40
#define DMA_CMD_DIR    0x80

#define DMA_STAT_PWDN    0x01
#define DMA_STAT_ERROR   0x02
#define DMA_STAT_ABORT   0x04
#define DMA_STAT_DONE    0x08
#define DMA_STAT_SCSIINT 0x10
#define DMA_STAT_BCMBLT  0x20

#define SBAC_STATUS 0x1000

typedef struct PCIESPState {
    /*< private >*/
    PCIDevice parent_obj;
    /*< public >*/

    MemoryRegion io;
    uint32_t dma_regs[8];
    uint32_t sbac;
    ESPState esp;
} PCIESPState;

static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_idle(val);
    esp_dma_enable(&pci->esp, 0, 0);
}

static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_blast(val);
    qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
}

static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_abort(val);
    if (pci->esp.current_req) {
        scsi_req_cancel(pci->esp.current_req);
    }
}

static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
{
    trace_esp_pci_dma_start(val);

    pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
    pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
    pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];

    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
                               | DMA_STAT_DONE | DMA_STAT_ABORT
                               | DMA_STAT_ERROR | DMA_STAT_PWDN);

    esp_dma_enable(&pci->esp, 0, 1);
}

static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
{
    trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
    switch (saddr) {
    case DMA_CMD:
        pci->dma_regs[saddr] = val;
        switch (val & DMA_CMD_MASK) {
        case 0x0: /* IDLE */
            esp_pci_handle_idle(pci, val);
            break;
        case 0x1: /* BLAST */
            esp_pci_handle_blast(pci, val);
            break;
        case 0x2: /* ABORT */
            esp_pci_handle_abort(pci, val);
            break;
        case 0x3: /* START */
            esp_pci_handle_start(pci, val);
            break;
        default: /* can't happen */
            abort();
        }
        break;
    case DMA_STC:
    case DMA_SPA:
    case DMA_SMDLA:
        pci->dma_regs[saddr] = val;
        break;
    case DMA_STAT:
        if (!(pci->sbac & SBAC_STATUS)) {
            /* clear some bits on write */
            uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
            pci->dma_regs[DMA_STAT] &= ~(val & mask);
        }
        break;
    default:
        trace_esp_pci_error_invalid_write_dma(val, saddr);
        return;
    }
}

static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
{
    uint32_t val;

    val = pci->dma_regs[saddr];
    if (saddr == DMA_STAT) {
        if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
            val |= DMA_STAT_SCSIINT;
        }
        if (pci->sbac & SBAC_STATUS) {
            pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
                                         DMA_STAT_DONE);
        }
    }

    trace_esp_pci_dma_read(saddr, val);
    return val;
}

static void esp_pci_io_write(void *opaque, hwaddr addr,
                             uint64_t val, unsigned int size)
{
    PCIESPState *pci = opaque;

    if (size < 4 || addr & 3) {
        /* need to upgrade request: we only support 4-bytes accesses */
        uint32_t current = 0, mask;
        int shift;

        if (addr < 0x40) {
            current = pci->esp.wregs[addr >> 2];
        } else if (addr < 0x60) {
            current = pci->dma_regs[(addr - 0x40) >> 2];
        } else if (addr < 0x74) {
            current = pci->sbac;
        }

        shift = (4 - size) * 8;
        mask = (~(uint32_t)0 << shift) >> shift;

        shift = ((4 - (addr & 3)) & 3) * 8;
        val <<= shift;
        val |= current & ~(mask << shift);
        addr &= ~3;
        size = 4;
    }

    if (addr < 0x40) {
        /* SCSI core reg */
        esp_reg_write(&pci->esp, addr >> 2, val);
    } else if (addr < 0x60) {
        /* PCI DMA CCB */
        esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
    } else if (addr == 0x70) {
        /* DMA SCSI Bus and control */
        trace_esp_pci_sbac_write(pci->sbac, val);
        pci->sbac = val;
    } else {
        trace_esp_pci_error_invalid_write((int)addr);
    }
}

static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
                                unsigned int size)
{
    PCIESPState *pci = opaque;
    uint32_t ret;

    if (addr < 0x40) {
        /* SCSI core reg */
        ret = esp_reg_read(&pci->esp, addr >> 2);
    } else if (addr < 0x60) {
        /* PCI DMA CCB */
        ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
    } else if (addr == 0x70) {
        /* DMA SCSI Bus and control */
        trace_esp_pci_sbac_read(pci->sbac);
        ret = pci->sbac;
    } else {
        /* Invalid region */
        trace_esp_pci_error_invalid_read((int)addr);
        ret = 0;
    }

    /* give only requested data */
    ret >>= (addr & 3) * 8;
    ret &= ~(~(uint64_t)0 << (8 * size));

    return ret;
}

static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
                                  DMADirection dir)
{
    dma_addr_t addr;
    DMADirection expected_dir;

    if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
        expected_dir = DMA_DIRECTION_FROM_DEVICE;
    } else {
        expected_dir = DMA_DIRECTION_TO_DEVICE;
    }

    if (dir != expected_dir) {
        trace_esp_pci_error_invalid_dma_direction();
        return;
    }

    if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
        qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
    }

    addr = pci->dma_regs[DMA_SPA];
    if (pci->dma_regs[DMA_WBC] < len) {
        len = pci->dma_regs[DMA_WBC];
    }

    pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);

    /* update status registers */
    pci->dma_regs[DMA_WBC] -= len;
    pci->dma_regs[DMA_WAC] += len;
}

static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
{
    PCIESPState *pci = opaque;
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
}

static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
{
    PCIESPState *pci = opaque;
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
}

static const MemoryRegionOps esp_pci_io_ops = {
    .read = esp_pci_io_read,
    .write = esp_pci_io_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
};

static void esp_pci_hard_reset(DeviceState *dev)
{
    PCIESPState *pci = PCI_ESP(dev);
    esp_hard_reset(&pci->esp);
    pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
                              | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
    pci->dma_regs[DMA_WBC] &= ~0xffff;
    pci->dma_regs[DMA_WAC] = 0xffffffff;
    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
                               | DMA_STAT_DONE | DMA_STAT_ABORT
                               | DMA_STAT_ERROR);
    pci->dma_regs[DMA_WMAC] = 0xfffffffd;
}

static const VMStateDescription vmstate_esp_pci_scsi = {
    .name = "pciespscsi",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
        VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
        VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
        VMSTATE_END_OF_LIST()
    }
};

static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
                                     size_t resid)
{
    ESPState *s = req->hba_private;
    PCIESPState *pci = container_of(s, PCIESPState, esp);

    esp_command_complete(req, status, resid);
    pci->dma_regs[DMA_WBC] = 0;
    pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
}

static const struct SCSIBusInfo esp_pci_scsi_info = {
    .tcq = false,
    .max_target = ESP_MAX_DEVS,
    .max_lun = 7,

    .transfer_data = esp_transfer_data,
    .complete = esp_pci_command_complete,
    .cancel = esp_request_cancelled,
};

static int esp_pci_scsi_init(PCIDevice *dev)
{
    PCIESPState *pci = PCI_ESP(dev);
    DeviceState *d = DEVICE(dev);
    ESPState *s = &pci->esp;
    uint8_t *pci_conf;
    Error *err = NULL;

    pci_conf = dev->config;

    /* Interrupt pin A */
    pci_conf[PCI_INTERRUPT_PIN] = 0x01;

    s->dma_memory_read = esp_pci_dma_memory_read;
    s->dma_memory_write = esp_pci_dma_memory_write;
    s->dma_opaque = pci;
    s->chip_id = TCHI_AM53C974;
    memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
                          "esp-io", 0x80);

    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
    s->irq = dev->irq[0];

    scsi_bus_new(&s->bus, d, &esp_pci_scsi_info, NULL);
    if (!d->hotplugged) {
        scsi_bus_legacy_handle_cmdline(&s->bus, &err);
        if (err != NULL) {
            error_free(err);
            return -1;
        }
    }
    return 0;
}

static void esp_pci_scsi_uninit(PCIDevice *d)
{
    PCIESPState *pci = PCI_ESP(d);

    memory_region_destroy(&pci->io);
}

static void esp_pci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = esp_pci_scsi_init;
    k->exit = esp_pci_scsi_uninit;
    k->vendor_id = PCI_VENDOR_ID_AMD;
    k->device_id = PCI_DEVICE_ID_AMD_SCSI;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_STORAGE_SCSI;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
    dc->reset = esp_pci_hard_reset;
    dc->vmsd = &vmstate_esp_pci_scsi;
}

static const TypeInfo esp_pci_info = {
    .name = TYPE_AM53C974_DEVICE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIESPState),
    .class_init = esp_pci_class_init,
};

typedef struct {
    PCIESPState pci;
    eeprom_t *eeprom;
} DC390State;

#define TYPE_DC390_DEVICE "dc390"
#define DC390(obj) \
    OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)

#define EE_ADAPT_SCSI_ID 64
#define EE_MODE2         65
#define EE_DELAY         66
#define EE_TAG_CMD_NUM   67
#define EE_ADAPT_OPTIONS 68
#define EE_BOOT_SCSI_ID  69
#define EE_BOOT_SCSI_LUN 70
#define EE_CHKSUM1       126
#define EE_CHKSUM2       127

#define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
#define EE_ADAPT_OPTION_INT13           0x04
#define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08


static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
{
    DC390State *pci = DC390(dev);
    uint32_t val;

    val = pci_default_read_config(dev, addr, l);

    if (addr == 0x00 && l == 1) {
        /* First byte of address space is AND-ed with EEPROM DO line */
        if (!eeprom93xx_read(pci->eeprom)) {
            val &= ~0xff;
        }
    }

    return val;
}

static void dc390_write_config(PCIDevice *dev,
                               uint32_t addr, uint32_t val, int l)
{
    DC390State *pci = DC390(dev);
    if (addr == 0x80) {
        /* EEPROM write */
        int eesk = val & 0x80 ? 1 : 0;
        int eedi = val & 0x40 ? 1 : 0;
        eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
    } else if (addr == 0xc0) {
        /* EEPROM CS low */
        eeprom93xx_write(pci->eeprom, 0, 0, 0);
    } else {
        pci_default_write_config(dev, addr, val, l);
    }
}

static int dc390_scsi_init(PCIDevice *dev)
{
    DC390State *pci = DC390(dev);
    uint8_t *contents;
    uint16_t chksum = 0;
    int i, ret;

    /* init base class */
    ret = esp_pci_scsi_init(dev);
    if (ret < 0) {
        return ret;
    }

    /* EEPROM */
    pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);

    /* set default eeprom values */
    contents = (uint8_t *)eeprom93xx_data(pci->eeprom);

    for (i = 0; i < 16; i++) {
        contents[i * 2] = 0x57;
        contents[i * 2 + 1] = 0x00;
    }
    contents[EE_ADAPT_SCSI_ID] = 7;
    contents[EE_MODE2] = 0x0f;
    contents[EE_TAG_CMD_NUM] = 0x04;
    contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
                               | EE_ADAPT_OPTION_BOOT_FROM_CDROM
                               | EE_ADAPT_OPTION_INT13;

    /* update eeprom checksum */
    for (i = 0; i < EE_CHKSUM1; i += 2) {
        chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
    }
    chksum = 0x1234 - chksum;
    contents[EE_CHKSUM1] = chksum & 0xff;
    contents[EE_CHKSUM2] = chksum >> 8;

    return 0;
}

static void dc390_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = dc390_scsi_init;
    k->config_read = dc390_read_config;
    k->config_write = dc390_write_config;
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
    dc->desc = "Tekram DC-390 SCSI adapter";
}

static const TypeInfo dc390_info = {
    .name = "dc390",
    .parent = TYPE_AM53C974_DEVICE,
    .instance_size = sizeof(DC390State),
    .class_init = dc390_class_init,
};

static void esp_pci_register_types(void)
{
    type_register_static(&esp_pci_info);
    type_register_static(&dc390_info);
}

type_init(esp_pci_register_types)
Commit	Line	Data
aebcf56f HP	1	/*
	2	* QEMU ESP/NCR53C9x emulation
	3	*
	4	* Copyright (c) 2005-2006 Fabrice Bellard
	5	* Copyright (c) 2012 Herve Poussineau
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
83c9f4ca	26	#include "hw/pci/pci.h"
0d09e41a PB	27	#include "hw/nvram/eeprom93xx.h"
0d09e41a PB	28	#include "hw/scsi/esp.h"
aebcf56f	29	#include "trace.h"
1de7afc9	30	#include "qemu/log.h"
aebcf56f	31
cea936b1 HP	32	#define TYPE_AM53C974_DEVICE "am53c974"
cea936b1 HP	33
3a15effe PC	34	#define PCI_ESP(obj) \
	35	OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
	36
aebcf56f HP	37	#define DMA_CMD 0x0
	38	#define DMA_STC 0x1
	39	#define DMA_SPA 0x2
	40	#define DMA_WBC 0x3
	41	#define DMA_WAC 0x4
	42	#define DMA_STAT 0x5
	43	#define DMA_SMDLA 0x6
	44	#define DMA_WMAC 0x7
	45
	46	#define DMA_CMD_MASK 0x03
	47	#define DMA_CMD_DIAG 0x04
	48	#define DMA_CMD_MDL 0x10
	49	#define DMA_CMD_INTE_P 0x20
	50	#define DMA_CMD_INTE_D 0x40
	51	#define DMA_CMD_DIR 0x80
	52
	53	#define DMA_STAT_PWDN 0x01
	54	#define DMA_STAT_ERROR 0x02
	55	#define DMA_STAT_ABORT 0x04
	56	#define DMA_STAT_DONE 0x08
	57	#define DMA_STAT_SCSIINT 0x10
	58	#define DMA_STAT_BCMBLT 0x20
	59
	60	#define SBAC_STATUS 0x1000
	61
	62	typedef struct PCIESPState {
4e5dcc77 AF	63	/< private >/
	64	PCIDevice parent_obj;
	65	/< public >/
	66
aebcf56f HP	67	MemoryRegion io;
	68	uint32_t dma_regs[8];
	69	uint32_t sbac;
	70	ESPState esp;
	71	} PCIESPState;
	72
	73	static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
	74	{
	75	trace_esp_pci_dma_idle(val);
	76	esp_dma_enable(&pci->esp, 0, 0);
	77	}
	78
	79	static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
	80	{
	81	trace_esp_pci_dma_blast(val);
	82	qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
	83	}
	84
	85	static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
	86	{
	87	trace_esp_pci_dma_abort(val);
	88	if (pci->esp.current_req) {
	89	scsi_req_cancel(pci->esp.current_req);
	90	}
	91	}
	92
	93	static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
	94	{
	95	trace_esp_pci_dma_start(val);
	96
	97	pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
	98	pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
	99	pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
	100
	101	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT \| DMA_STAT_SCSIINT
	102	\| DMA_STAT_DONE \| DMA_STAT_ABORT
	103	\| DMA_STAT_ERROR \| DMA_STAT_PWDN);
	104
	105	esp_dma_enable(&pci->esp, 0, 1);
	106	}
	107
	108	static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
	109	{
	110	trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
	111	switch (saddr) {
	112	case DMA_CMD:
	113	pci->dma_regs[saddr] = val;
	114	switch (val & DMA_CMD_MASK) {
	115	case 0x0: /* IDLE */
	116	esp_pci_handle_idle(pci, val);
	117	break;
	118	case 0x1: /* BLAST */
	119	esp_pci_handle_blast(pci, val);
	120	break;
	121	case 0x2: /* ABORT */
	122	esp_pci_handle_abort(pci, val);
	123	break;
	124	case 0x3: /* START */
	125	esp_pci_handle_start(pci, val);
	126	break;
	127	default: /* can't happen */
	128	abort();
	129	}
	130	break;
131	case DMA_STC:
132	case DMA_SPA:
133	case DMA_SMDLA:
134	pci->dma_regs[saddr] = val;
135	break;
136	case DMA_STAT:
137	if (!(pci->sbac & SBAC_STATUS)) {
138	/* clear some bits on write */
139	uint32_t mask = DMA_STAT_ERROR \| DMA_STAT_ABORT \| DMA_STAT_DONE;
140	pci->dma_regs[DMA_STAT] &= ~(val & mask);
141	}
142	break;
143	default:
144	trace_esp_pci_error_invalid_write_dma(val, saddr);
145	return;
146	}
147	}
148
149	static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
150	{
151	uint32_t val;
152
153	val = pci->dma_regs[saddr];
154	if (saddr == DMA_STAT) {
155	if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
156	val \|= DMA_STAT_SCSIINT;
157	}
158	if (pci->sbac & SBAC_STATUS) {
159	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR \| DMA_STAT_ABORT \|
160	DMA_STAT_DONE);
161	}
162	}
163
164	trace_esp_pci_dma_read(saddr, val);
165	return val;
166	}
167
a8170e5e	168	static void esp_pci_io_write(void *opaque, hwaddr addr,
aebcf56f HP	169	uint64_t val, unsigned int size)
	170	{
	171	PCIESPState *pci = opaque;
	172
	173	if (size < 4 \|\| addr & 3) {
	174	/* need to upgrade request: we only support 4-bytes accesses */
	175	uint32_t current = 0, mask;
	176	int shift;
	177
	178	if (addr < 0x40) {
	179	current = pci->esp.wregs[addr >> 2];
	180	} else if (addr < 0x60) {
	181	current = pci->dma_regs[(addr - 0x40) >> 2];
	182	} else if (addr < 0x74) {
	183	current = pci->sbac;
	184	}
	185
	186	shift = (4 - size) * 8;
	187	mask = (~(uint32_t)0 << shift) >> shift;
	188
	189	shift = ((4 - (addr & 3)) & 3) * 8;
	190	val <<= shift;
	191	val \|= current & ~(mask << shift);
	192	addr &= ~3;
	193	size = 4;
	194	}
	195
	196	if (addr < 0x40) {
	197	/* SCSI core reg */
	198	esp_reg_write(&pci->esp, addr >> 2, val);
	199	} else if (addr < 0x60) {
	200	/* PCI DMA CCB */
	201	esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
	202	} else if (addr == 0x70) {
	203	/* DMA SCSI Bus and control */
	204	trace_esp_pci_sbac_write(pci->sbac, val);
	205	pci->sbac = val;
	206	} else {
	207	trace_esp_pci_error_invalid_write((int)addr);
	208	}
	209	}
	210
a8170e5e	211	static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
aebcf56f HP	212	unsigned int size)
	213	{
	214	PCIESPState *pci = opaque;
	215	uint32_t ret;
	216
	217	if (addr < 0x40) {
	218	/* SCSI core reg */
	219	ret = esp_reg_read(&pci->esp, addr >> 2);
	220	} else if (addr < 0x60) {
	221	/* PCI DMA CCB */
	222	ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
	223	} else if (addr == 0x70) {
	224	/* DMA SCSI Bus and control */
	225	trace_esp_pci_sbac_read(pci->sbac);
	226	ret = pci->sbac;
	227	} else {
	228	/* Invalid region */
	229	trace_esp_pci_error_invalid_read((int)addr);
	230	ret = 0;
	231	}
	232
	233	/* give only requested data */
	234	ret >>= (addr & 3) * 8;
	235	ret &= ~(~(uint64_t)0 << (8 * size));
	236
	237	return ret;
	238	}
	239
	240	static void esp_pci_dma_memory_rw(PCIESPState pci, uint8_t buf, int len,
	241	DMADirection dir)
	242	{
	243	dma_addr_t addr;
	244	DMADirection expected_dir;
	245
	246	if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
	247	expected_dir = DMA_DIRECTION_FROM_DEVICE;
	248	} else {
	249	expected_dir = DMA_DIRECTION_TO_DEVICE;
	250	}
	251
	252	if (dir != expected_dir) {
	253	trace_esp_pci_error_invalid_dma_direction();
	254	return;
	255	}
	256
	257	if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
	258	qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
	259	}
	260
	261	addr = pci->dma_regs[DMA_SPA];
	262	if (pci->dma_regs[DMA_WBC] < len) {
	263	len = pci->dma_regs[DMA_WBC];
	264	}
	265
4e5dcc77	266	pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
aebcf56f HP	267
	268	/* update status registers */
	269	pci->dma_regs[DMA_WBC] -= len;
	270	pci->dma_regs[DMA_WAC] += len;
	271	}
	272
	273	static void esp_pci_dma_memory_read(void opaque, uint8_t buf, int len)
	274	{
	275	PCIESPState *pci = opaque;
	276	esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
	277	}
	278
	279	static void esp_pci_dma_memory_write(void opaque, uint8_t buf, int len)
	280	{
	281	PCIESPState *pci = opaque;
	282	esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
	283	}
	284
	285	static const MemoryRegionOps esp_pci_io_ops = {
	286	.read = esp_pci_io_read,
	287	.write = esp_pci_io_write,
	288	.endianness = DEVICE_LITTLE_ENDIAN,
	289	.impl = {
	290	.min_access_size = 1,
	291	.max_access_size = 4,
	292	},
	293	};
	294
	295	static void esp_pci_hard_reset(DeviceState *dev)
	296	{
3a15effe	297	PCIESPState *pci = PCI_ESP(dev);
aebcf56f HP	298	esp_hard_reset(&pci->esp);
	299	pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR \| DMA_CMD_INTE_D \| DMA_CMD_INTE_P
	300	\| DMA_CMD_MDL \| DMA_CMD_DIAG \| DMA_CMD_MASK);
	301	pci->dma_regs[DMA_WBC] &= ~0xffff;
	302	pci->dma_regs[DMA_WAC] = 0xffffffff;
	303	pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT \| DMA_STAT_SCSIINT
	304	\| DMA_STAT_DONE \| DMA_STAT_ABORT
	305	\| DMA_STAT_ERROR);
	306	pci->dma_regs[DMA_WMAC] = 0xfffffffd;
	307	}
	308
	309	static const VMStateDescription vmstate_esp_pci_scsi = {
	310	.name = "pciespscsi",
	311	.version_id = 0,
	312	.minimum_version_id = 0,
	313	.minimum_version_id_old = 0,
	314	.fields = (VMStateField[]) {
4e5dcc77	315	VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
aebcf56f HP	316	VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
	317	VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
	318	VMSTATE_END_OF_LIST()
	319	}
	320	};
	321
	322	static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
	323	size_t resid)
	324	{
	325	ESPState *s = req->hba_private;
	326	PCIESPState *pci = container_of(s, PCIESPState, esp);
	327
	328	esp_command_complete(req, status, resid);
	329	pci->dma_regs[DMA_WBC] = 0;
	330	pci->dma_regs[DMA_STAT] \|= DMA_STAT_DONE;
	331	}
	332
	333	static const struct SCSIBusInfo esp_pci_scsi_info = {
	334	.tcq = false,
	335	.max_target = ESP_MAX_DEVS,
	336	.max_lun = 7,
	337
	338	.transfer_data = esp_transfer_data,
	339	.complete = esp_pci_command_complete,
	340	.cancel = esp_request_cancelled,
	341	};
	342
	343	static int esp_pci_scsi_init(PCIDevice *dev)
	344	{
3a15effe PC	345	PCIESPState *pci = PCI_ESP(dev);
3a15effe PC	346	DeviceState *d = DEVICE(dev);
aebcf56f HP	347	ESPState *s = &pci->esp;
aebcf56f HP	348	uint8_t *pci_conf;
caad4eb3	349	Error *err = NULL;
aebcf56f	350
4e5dcc77	351	pci_conf = dev->config;
aebcf56f HP	352
	353	/* Interrupt pin A */
	354	pci_conf[PCI_INTERRUPT_PIN] = 0x01;
	355
	356	s->dma_memory_read = esp_pci_dma_memory_read;
	357	s->dma_memory_write = esp_pci_dma_memory_write;
	358	s->dma_opaque = pci;
	359	s->chip_id = TCHI_AM53C974;
29776739 PB	360	memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
29776739 PB	361	"esp-io", 0x80);
aebcf56f	362
4e5dcc77 AF	363	pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
4e5dcc77 AF	364	s->irq = dev->irq[0];
aebcf56f	365
3a15effe PC	366	scsi_bus_new(&s->bus, d, &esp_pci_scsi_info, NULL);
3a15effe PC	367	if (!d->hotplugged) {
caad4eb3 AF	368	scsi_bus_legacy_handle_cmdline(&s->bus, &err);
	369	if (err != NULL) {
	370	error_free(err);
	371	return -1;
	372	}
aebcf56f HP	373	}
	374	return 0;
	375	}
	376
	377	static void esp_pci_scsi_uninit(PCIDevice *d)
	378	{
3a15effe	379	PCIESPState *pci = PCI_ESP(d);
aebcf56f HP	380
	381	memory_region_destroy(&pci->io);
	382	}
	383
	384	static void esp_pci_class_init(ObjectClass klass, void data)
	385	{
	386	DeviceClass *dc = DEVICE_CLASS(klass);
	387	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	388
	389	k->init = esp_pci_scsi_init;
	390	k->exit = esp_pci_scsi_uninit;
	391	k->vendor_id = PCI_VENDOR_ID_AMD;
	392	k->device_id = PCI_DEVICE_ID_AMD_SCSI;
	393	k->revision = 0x10;
	394	k->class_id = PCI_CLASS_STORAGE_SCSI;
125ee0ed	395	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
aebcf56f HP	396	dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
	397	dc->reset = esp_pci_hard_reset;
	398	dc->vmsd = &vmstate_esp_pci_scsi;
	399	}
	400
	401	static const TypeInfo esp_pci_info = {
cea936b1	402	.name = TYPE_AM53C974_DEVICE,
aebcf56f HP	403	.parent = TYPE_PCI_DEVICE,
	404	.instance_size = sizeof(PCIESPState),
	405	.class_init = esp_pci_class_init,
	406	};
	407
cea936b1 HP	408	typedef struct {
	409	PCIESPState pci;
	410	eeprom_t *eeprom;
	411	} DC390State;
	412
	413	#define TYPE_DC390_DEVICE "dc390"
	414	#define DC390(obj) \
	415	OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
	416
	417	#define EE_ADAPT_SCSI_ID 64
	418	#define EE_MODE2 65
	419	#define EE_DELAY 66
	420	#define EE_TAG_CMD_NUM 67
	421	#define EE_ADAPT_OPTIONS 68
	422	#define EE_BOOT_SCSI_ID 69
	423	#define EE_BOOT_SCSI_LUN 70
	424	#define EE_CHKSUM1 126
	425	#define EE_CHKSUM2 127
	426
	427	#define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
	428	#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
	429	#define EE_ADAPT_OPTION_INT13 0x04
	430	#define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
	431
	432
	433	static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
	434	{
	435	DC390State *pci = DC390(dev);
	436	uint32_t val;
	437
	438	val = pci_default_read_config(dev, addr, l);
	439
	440	if (addr == 0x00 && l == 1) {
	441	/* First byte of address space is AND-ed with EEPROM DO line */
	442	if (!eeprom93xx_read(pci->eeprom)) {
	443	val &= ~0xff;
	444	}
	445	}
	446
	447	return val;
	448	}
	449
	450	static void dc390_write_config(PCIDevice *dev,
	451	uint32_t addr, uint32_t val, int l)
	452	{
	453	DC390State *pci = DC390(dev);
	454	if (addr == 0x80) {
	455	/* EEPROM write */
	456	int eesk = val & 0x80 ? 1 : 0;
	457	int eedi = val & 0x40 ? 1 : 0;
	458	eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
	459	} else if (addr == 0xc0) {
	460	/* EEPROM CS low */
	461	eeprom93xx_write(pci->eeprom, 0, 0, 0);
	462	} else {
	463	pci_default_write_config(dev, addr, val, l);
	464	}
	465	}
	466
	467	static int dc390_scsi_init(PCIDevice *dev)
	468	{
	469	DC390State *pci = DC390(dev);
	470	uint8_t *contents;
	471	uint16_t chksum = 0;
472	int i, ret;
473
474	/* init base class */
475	ret = esp_pci_scsi_init(dev);
476	if (ret < 0) {
477	return ret;
478	}
479
480	/* EEPROM */
481	pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
482
483	/* set default eeprom values */
484	contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
485
486	for (i = 0; i < 16; i++) {
487	contents[i * 2] = 0x57;
488	contents[i * 2 + 1] = 0x00;
489	}
490	contents[EE_ADAPT_SCSI_ID] = 7;
491	contents[EE_MODE2] = 0x0f;
492	contents[EE_TAG_CMD_NUM] = 0x04;
493	contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
494	\| EE_ADAPT_OPTION_BOOT_FROM_CDROM
495	\| EE_ADAPT_OPTION_INT13;
496
497	/* update eeprom checksum */
498	for (i = 0; i < EE_CHKSUM1; i += 2) {
499	chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
500	}
501	chksum = 0x1234 - chksum;
502	contents[EE_CHKSUM1] = chksum & 0xff;
503	contents[EE_CHKSUM2] = chksum >> 8;
504
505	return 0;
506	}
507
508	static void dc390_class_init(ObjectClass klass, void data)
509	{
510	DeviceClass *dc = DEVICE_CLASS(klass);
511	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
512
513	k->init = dc390_scsi_init;
514	k->config_read = dc390_read_config;
515	k->config_write = dc390_write_config;
125ee0ed	516	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
cea936b1 HP	517	dc->desc = "Tekram DC-390 SCSI adapter";
	518	}
	519
	520	static const TypeInfo dc390_info = {
	521	.name = "dc390",
	522	.parent = TYPE_AM53C974_DEVICE,
	523	.instance_size = sizeof(DC390State),
	524	.class_init = dc390_class_init,
	525	};
	526
aebcf56f HP	527	static void esp_pci_register_types(void)
	528	{
	529	type_register_static(&esp_pci_info);
cea936b1	530	type_register_static(&dc390_info);
aebcf56f HP	531	}
	532
	533	type_init(esp_pci_register_types)