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Move QOM typedefs and add missing includes
[thirdparty/qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a4ab4792 21#include "qemu/osdep.h"
a8d25326 22#include "qemu-common.h"
83c9f4ca 23#include "hw/pci/pci.h"
a27bd6c7 24#include "hw/qdev-properties.h"
9c17d615 25#include "sysemu/dma.h"
4be74634 26#include "sysemu/block-backend.h"
4522b69c 27#include "hw/pci/msi.h"
83c9f4ca 28#include "hw/pci/msix.h"
1de7afc9 29#include "qemu/iov.h"
0b8fa32f 30#include "qemu/module.h"
0d09e41a 31#include "hw/scsi/scsi.h"
08e2c9f1 32#include "scsi/constants.h"
e8f943c3 33#include "trace.h"
1108b2f8 34#include "qapi/error.h"
47b43a1f 35#include "mfi.h"
d6454270 36#include "migration/vmstate.h"
db1015e9 37#include "qom/object.h"
e8f943c3 38
e23d0498
HR		 39#define MEGASAS_VERSION_GEN1 "1.70"
40#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 41#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
42#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 43#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 44#define MEGASAS_MAX_SGE 128 /* Firmware limit */
45#define MEGASAS_DEFAULT_SGE 80
46#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
47#define MEGASAS_MAX_ARRAYS 128
48
fb654157 49#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 50#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
51#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
52
e8f943c3
HR		 53#define MEGASAS_FLAG_USE_JBOD 0
54#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
b4b4a57f 55#define MEGASAS_FLAG_USE_QUEUE64 1
e8f943c3
HR		 56#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
57
e8f943c3
HR		 58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
a8170e5e
AK		 64 hwaddr pa;
65 hwaddr pa_size;
5104fac8 66 uint32_t dcmd_opcode;
e8f943c3
HR		 67 union mfi_frame *frame;
68 SCSIRequest *req;
69 QEMUSGList qsg;
70 void *iov_buf;
71 size_t iov_size;
72 size_t iov_offset;
73 struct MegasasState *state;
74} MegasasCmd;
75
db1015e9 76struct MegasasState {
52190c1e
AF		 77 /*< private >*/
78 PCIDevice parent_obj;
79 /*< public >*/
80
e8f943c3
HR		 81 MemoryRegion mmio_io;
82 MemoryRegion port_io;
83 MemoryRegion queue_io;
84 uint32_t frame_hi;
85
2b151297 86 uint32_t fw_state;
e8f943c3
HR		 87 uint32_t fw_sge;
88 uint32_t fw_cmds;
89 uint32_t flags;
2b151297
PP		 90 uint32_t fw_luns;
91 uint32_t intr_mask;
92 uint32_t doorbell;
93 uint32_t busy;
94 uint32_t diag;
95 uint32_t adp_reset;
b4b4a57f
C		 96 OnOffAuto msi;
97 OnOffAuto msix;
e8f943c3
HR		 98
99 MegasasCmd *event_cmd;
2b151297 100 uint16_t event_locale;
e8f943c3 101 int event_class;
2b151297
PP		 102 uint32_t event_count;
103 uint32_t shutdown_event;
104 uint32_t boot_event;
e8f943c3 105
76b523db 106 uint64_t sas_addr;
fb654157 107 char *hba_serial;
76b523db 108
e8f943c3
HR		 109 uint64_t reply_queue_pa;
110 void *reply_queue;
2b151297 111 uint16_t reply_queue_len;
f50ab86a 112 uint16_t reply_queue_head;
2b151297 113 uint16_t reply_queue_tail;
e8f943c3
HR		 114 uint64_t consumer_pa;
115 uint64_t producer_pa;
116
117 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3 119 SCSIBus bus;
db1015e9
EH		 120};
121typedef struct MegasasState MegasasState;
e8f943c3 122
db1015e9 123struct MegasasBaseClass {
e23d0498
HR		 124 PCIDeviceClass parent_class;
125 const char *product_name;
126 const char *product_version;
127 int mmio_bar;
128 int ioport_bar;
129 int osts;
db1015e9
EH		 130};
131typedef struct MegasasBaseClass MegasasBaseClass;
e23d0498
HR		 132
133#define TYPE_MEGASAS_BASE "megasas-base"
134#define TYPE_MEGASAS_GEN1 "megasas"
135#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 136
137#define MEGASAS(obj) \
e23d0498
HR		 138 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
139
2e0aec15 140#define MEGASAS_CLASS(oc) \
e23d0498 141 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
2e0aec15 142#define MEGASAS_GET_CLASS(oc) \
e23d0498 143 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 144
e8f943c3
HR		 145#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
146
147static bool megasas_intr_enabled(MegasasState *s)
148{
149 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
150 MEGASAS_INTR_DISABLED_MASK) {
151 return true;
152 }
153 return false;
154}
155
156static bool megasas_use_queue64(MegasasState *s)
157{
158 return s->flags & MEGASAS_MASK_USE_QUEUE64;
159}
160
161static bool megasas_use_msix(MegasasState *s)
162{
b4b4a57f 163 return s->msix != ON_OFF_AUTO_OFF;
e8f943c3
HR		 164}
165
166static bool megasas_is_jbod(MegasasState *s)
167{
168 return s->flags & MEGASAS_MASK_USE_JBOD;
169}
170
16578c6f
PB		 171static void megasas_frame_set_cmd_status(MegasasState *s,
172 unsigned long frame, uint8_t v)
e8f943c3 173{
16578c6f
PB		 174 PCIDevice *pci = &s->parent_obj;
175 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 176}
177
16578c6f
PB		 178static void megasas_frame_set_scsi_status(MegasasState *s,
179 unsigned long frame, uint8_t v)
e8f943c3 180{
16578c6f
PB		 181 PCIDevice *pci = &s->parent_obj;
182 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 183}
184
ee760ac8
TH		 185static inline const char *mfi_frame_desc(unsigned int cmd)
186{
187 static const char *mfi_frame_descs[] = {
188 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
189 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"
190 };
191
192 if (cmd < ARRAY_SIZE(mfi_frame_descs)) {
193 return mfi_frame_descs[cmd];
194 }
195
196 return "Unknown";
197}
198
e8f943c3
HR		 199/*
200 * Context is considered opaque, but the HBA firmware is running
201 * in little endian mode. So convert it to little endian, too.
202 */
16578c6f
PB		 203static uint64_t megasas_frame_get_context(MegasasState *s,
204 unsigned long frame)
e8f943c3 205{
16578c6f
PB		 206 PCIDevice *pci = &s->parent_obj;
207 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 208}
209
210static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
211{
212 return cmd->flags & MFI_FRAME_IEEE_SGL;
213}
214
215static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
216{
217 return cmd->flags & MFI_FRAME_SGL64;
218}
219
220static bool megasas_frame_is_sense64(MegasasCmd *cmd)
221{
222 return cmd->flags & MFI_FRAME_SENSE64;
223}
224
225static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
226 union mfi_sgl *sgl)
227{
228 uint64_t addr;
229
230 if (megasas_frame_is_ieee_sgl(cmd)) {
231 addr = le64_to_cpu(sgl->sg_skinny->addr);
232 } else if (megasas_frame_is_sgl64(cmd)) {
233 addr = le64_to_cpu(sgl->sg64->addr);
234 } else {
235 addr = le32_to_cpu(sgl->sg32->addr);
236 }
237 return addr;
238}
239
240static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
241 union mfi_sgl *sgl)
242{
243 uint32_t len;
244
245 if (megasas_frame_is_ieee_sgl(cmd)) {
246 len = le32_to_cpu(sgl->sg_skinny->len);
247 } else if (megasas_frame_is_sgl64(cmd)) {
248 len = le32_to_cpu(sgl->sg64->len);
249 } else {
250 len = le32_to_cpu(sgl->sg32->len);
251 }
252 return len;
253}
254
255static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
256 union mfi_sgl *sgl)
257{
258 uint8_t *next = (uint8_t *)sgl;
259
260 if (megasas_frame_is_ieee_sgl(cmd)) {
261 next += sizeof(struct mfi_sg_skinny);
262 } else if (megasas_frame_is_sgl64(cmd)) {
263 next += sizeof(struct mfi_sg64);
264 } else {
265 next += sizeof(struct mfi_sg32);
266 }
267
268 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
269 return NULL;
270 }
271 return (union mfi_sgl *)next;
272}
273
274static void megasas_soft_reset(MegasasState *s);
275
276static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
277{
278 int i;
279 int iov_count = 0;
280 size_t iov_size = 0;
281
282 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
283 iov_count = cmd->frame->header.sge_count;
284 if (iov_count > MEGASAS_MAX_SGE) {
285 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
286 MEGASAS_MAX_SGE);
287 return iov_count;
288 }
52190c1e 289 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 290 for (i = 0; i < iov_count; i++) {
291 dma_addr_t iov_pa, iov_size_p;
292
293 if (!sgl) {
294 trace_megasas_iovec_sgl_underflow(cmd->index, i);
295 goto unmap;
296 }
297 iov_pa = megasas_sgl_get_addr(cmd, sgl);
298 iov_size_p = megasas_sgl_get_len(cmd, sgl);
299 if (!iov_pa || !iov_size_p) {
300 trace_megasas_iovec_sgl_invalid(cmd->index, i,
301 iov_pa, iov_size_p);
302 goto unmap;
303 }
304 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
305 sgl = megasas_sgl_next(cmd, sgl);
306 iov_size += (size_t)iov_size_p;
307 }
308 if (cmd->iov_size > iov_size) {
309 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
310 } else if (cmd->iov_size < iov_size) {
d17e7448 311 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
e8f943c3
HR		 312 }
313 cmd->iov_offset = 0;
314 return 0;
315unmap:
316 qemu_sglist_destroy(&cmd->qsg);
317 return iov_count - i;
318}
319
e8f943c3
HR		 320/*
321 * passthrough sense and io sense are at the same offset
322 */
323static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
324 uint8_t sense_len)
325{
1016b239 326 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 327 uint32_t pa_hi = 0, pa_lo;
a8170e5e 328 hwaddr pa;
134550bf 329 int frame_sense_len;
e8f943c3 330
134550bf
PB		 331 frame_sense_len = cmd->frame->header.sense_len;
332 if (sense_len > frame_sense_len) {
333 sense_len = frame_sense_len;
e8f943c3
HR		 334 }
335 if (sense_len) {
336 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
337 if (megasas_frame_is_sense64(cmd)) {
338 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
339 }
340 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 341 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 342 cmd->frame->header.sense_len = sense_len;
343 }
344 return sense_len;
345}
346
347static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
348{
349 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
350 uint8_t sense_len = 18;
351
352 memset(sense_buf, 0, sense_len);
353 sense_buf[0] = 0xf0;
354 sense_buf[2] = sense.key;
355 sense_buf[7] = 10;
356 sense_buf[12] = sense.asc;
357 sense_buf[13] = sense.ascq;
358 megasas_build_sense(cmd, sense_buf, sense_len);
359}
360
361static void megasas_copy_sense(MegasasCmd *cmd)
362{
363 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
364 uint8_t sense_len;
365
366 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
367 SCSI_SENSE_BUF_SIZE);
368 megasas_build_sense(cmd, sense_buf, sense_len);
369}
370
371/*
372 * Format an INQUIRY CDB
373 */
374static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
375{
376 memset(cdb, 0, 6);
377 cdb[0] = INQUIRY;
378 if (pg > 0) {
379 cdb[1] = 0x1;
380 cdb[2] = pg;
381 }
382 cdb[3] = (len >> 8) & 0xff;
383 cdb[4] = (len & 0xff);
384 return len;
385}
386
387/*
388 * Encode lba and len into a READ_16/WRITE_16 CDB
389 */
390static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
391 uint32_t len, bool is_write)
392{
393 memset(cdb, 0x0, 16);
394 if (is_write) {
395 cdb[0] = WRITE_16;
396 } else {
397 cdb[0] = READ_16;
398 }
399 cdb[2] = (lba >> 56) & 0xff;
400 cdb[3] = (lba >> 48) & 0xff;
401 cdb[4] = (lba >> 40) & 0xff;
402 cdb[5] = (lba >> 32) & 0xff;
403 cdb[6] = (lba >> 24) & 0xff;
404 cdb[7] = (lba >> 16) & 0xff;
405 cdb[8] = (lba >> 8) & 0xff;
406 cdb[9] = (lba) & 0xff;
407 cdb[10] = (len >> 24) & 0xff;
408 cdb[11] = (len >> 16) & 0xff;
409 cdb[12] = (len >> 8) & 0xff;
410 cdb[13] = (len) & 0xff;
411}
412
413/*
414 * Utility functions
415 */
416static uint64_t megasas_fw_time(void)
417{
418 struct tm curtime;
e8f943c3
HR		 419
420 qemu_get_timedate(&curtime, 0);
9be38598 421 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
e8f943c3
HR		 422 ((uint64_t)curtime.tm_min & 0xff) << 40 |
423 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
424 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
425 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
426 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
e8f943c3
HR		 427}
428
76b523db
HR		 429/*
430 * Default disk sata address
431 * 0x1221 is the magic number as
432 * present in real hardware,
433 * so use it here, too.
434 */
435static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 436{
76b523db 437 uint64_t addr = (0x1221ULL << 48);
8ef2eb8d 438 return addr | ((uint64_t)id << 24);
e8f943c3
HR		 439}
440
441/*
442 * Frame handling
443 */
444static int megasas_next_index(MegasasState *s, int index, int limit)
445{
446 index++;
447 if (index == limit) {
448 index = 0;
449 }
450 return index;
451}
452
453static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 454 hwaddr frame)
e8f943c3
HR		 455{
456 MegasasCmd *cmd = NULL;
457 int num = 0, index;
458
459 index = s->reply_queue_head;
460
f50ab86a 461 while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) {
e8f943c3
HR		 462 if (s->frames[index].pa && s->frames[index].pa == frame) {
463 cmd = &s->frames[index];
464 break;
465 }
466 index = megasas_next_index(s, index, s->fw_cmds);
467 num++;
468 }
469
470 return cmd;
471}
472
6df5718b 473static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 474{
6df5718b 475 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 476
75f19f8c
PB		 477 if (cmd->pa_size) {
478 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
479 }
6df5718b
HR		 480 cmd->frame = NULL;
481 cmd->pa = 0;
75f19f8c 482 cmd->pa_size = 0;
48285ba2 483 qemu_sglist_destroy(&cmd->qsg);
6df5718b 484 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 485}
486
6df5718b
HR		 487/*
488 * This absolutely needs to be locked if
489 * qemu ever goes multithreaded.
490 */
e8f943c3 491static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 492 hwaddr frame, uint64_t context, int count)
e8f943c3 493{
1016b239 494 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 495 MegasasCmd *cmd = NULL;
2e56fbc8 496 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
a8170e5e 497 hwaddr frame_size_p = frame_size;
6df5718b 498 unsigned long index;
e8f943c3 499
6df5718b
HR		 500 index = 0;
501 while (index < s->fw_cmds) {
502 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
503 if (!s->frames[index].pa)
504 break;
505 /* Busy frame found */
506 trace_megasas_qf_mapped(index);
507 }
508 if (index >= s->fw_cmds) {
509 /* All frames busy */
510 trace_megasas_qf_busy(frame);
e8f943c3
HR		 511 return NULL;
512 }
6df5718b
HR		 513 cmd = &s->frames[index];
514 set_bit(index, s->frame_map);
515 trace_megasas_qf_new(index, frame);
516
517 cmd->pa = frame;
518 /* Map all possible frames */
519 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
fd691855 520 if (!cmd->frame || frame_size_p != frame_size) {
6df5718b
HR		 521 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
522 if (cmd->frame) {
523 megasas_unmap_frame(s, cmd);
e8f943c3 524 }
6df5718b
HR		 525 s->event_count++;
526 return NULL;
527 }
528 cmd->pa_size = frame_size_p;
529 cmd->context = context;
530 if (!megasas_use_queue64(s)) {
531 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 532 }
533 cmd->count = count;
5104fac8 534 cmd->dcmd_opcode = -1;
e8f943c3
HR		 535 s->busy++;
536
aaf2a859 537 if (s->consumer_pa) {
16578c6f 538 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
aaf2a859 539 }
e8f943c3 540 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 541 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 542
543 return cmd;
544}
545
546static void megasas_complete_frame(MegasasState *s, uint64_t context)
547{
52190c1e 548 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 549 int tail, queue_offset;
550
551 /* Decrement busy count */
552 s->busy--;
e8f943c3
HR		 553 if (s->reply_queue_pa) {
554 /*
555 * Put command on the reply queue.
556 * Context is opaque, but emulation is running in
557 * little endian. So convert it.
558 */
e8f943c3 559 if (megasas_use_queue64(s)) {
7957ee71 560 queue_offset = s->reply_queue_head * sizeof(uint64_t);
16578c6f 561 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 562 } else {
7957ee71 563 queue_offset = s->reply_queue_head * sizeof(uint32_t);
16578c6f 564 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 565 }
16578c6f 566 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
aaf2a859 567 trace_megasas_qf_complete(context, s->reply_queue_head,
7957ee71 568 s->reply_queue_tail, s->busy);
e8f943c3
HR		 569 }
570
571 if (megasas_intr_enabled(s)) {
7957ee71 572 /* Update reply queue pointer */
16578c6f 573 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
7957ee71
HR		 574 tail = s->reply_queue_head;
575 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
576 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
577 s->busy);
16578c6f 578 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
e8f943c3 579 /* Notify HBA */
7957ee71
HR		 580 if (msix_enabled(pci_dev)) {
581 trace_megasas_msix_raise(0);
582 msix_notify(pci_dev, 0);
583 } else if (msi_enabled(pci_dev)) {
584 trace_megasas_msi_raise(0);
585 msi_notify(pci_dev, 0);
586 } else {
587 s->doorbell++;
588 if (s->doorbell == 1) {
e8f943c3 589 trace_megasas_irq_raise();
9e64f8a3 590 pci_irq_assert(pci_dev);
e8f943c3
HR		 591 }
592 }
593 } else {
594 trace_megasas_qf_complete_noirq(context);
595 }
596}
597
9e55d588
PB		 598static void megasas_complete_command(MegasasCmd *cmd)
599{
9e55d588
PB		 600 cmd->iov_size = 0;
601 cmd->iov_offset = 0;
602
603 cmd->req->hba_private = NULL;
604 scsi_req_unref(cmd->req);
605 cmd->req = NULL;
606
607 megasas_unmap_frame(cmd->state, cmd);
608 megasas_complete_frame(cmd->state, cmd->context);
609}
610
e8f943c3
HR		 611static void megasas_reset_frames(MegasasState *s)
612{
613 int i;
614 MegasasCmd *cmd;
615
616 for (i = 0; i < s->fw_cmds; i++) {
617 cmd = &s->frames[i];
618 if (cmd->pa) {
6df5718b 619 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 620 }
621 }
6df5718b 622 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 623}
624
625static void megasas_abort_command(MegasasCmd *cmd)
626{
9e55d588 627 /* Never abort internal commands. */
87e459a8
PB		 628 if (cmd->dcmd_opcode != -1) {
629 return;
630 }
9e55d588 631 if (cmd->req != NULL) {
e2b06058 632 scsi_req_cancel(cmd->req);
e8f943c3
HR		 633 }
634}
635
636static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
637{
1016b239 638 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 639 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 640 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
641 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 642 uint32_t flags;
643 int ret = MFI_STAT_OK;
644
96f8f23a
HR		 645 if (s->reply_queue_pa) {
646 trace_megasas_initq_mapped(s->reply_queue_pa);
647 goto out;
648 }
e8f943c3
HR		 649 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
650 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
651 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
652 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 653 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 654 if (!initq || initq_size != sizeof(*initq)) {
655 trace_megasas_initq_map_failed(cmd->index);
656 s->event_count++;
657 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
658 goto out;
659 }
660 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
661 if (s->reply_queue_len > s->fw_cmds) {
662 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
663 s->event_count++;
664 ret = MFI_STAT_INVALID_PARAMETER;
665 goto out;
666 }
667 pa_lo = le32_to_cpu(initq->rq_addr_lo);
668 pa_hi = le32_to_cpu(initq->rq_addr_hi);
669 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
670 pa_lo = le32_to_cpu(initq->ci_addr_lo);
671 pa_hi = le32_to_cpu(initq->ci_addr_hi);
672 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
673 pa_lo = le32_to_cpu(initq->pi_addr_lo);
674 pa_hi = le32_to_cpu(initq->pi_addr_hi);
675 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
16578c6f 676 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
b60bdd1f 677 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
16578c6f 678 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
b60bdd1f 679 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
e8f943c3
HR		 680 flags = le32_to_cpu(initq->flags);
681 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
682 s->flags |= MEGASAS_MASK_USE_QUEUE64;
683 }
684 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
685 s->reply_queue_len, s->reply_queue_head,
686 s->reply_queue_tail, flags);
687 megasas_reset_frames(s);
688 s->fw_state = MFI_FWSTATE_OPERATIONAL;
689out:
690 if (initq) {
1016b239 691 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 692 }
693 return ret;
694}
695
696static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
697{
698 dma_addr_t iov_pa, iov_size;
24c0c77a 699 int iov_count;
e8f943c3
HR		 700
701 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
24c0c77a
PB		 702 iov_count = cmd->frame->header.sge_count;
703 if (!iov_count) {
e8f943c3
HR		 704 trace_megasas_dcmd_zero_sge(cmd->index);
705 cmd->iov_size = 0;
706 return 0;
24c0c77a
PB		 707 } else if (iov_count > 1) {
708 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
e8f943c3 709 cmd->iov_size = 0;
765a7070 710 return -EINVAL;
e8f943c3
HR		 711 }
712 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
713 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 714 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 715 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
716 cmd->iov_size = iov_size;
765a7070 717 return 0;
e8f943c3
HR		 718}
719
720static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
721{
722 trace_megasas_finish_dcmd(cmd->index, iov_size);
723
e8f943c3
HR		 724 if (iov_size > cmd->iov_size) {
725 if (megasas_frame_is_ieee_sgl(cmd)) {
726 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
727 } else if (megasas_frame_is_sgl64(cmd)) {
728 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
729 } else {
730 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
731 }
732 }
e8f943c3
HR		 733}
734
735static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
736{
52190c1e 737 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498 738 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
2e0aec15 739 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
e8f943c3
HR		 740 struct mfi_ctrl_info info;
741 size_t dcmd_size = sizeof(info);
742 BusChild *kid;
3f2cd4dd 743 int num_pd_disks = 0;
e8f943c3 744
36fef36b 745 memset(&info, 0x0, dcmd_size);
e8f943c3
HR		 746 if (cmd->iov_size < dcmd_size) {
747 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
748 dcmd_size);
749 return MFI_STAT_INVALID_PARAMETER;
750 }
751
e23d0498
HR		 752 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
753 info.pci.device = cpu_to_le16(pci_class->device_id);
754 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
755 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 756
76b523db
HR		 757 /*
758 * For some reason the firmware supports
759 * only up to 8 device ports.
760 * Despite supporting a far larger number
761 * of devices for the physical devices.
762 * So just display the first 8 devices
763 * in the device port list, independent
764 * of how many logical devices are actually
765 * present.
766 */
767 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 768 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 769 info.device.port_count = 8;
770 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 771 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 772 uint16_t pd_id;
76b523db 773
3f2cd4dd
HR		 774 if (num_pd_disks < 8) {
775 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
776 info.device.port_addr[num_pd_disks] =
777 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 778 }
3f2cd4dd 779 num_pd_disks++;
76b523db 780 }
e8f943c3 781
e23d0498 782 memcpy(info.product_name, base_class->product_name, 24);
fb654157 783 snprintf(info.serial_number, 32, "%s", s->hba_serial);
69fbd0ea 784 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
e8f943c3 785 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 786 snprintf(info.image_component[0].version, 10, "%s-QEMU",
787 base_class->product_version);
5a7733b0
OH		 788 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
789 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 790 info.image_component_count = 1;
52190c1e 791 if (pci_dev->has_rom) {
e8f943c3
HR		 792 uint8_t biosver[32];
793 uint8_t *ptr;
794
52190c1e 795 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 796 memcpy(biosver, ptr + 0x41, 31);
844864fb 797 biosver[31] = 0;
e8f943c3
HR		 798 memcpy(info.image_component[1].name, "BIOS", 4);
799 memcpy(info.image_component[1].version, biosver,
800 strlen((const char *)biosver));
801 info.image_component_count++;
802 }
803 info.current_fw_time = cpu_to_le32(megasas_fw_time());
804 info.max_arms = 32;
805 info.max_spans = 8;
806 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 807 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 808 info.max_cmds = cpu_to_le16(s->fw_cmds);
809 info.max_sg_elements = cpu_to_le16(s->fw_sge);
810 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 811 if (!megasas_is_jbod(s))
812 info.lds_present = cpu_to_le16(num_pd_disks);
813 info.pd_present = cpu_to_le16(num_pd_disks);
814 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 815 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
816 MFI_INFO_HW_MEM |
817 MFI_INFO_HW_FLASH);
818 info.memory_size = cpu_to_le16(512);
819 info.nvram_size = cpu_to_le16(32);
820 info.flash_size = cpu_to_le16(16);
821 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
822 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
823 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
824 MFI_INFO_AOPS_MIXED_ARRAY);
825 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
826 MFI_INFO_LDOPS_ACCESS_POLICY |
827 MFI_INFO_LDOPS_IO_POLICY |
828 MFI_INFO_LDOPS_WRITE_POLICY |
829 MFI_INFO_LDOPS_READ_POLICY);
830 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
831 info.stripe_sz_ops.min = 3;
786a4ea8 832 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
e8f943c3
HR		 833 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
834 info.properties.intr_throttle_cnt = cpu_to_le16(16);
835 info.properties.intr_throttle_timeout = cpu_to_le16(50);
836 info.properties.rebuild_rate = 30;
837 info.properties.patrol_read_rate = 30;
838 info.properties.bgi_rate = 30;
839 info.properties.cc_rate = 30;
840 info.properties.recon_rate = 30;
841 info.properties.cache_flush_interval = 4;
842 info.properties.spinup_drv_cnt = 2;
843 info.properties.spinup_delay = 6;
844 info.properties.ecc_bucket_size = 15;
845 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
846 info.properties.expose_encl_devices = 1;
847 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
848 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
849 MFI_INFO_PDOPS_FORCE_OFFLINE);
850 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
851 MFI_INFO_PDMIX_SATA |
852 MFI_INFO_PDMIX_LD);
853
854 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
855 return MFI_STAT_OK;
856}
857
858static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
859{
860 struct mfi_defaults info;
861 size_t dcmd_size = sizeof(struct mfi_defaults);
862
863 memset(&info, 0x0, dcmd_size);
864 if (cmd->iov_size < dcmd_size) {
865 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
866 dcmd_size);
867 return MFI_STAT_INVALID_PARAMETER;
868 }
869
76b523db 870 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 871 info.stripe_size = 3;
872 info.flush_time = 4;
873 info.background_rate = 30;
874 info.allow_mix_in_enclosure = 1;
875 info.allow_mix_in_ld = 1;
876 info.direct_pd_mapping = 1;
877 /* Enable for BIOS support */
878 info.bios_enumerate_lds = 1;
879 info.disable_ctrl_r = 1;
880 info.expose_enclosure_devices = 1;
881 info.disable_preboot_cli = 1;
882 info.cluster_disable = 1;
883
884 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
885 return MFI_STAT_OK;
886}
887
888static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
889{
890 struct mfi_bios_data info;
891 size_t dcmd_size = sizeof(info);
892
893 memset(&info, 0x0, dcmd_size);
894 if (cmd->iov_size < dcmd_size) {
895 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
896 dcmd_size);
897 return MFI_STAT_INVALID_PARAMETER;
898 }
899 info.continue_on_error = 1;
900 info.verbose = 1;
901 if (megasas_is_jbod(s)) {
902 info.expose_all_drives = 1;
903 }
904
905 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
906 return MFI_STAT_OK;
907}
908
909static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
910{
911 uint64_t fw_time;
912 size_t dcmd_size = sizeof(fw_time);
913
914 fw_time = cpu_to_le64(megasas_fw_time());
915
916 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
917 return MFI_STAT_OK;
918}
919
920static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
921{
922 uint64_t fw_time;
923
924 /* This is a dummy; setting of firmware time is not allowed */
925 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
926
927 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
928 fw_time = cpu_to_le64(megasas_fw_time());
929 return MFI_STAT_OK;
930}
931
932static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
933{
934 struct mfi_evt_log_state info;
935 size_t dcmd_size = sizeof(info);
936
937 memset(&info, 0, dcmd_size);
938
939 info.newest_seq_num = cpu_to_le32(s->event_count);
940 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
941 info.boot_seq_num = cpu_to_le32(s->boot_event);
942
943 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
944 return MFI_STAT_OK;
945}
946
947static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
948{
949 union mfi_evt event;
950
951 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
952 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
953 sizeof(struct mfi_evt_detail));
954 return MFI_STAT_INVALID_PARAMETER;
955 }
956 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
957 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
958 s->event_locale = event.members.locale;
959 s->event_class = event.members.class;
960 s->event_cmd = cmd;
961 /* Decrease busy count; event frame doesn't count here */
962 s->busy--;
963 cmd->iov_size = sizeof(struct mfi_evt_detail);
964 return MFI_STAT_INVALID_STATUS;
965}
966
967static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
968{
969 struct mfi_pd_list info;
970 size_t dcmd_size = sizeof(info);
971 BusChild *kid;
972 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 973
974 memset(&info, 0, dcmd_size);
975 offset = 8;
976 dcmd_limit = offset + sizeof(struct mfi_pd_address);
977 if (cmd->iov_size < dcmd_limit) {
978 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
979 dcmd_limit);
980 return MFI_STAT_INVALID_PARAMETER;
981 }
982
983 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 984 if (max_pd_disks > MFI_MAX_SYS_PDS) {
985 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 986 }
e8f943c3 987 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 988 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd
HR		 989 uint16_t pd_id;
990
991 if (num_pd_disks >= max_pd_disks)
992 break;
e8f943c3 993
3f2cd4dd
HR		 994 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
995 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 996 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
997 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 998 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 999 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
1000 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
1001 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 1002 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1003 num_pd_disks++;
1004 offset += sizeof(struct mfi_pd_address);
1005 }
1006 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
1007 max_pd_disks, offset);
1008
1009 info.size = cpu_to_le32(offset);
1010 info.count = cpu_to_le32(num_pd_disks);
1011
1012 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
1013 return MFI_STAT_OK;
1014}
1015
1016static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1017{
1018 uint16_t flags;
1019
1020 /* mbox0 contains flags */
1021 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1022 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1023 if (flags == MR_PD_QUERY_TYPE_ALL ||
1024 megasas_is_jbod(s)) {
1025 return megasas_dcmd_pd_get_list(s, cmd);
1026 }
1027
1028 return MFI_STAT_OK;
1029}
1030
1031static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1032 MegasasCmd *cmd)
1033{
1034 struct mfi_pd_info *info = cmd->iov_buf;
1035 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1036 uint64_t pd_size;
3f2cd4dd 1037 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3 1038 uint8_t cmdbuf[6];
e8f943c3
HR		 1039 size_t len, resid;
1040
1041 if (!cmd->iov_buf) {
0bd0adbe 1042 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1043 info = cmd->iov_buf;
1044 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1045 info->vpd_page83[0] = 0x7f;
1046 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
87e459a8
PB		 1047 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1048 if (!cmd->req) {
e8f943c3
HR		 1049 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1050 "PD get info std inquiry");
1051 g_free(cmd->iov_buf);
1052 cmd->iov_buf = NULL;
1053 return MFI_STAT_FLASH_ALLOC_FAIL;
1054 }
1055 trace_megasas_dcmd_internal_submit(cmd->index,
1056 "PD get info std inquiry", lun);
87e459a8 1057 len = scsi_req_enqueue(cmd->req);
e8f943c3
HR		 1058 if (len > 0) {
1059 cmd->iov_size = len;
87e459a8 1060 scsi_req_continue(cmd->req);
e8f943c3
HR		 1061 }
1062 return MFI_STAT_INVALID_STATUS;
1063 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1064 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
87e459a8
PB		 1065 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1066 if (!cmd->req) {
e8f943c3
HR		 1067 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1068 "PD get info vpd inquiry");
1069 return MFI_STAT_FLASH_ALLOC_FAIL;
1070 }
1071 trace_megasas_dcmd_internal_submit(cmd->index,
1072 "PD get info vpd inquiry", lun);
87e459a8 1073 len = scsi_req_enqueue(cmd->req);
e8f943c3
HR		 1074 if (len > 0) {
1075 cmd->iov_size = len;
87e459a8 1076 scsi_req_continue(cmd->req);
e8f943c3
HR		 1077 }
1078 return MFI_STAT_INVALID_STATUS;
1079 }
1080 /* Finished, set FW state */
1081 if ((info->inquiry_data[0] >> 5) == 0) {
1082 if (megasas_is_jbod(cmd->state)) {
1083 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1084 } else {
1085 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1086 }
1087 } else {
1088 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1089 }
1090
3f2cd4dd 1091 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1092 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1093 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1094 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1095 info->raw_size = cpu_to_le64(pd_size);
1096 info->non_coerced_size = cpu_to_le64(pd_size);
1097 info->coerced_size = cpu_to_le64(pd_size);
1098 info->encl_device_id = 0xFFFF;
1099 info->slot_number = (sdev->id & 0xFF);
1100 info->path_info.count = 1;
1101 info->path_info.sas_addr[0] =
3f2cd4dd 1102 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1103 info->connected_port_bitmap = 0x1;
1104 info->device_speed = 1;
1105 info->link_speed = 1;
1106 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1107 g_free(cmd->iov_buf);
1108 cmd->iov_size = dcmd_size - resid;
1109 cmd->iov_buf = NULL;
1110 return MFI_STAT_OK;
1111}
1112
1113static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1114{
1115 size_t dcmd_size = sizeof(struct mfi_pd_info);
1116 uint16_t pd_id;
3f2cd4dd 1117 uint8_t target_id, lun_id;
e8f943c3
HR		 1118 SCSIDevice *sdev = NULL;
1119 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1120
1121 if (cmd->iov_size < dcmd_size) {
1122 return MFI_STAT_INVALID_PARAMETER;
1123 }
1124
1125 /* mbox0 has the ID */
1126 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1127 target_id = (pd_id >> 8) & 0xFF;
1128 lun_id = pd_id & 0xFF;
1129 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1130 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1131
1132 if (sdev) {
1133 /* Submit inquiry */
1134 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1135 }
1136
1137 return retval;
1138}
1139
1140static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1141{
1142 struct mfi_ld_list info;
1143 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1144 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1145 uint64_t ld_size;
1146 BusChild *kid;
1147
1148 memset(&info, 0, dcmd_size);
e74a4315 1149 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1150 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1151 dcmd_size);
1152 return MFI_STAT_INVALID_PARAMETER;
1153 }
1154
3f2cd4dd 1155 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1156 if (megasas_is_jbod(s)) {
1157 max_ld_disks = 0;
1158 }
3f2cd4dd
HR		 1159 if (max_ld_disks > MFI_MAX_LD) {
1160 max_ld_disks = MFI_MAX_LD;
1161 }
e8f943c3 1162 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1163 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
e8f943c3
HR		 1164
1165 if (num_ld_disks >= max_ld_disks) {
1166 break;
1167 }
1168 /* Logical device size is in blocks */
4be74634 1169 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1170 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1171 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1172 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1173 num_ld_disks++;
1174 }
1175 info.ld_count = cpu_to_le32(num_ld_disks);
1176 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1177
1178 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1179 cmd->iov_size = dcmd_size - resid;
1180 return MFI_STAT_OK;
1181}
1182
34bb4d02
HR		 1183static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1184{
1185 uint16_t flags;
d97ae368
HR		 1186 struct mfi_ld_targetid_list info;
1187 size_t dcmd_size = sizeof(info), resid;
1188 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1189 BusChild *kid;
34bb4d02
HR		 1190
1191 /* mbox0 contains flags */
1192 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1193 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1194 if (flags != MR_LD_QUERY_TYPE_ALL &&
1195 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1196 max_ld_disks = 0;
1197 }
1198
1199 memset(&info, 0, dcmd_size);
1200 if (cmd->iov_size < 12) {
1201 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1202 dcmd_size);
1203 return MFI_STAT_INVALID_PARAMETER;
1204 }
1205 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1206 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1207 if (megasas_is_jbod(s)) {
1208 max_ld_disks = 0;
34bb4d02 1209 }
3f2cd4dd
HR		 1210 if (max_ld_disks > MFI_MAX_LD) {
1211 max_ld_disks = MFI_MAX_LD;
1212 }
d97ae368 1213 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1214 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
34bb4d02 1215
d97ae368
HR		 1216 if (num_ld_disks >= max_ld_disks) {
1217 break;
1218 }
1219 info.targetid[num_ld_disks] = sdev->lun;
1220 num_ld_disks++;
1221 dcmd_size++;
1222 }
1223 info.ld_count = cpu_to_le32(num_ld_disks);
1224 info.size = dcmd_size;
1225 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1226
1227 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1228 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1229 return MFI_STAT_OK;
1230}
1231
e8f943c3
HR		 1232static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1233 MegasasCmd *cmd)
1234{
1235 struct mfi_ld_info *info = cmd->iov_buf;
1236 size_t dcmd_size = sizeof(struct mfi_ld_info);
1237 uint8_t cdb[6];
e8f943c3 1238 ssize_t len, resid;
3f2cd4dd 1239 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1240 uint64_t ld_size;
1241
1242 if (!cmd->iov_buf) {
0bd0adbe 1243 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1244 info = cmd->iov_buf;
1245 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
87e459a8
PB		 1246 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1247 if (!cmd->req) {
e8f943c3
HR		 1248 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1249 "LD get info vpd inquiry");
1250 g_free(cmd->iov_buf);
1251 cmd->iov_buf = NULL;
1252 return MFI_STAT_FLASH_ALLOC_FAIL;
1253 }
1254 trace_megasas_dcmd_internal_submit(cmd->index,
1255 "LD get info vpd inquiry", lun);
87e459a8 1256 len = scsi_req_enqueue(cmd->req);
e8f943c3
HR		 1257 if (len > 0) {
1258 cmd->iov_size = len;
87e459a8 1259 scsi_req_continue(cmd->req);
e8f943c3
HR		 1260 }
1261 return MFI_STAT_INVALID_STATUS;
1262 }
1263
1264 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1265 info->ld_config.properties.ld.v.target_id = lun;
1266 info->ld_config.params.stripe_size = 3;
1267 info->ld_config.params.num_drives = 1;
1268 info->ld_config.params.is_consistent = 1;
1269 /* Logical device size is in blocks */
4be74634 1270 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1271 info->size = cpu_to_le64(ld_size);
1272 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1273 info->ld_config.span[0].start_block = 0;
1274 info->ld_config.span[0].num_blocks = info->size;
1275 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1276
1277 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1278 g_free(cmd->iov_buf);
1279 cmd->iov_size = dcmd_size - resid;
1280 cmd->iov_buf = NULL;
1281 return MFI_STAT_OK;
1282}
1283
1284static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1285{
1286 struct mfi_ld_info info;
1287 size_t dcmd_size = sizeof(info);
1288 uint16_t ld_id;
1289 uint32_t max_ld_disks = s->fw_luns;
1290 SCSIDevice *sdev = NULL;
1291 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1292
1293 if (cmd->iov_size < dcmd_size) {
1294 return MFI_STAT_INVALID_PARAMETER;
1295 }
1296
1297 /* mbox0 has the ID */
1298 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1299 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1300
1301 if (megasas_is_jbod(s)) {
1302 return MFI_STAT_DEVICE_NOT_FOUND;
1303 }
1304
1305 if (ld_id < max_ld_disks) {
1306 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1307 }
1308
1309 if (sdev) {
1310 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1311 }
1312
1313 return retval;
1314}
1315
1316static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1317{
d37af740 1318 uint8_t data[4096] = { 0 };
e8f943c3
HR		 1319 struct mfi_config_data *info;
1320 int num_pd_disks = 0, array_offset, ld_offset;
1321 BusChild *kid;
1322
1323 if (cmd->iov_size > 4096) {
1324 return MFI_STAT_INVALID_PARAMETER;
1325 }
1326
1327 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1328 num_pd_disks++;
1329 }
1330 info = (struct mfi_config_data *)&data;
1331 /*
1332 * Array mapping:
1333 * - One array per SCSI device
1334 * - One logical drive per SCSI device
1335 * spanning the entire device
1336 */
1337 info->array_count = num_pd_disks;
1338 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1339 info->log_drv_count = num_pd_disks;
1340 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1341 info->spares_count = 0;
1342 info->spares_size = sizeof(struct mfi_spare);
1343 info->size = sizeof(struct mfi_config_data) + info->array_size +
1344 info->log_drv_size;
1345 if (info->size > 4096) {
1346 return MFI_STAT_INVALID_PARAMETER;
1347 }
1348
1349 array_offset = sizeof(struct mfi_config_data);
1350 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1351
1352 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1353 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 1354 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1355 struct mfi_array *array;
1356 struct mfi_ld_config *ld;
1357 uint64_t pd_size;
1358 int i;
1359
1360 array = (struct mfi_array *)(data + array_offset);
4be74634 1361 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1362 array->size = cpu_to_le64(pd_size);
1363 array->num_drives = 1;
1364 array->array_ref = cpu_to_le16(sdev_id);
1365 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1366 array->pd[0].ref.v.seq_num = 0;
1367 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1368 array->pd[0].encl.pd = 0xFF;
1369 array->pd[0].encl.slot = (sdev->id & 0xFF);
1370 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1371 array->pd[i].ref.v.device_id = 0xFFFF;
1372 array->pd[i].ref.v.seq_num = 0;
1373 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1374 array->pd[i].encl.pd = 0xFF;
1375 array->pd[i].encl.slot = 0xFF;
1376 }
1377 array_offset += sizeof(struct mfi_array);
1378 ld = (struct mfi_ld_config *)(data + ld_offset);
1379 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1380 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1381 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1382 MR_LD_CACHE_READ_ADAPTIVE;
1383 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1384 MR_LD_CACHE_READ_ADAPTIVE;
1385 ld->params.state = MFI_LD_STATE_OPTIMAL;
1386 ld->params.stripe_size = 3;
1387 ld->params.num_drives = 1;
1388 ld->params.span_depth = 1;
1389 ld->params.is_consistent = 1;
1390 ld->span[0].start_block = 0;
1391 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1392 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1393 ld_offset += sizeof(struct mfi_ld_config);
1394 }
1395
1396 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1397 return MFI_STAT_OK;
1398}
1399
1400static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1401{
1402 struct mfi_ctrl_props info;
1403 size_t dcmd_size = sizeof(info);
1404
1405 memset(&info, 0x0, dcmd_size);
1406 if (cmd->iov_size < dcmd_size) {
1407 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1408 dcmd_size);
1409 return MFI_STAT_INVALID_PARAMETER;
1410 }
1411 info.pred_fail_poll_interval = cpu_to_le16(300);
1412 info.intr_throttle_cnt = cpu_to_le16(16);
1413 info.intr_throttle_timeout = cpu_to_le16(50);
1414 info.rebuild_rate = 30;
1415 info.patrol_read_rate = 30;
1416 info.bgi_rate = 30;
1417 info.cc_rate = 30;
1418 info.recon_rate = 30;
1419 info.cache_flush_interval = 4;
1420 info.spinup_drv_cnt = 2;
1421 info.spinup_delay = 6;
1422 info.ecc_bucket_size = 15;
1423 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1424 info.expose_encl_devices = 1;
1425
1426 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1427 return MFI_STAT_OK;
1428}
1429
1430static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1431{
4be74634 1432 blk_drain_all();
e8f943c3
HR		 1433 return MFI_STAT_OK;
1434}
1435
1436static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1437{
1438 s->fw_state = MFI_FWSTATE_READY;
1439 return MFI_STAT_OK;
1440}
1441
200b6966 1442/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1443static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1444{
200b6966
HR		 1445 uint16_t target_id;
1446 int i;
1447
1448 /* mbox0 contains the device index */
1449 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1450 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1451 for (i = 0; i < s->fw_cmds; i++) {
1452 MegasasCmd *tmp_cmd = &s->frames[i];
1453 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1454 SCSIDevice *d = tmp_cmd->req->dev;
1455 qdev_reset_all(&d->qdev);
1456 }
1457 }
1458 return MFI_STAT_OK;
e8f943c3
HR		 1459}
1460
1461static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1462{
10d6530c
HR		 1463 struct mfi_ctrl_props info;
1464 size_t dcmd_size = sizeof(info);
1465
1466 if (cmd->iov_size < dcmd_size) {
1467 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1468 dcmd_size);
1469 return MFI_STAT_INVALID_PARAMETER;
1470 }
1b858980 1471 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
10d6530c 1472 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1473 return MFI_STAT_OK;
1474}
1475
1476static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1477{
1478 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1479 return MFI_STAT_OK;
1480}
1481
1482static const struct dcmd_cmd_tbl_t {
1483 int opcode;
1484 const char *desc;
1485 int (*func)(MegasasState *s, MegasasCmd *cmd);
1486} dcmd_cmd_tbl[] = {
1487 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1488 megasas_dcmd_dummy },
1489 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1490 megasas_ctrl_get_info },
1491 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1492 megasas_dcmd_get_properties },
1493 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1494 megasas_dcmd_set_properties },
1495 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1496 megasas_dcmd_dummy },
1497 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1498 megasas_dcmd_dummy },
1499 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1500 megasas_dcmd_dummy },
1501 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1502 megasas_dcmd_dummy },
1503 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1504 megasas_dcmd_dummy },
1505 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1506 megasas_event_info },
1507 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1508 megasas_dcmd_dummy },
1509 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1510 megasas_event_wait },
1511 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1512 megasas_ctrl_shutdown },
1513 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1514 megasas_dcmd_dummy },
1515 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1516 megasas_dcmd_get_fw_time },
1517 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1518 megasas_dcmd_set_fw_time },
1519 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1520 megasas_dcmd_get_bios_info },
1521 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1522 megasas_dcmd_dummy },
1523 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1524 megasas_mfc_get_defaults },
1525 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1526 megasas_dcmd_dummy },
1527 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1528 megasas_cache_flush },
1529 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1530 megasas_dcmd_pd_get_list },
1531 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1532 megasas_dcmd_pd_list_query },
1533 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1534 megasas_dcmd_pd_get_info },
1535 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1538 megasas_dcmd_dummy },
1539 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1542 megasas_dcmd_dummy },
1543 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1544 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1545 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1546 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1547 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1548 megasas_dcmd_ld_get_info },
1549 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1550 megasas_dcmd_dummy },
1551 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1552 megasas_dcmd_dummy },
1553 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1554 megasas_dcmd_dummy },
1555 { MFI_DCMD_CFG_READ, "CFG_READ",
1556 megasas_dcmd_cfg_read },
1557 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1558 megasas_dcmd_dummy },
1559 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1560 megasas_dcmd_dummy },
1561 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1562 megasas_dcmd_dummy },
1563 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1564 megasas_dcmd_dummy },
1565 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1566 megasas_dcmd_dummy },
1567 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1568 megasas_dcmd_dummy },
1569 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1570 megasas_dcmd_dummy },
1571 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1572 megasas_dcmd_dummy },
1573 { MFI_DCMD_CLUSTER, "CLUSTER",
1574 megasas_dcmd_dummy },
1575 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1576 megasas_dcmd_dummy },
1577 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1578 megasas_cluster_reset_ld },
1579 { -1, NULL, NULL }
1580};
1581
1582static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1583{
e8f943c3 1584 int retval = 0;
765a7070 1585 size_t len;
e8f943c3
HR		 1586 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1587
5104fac8
PB		 1588 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1589 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
765a7070 1590 if (megasas_map_dcmd(s, cmd) < 0) {
e8f943c3
HR		 1591 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1592 }
5104fac8 1593 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
e8f943c3
HR		 1594 cmdptr++;
1595 }
765a7070 1596 len = cmd->iov_size;
e8f943c3 1597 if (cmdptr->opcode == -1) {
5104fac8 1598 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
e8f943c3
HR		 1599 retval = megasas_dcmd_dummy(s, cmd);
1600 } else {
1601 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1602 retval = cmdptr->func(s, cmd);
1603 }
1604 if (retval != MFI_STAT_INVALID_STATUS) {
1605 megasas_finish_dcmd(cmd, len);
1606 }
1607 return retval;
1608}
1609
1610static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
36c327a6 1611 SCSIRequest *req, size_t resid)
e8f943c3 1612{
e8f943c3
HR		 1613 int retval = MFI_STAT_OK;
1614 int lun = req->lun;
1615
5104fac8 1616 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
36c327a6 1617 cmd->iov_size -= resid;
5104fac8 1618 switch (cmd->dcmd_opcode) {
e8f943c3
HR		 1619 case MFI_DCMD_PD_GET_INFO:
1620 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1621 break;
1622 case MFI_DCMD_LD_GET_INFO:
1623 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1624 break;
1625 default:
5104fac8 1626 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
e8f943c3
HR		 1627 retval = MFI_STAT_INVALID_DCMD;
1628 break;
1629 }
1630 if (retval != MFI_STAT_INVALID_STATUS) {
1631 megasas_finish_dcmd(cmd, cmd->iov_size);
1632 }
1633 return retval;
1634}
1635
1636static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1637{
1638 int len;
1639
1640 len = scsi_req_enqueue(cmd->req);
1641 if (len < 0) {
1642 len = -len;
1643 }
1644 if (len > 0) {
1645 if (len > cmd->iov_size) {
1646 if (is_write) {
1647 trace_megasas_iov_write_overflow(cmd->index, len,
1648 cmd->iov_size);
1649 } else {
1650 trace_megasas_iov_read_overflow(cmd->index, len,
1651 cmd->iov_size);
1652 }
1653 }
1654 if (len < cmd->iov_size) {
1655 if (is_write) {
1656 trace_megasas_iov_write_underflow(cmd->index, len,
1657 cmd->iov_size);
1658 } else {
1659 trace_megasas_iov_read_underflow(cmd->index, len,
1660 cmd->iov_size);
1661 }
1662 cmd->iov_size = len;
1663 }
1664 scsi_req_continue(cmd->req);
1665 }
1666 return len;
1667}
1668
1669static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
36c327a6 1670 int frame_cmd)
e8f943c3
HR		 1671{
1672 uint8_t *cdb;
b356807f 1673 int target_id, lun_id, cdb_len;
e8f943c3
HR		 1674 bool is_write;
1675 struct SCSIDevice *sdev = NULL;
36c327a6 1676 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
e8f943c3
HR		 1677
1678 cdb = cmd->frame->pass.cdb;
b356807f
PB		 1679 target_id = cmd->frame->header.target_id;
1680 lun_id = cmd->frame->header.lun_id;
1681 cdb_len = cmd->frame->header.cdb_len;
e8f943c3 1682
3f2cd4dd 1683 if (is_logical) {
b356807f 1684 if (target_id >= MFI_MAX_LD || lun_id != 0) {
3f2cd4dd 1685 trace_megasas_scsi_target_not_present(
ee760ac8 1686 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
3f2cd4dd
HR		 1687 return MFI_STAT_DEVICE_NOT_FOUND;
1688 }
e8f943c3 1689 }
b356807f 1690 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
3f2cd4dd 1691
e8f943c3 1692 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
ee760ac8 1693 trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical,
b356807f 1694 target_id, lun_id, sdev, cmd->iov_size);
e8f943c3
HR		 1695
1696 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1697 trace_megasas_scsi_target_not_present(
ee760ac8 1698 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
e8f943c3
HR		 1699 return MFI_STAT_DEVICE_NOT_FOUND;
1700 }
1701
b356807f 1702 if (cdb_len > 16) {
e8f943c3 1703 trace_megasas_scsi_invalid_cdb_len(
ee760ac8 1704 mfi_frame_desc(frame_cmd), is_logical,
b356807f 1705 target_id, lun_id, cdb_len);
e8f943c3
HR		 1706 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1707 cmd->frame->header.scsi_status = CHECK_CONDITION;
1708 s->event_count++;
1709 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1710 }
1711
1712 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1713 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1714 cmd->frame->header.scsi_status = CHECK_CONDITION;
1715 s->event_count++;
1716 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1717 }
1718
b356807f 1719 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cmd);
e8f943c3
HR		 1720 if (!cmd->req) {
1721 trace_megasas_scsi_req_alloc_failed(
ee760ac8 1722 mfi_frame_desc(frame_cmd), target_id, lun_id);
e8f943c3
HR		 1723 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1724 cmd->frame->header.scsi_status = BUSY;
1725 s->event_count++;
1726 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1727 }
1728
1729 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1730 if (cmd->iov_size) {
e8f943c3 1731 if (is_write) {
aaf2a859 1732 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1733 } else {
aaf2a859 1734 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1735 }
1736 } else {
1737 trace_megasas_scsi_nodata(cmd->index);
1738 }
aaf2a859 1739 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1740 return MFI_STAT_INVALID_STATUS;
1741}
1742
36c327a6 1743static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
e8f943c3
HR		 1744{
1745 uint32_t lba_count, lba_start_hi, lba_start_lo;
1746 uint64_t lba_start;
36c327a6 1747 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
e8f943c3
HR		 1748 uint8_t cdb[16];
1749 int len;
1750 struct SCSIDevice *sdev = NULL;
b356807f 1751 int target_id, lun_id, cdb_len;
e8f943c3
HR		 1752
1753 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1754 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1755 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1756 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1757
b356807f
PB		 1758 target_id = cmd->frame->header.target_id;
1759 lun_id = cmd->frame->header.lun_id;
1760 cdb_len = cmd->frame->header.cdb_len;
1761
1762 if (target_id < MFI_MAX_LD && lun_id == 0) {
1763 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1764 }
1765
1766 trace_megasas_handle_io(cmd->index,
ee760ac8 1767 mfi_frame_desc(frame_cmd), target_id, lun_id,
e8f943c3
HR		 1768 (unsigned long)lba_start, (unsigned long)lba_count);
1769 if (!sdev) {
1770 trace_megasas_io_target_not_present(cmd->index,
ee760ac8 1771 mfi_frame_desc(frame_cmd), target_id, lun_id);
e8f943c3
HR		 1772 return MFI_STAT_DEVICE_NOT_FOUND;
1773 }
1774
b356807f 1775 if (cdb_len > 16) {
e8f943c3 1776 trace_megasas_scsi_invalid_cdb_len(
ee760ac8 1777 mfi_frame_desc(frame_cmd), 1, target_id, lun_id, cdb_len);
e8f943c3
HR		 1778 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1779 cmd->frame->header.scsi_status = CHECK_CONDITION;
1780 s->event_count++;
1781 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1782 }
1783
1784 cmd->iov_size = lba_count * sdev->blocksize;
1785 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1786 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1787 cmd->frame->header.scsi_status = CHECK_CONDITION;
1788 s->event_count++;
1789 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1790 }
1791
1792 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1793 cmd->req = scsi_req_new(sdev, cmd->index,
b356807f 1794 lun_id, cdb, cmd);
e8f943c3
HR		 1795 if (!cmd->req) {
1796 trace_megasas_scsi_req_alloc_failed(
ee760ac8 1797 mfi_frame_desc(frame_cmd), target_id, lun_id);
e8f943c3
HR		 1798 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1799 cmd->frame->header.scsi_status = BUSY;
1800 s->event_count++;
1801 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1802 }
1803 len = megasas_enqueue_req(cmd, is_write);
1804 if (len > 0) {
1805 if (is_write) {
1806 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1807 } else {
1808 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1809 }
1810 }
1811 return MFI_STAT_INVALID_STATUS;
1812}
1813
e8f943c3
HR		 1814static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1815{
1816 MegasasCmd *cmd = req->hba_private;
1817
36c327a6 1818 if (cmd->dcmd_opcode != -1) {
e8f943c3
HR		 1819 return NULL;
1820 } else {
1821 return &cmd->qsg;
1822 }
1823}
1824
1825static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1826{
1827 MegasasCmd *cmd = req->hba_private;
1828 uint8_t *buf;
e8f943c3
HR		 1829
1830 trace_megasas_io_complete(cmd->index, len);
1831
36c327a6 1832 if (cmd->dcmd_opcode != -1) {
e8f943c3
HR		 1833 scsi_req_continue(req);
1834 return;
1835 }
1836
1837 buf = scsi_req_get_buf(req);
5104fac8 1838 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
e8f943c3
HR		 1839 struct mfi_pd_info *info = cmd->iov_buf;
1840
1841 if (info->inquiry_data[0] == 0x7f) {
1842 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1843 memcpy(info->inquiry_data, buf, len);
1844 } else if (info->vpd_page83[0] == 0x7f) {
1845 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1846 memcpy(info->vpd_page83, buf, len);
1847 }
1848 scsi_req_continue(req);
5104fac8 1849 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
e8f943c3
HR		 1850 struct mfi_ld_info *info = cmd->iov_buf;
1851
1852 if (cmd->iov_buf) {
1853 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1854 scsi_req_continue(req);
1855 }
1856 }
1857}
1858
1859static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1860 size_t resid)
1861{
1862 MegasasCmd *cmd = req->hba_private;
1863 uint8_t cmd_status = MFI_STAT_OK;
1864
1865 trace_megasas_command_complete(cmd->index, status, resid);
1866
9e55d588
PB		 1867 if (req->io_canceled) {
1868 return;
1869 }
1870
87e459a8 1871 if (cmd->dcmd_opcode != -1) {
e8f943c3
HR		 1872 /*
1873 * Internal command complete
1874 */
36c327a6 1875 cmd_status = megasas_finish_internal_dcmd(cmd, req, resid);
e8f943c3
HR		 1876 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1877 return;
1878 }
1879 } else {
1880 req->status = status;
1881 trace_megasas_scsi_complete(cmd->index, req->status,
1882 cmd->iov_size, req->cmd.xfer);
1883 if (req->status != GOOD) {
1884 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1885 }
1886 if (req->status == CHECK_CONDITION) {
1887 megasas_copy_sense(cmd);
1888 }
1889
e8f943c3 1890 cmd->frame->header.scsi_status = req->status;
e8f943c3
HR		 1891 }
1892 cmd->frame->header.cmd_status = cmd_status;
9e55d588 1893 megasas_complete_command(cmd);
e8f943c3
HR		 1894}
1895
9e55d588 1896static void megasas_command_cancelled(SCSIRequest *req)
e8f943c3
HR		 1897{
1898 MegasasCmd *cmd = req->hba_private;
1899
9e55d588
PB		 1900 if (!cmd) {
1901 return;
e8f943c3 1902 }
9e55d588
PB		 1903 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1904 megasas_complete_command(cmd);
e8f943c3
HR		 1905}
1906
1907static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1908{
1909 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1910 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1911 MegasasCmd *abort_cmd;
1912
1913 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1914 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1915 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1916
1917 abort_cmd = megasas_lookup_frame(s, abort_addr);
1918 if (!abort_cmd) {
1919 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1920 s->event_count++;
1921 return MFI_STAT_OK;
1922 }
1923 if (!megasas_use_queue64(s)) {
1924 abort_ctx &= (uint64_t)0xFFFFFFFF;
1925 }
1926 if (abort_cmd->context != abort_ctx) {
d17e7448
EB		 1927 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1928 abort_cmd->index);
e8f943c3
HR		 1929 s->event_count++;
1930 return MFI_STAT_ABORT_NOT_POSSIBLE;
1931 }
1932 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1933 megasas_abort_command(abort_cmd);
1934 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1935 s->event_cmd = NULL;
1936 }
1937 s->event_count++;
1938 return MFI_STAT_OK;
1939}
1940
1941static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1942 uint32_t frame_count)
1943{
1944 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1945 uint64_t frame_context;
36c327a6 1946 int frame_cmd;
e8f943c3
HR		 1947 MegasasCmd *cmd;
1948
1949 /*
1950 * Always read 64bit context, top bits will be
1951 * masked out if required in megasas_enqueue_frame()
1952 */
16578c6f 1953 frame_context = megasas_frame_get_context(s, frame_addr);
e8f943c3
HR		 1954
1955 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1956 if (!cmd) {
1957 /* reply queue full */
1958 trace_megasas_frame_busy(frame_addr);
16578c6f
PB		 1959 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1960 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
e8f943c3
HR		 1961 megasas_complete_frame(s, frame_context);
1962 s->event_count++;
1963 return;
1964 }
36c327a6
PB		 1965 frame_cmd = cmd->frame->header.frame_cmd;
1966 switch (frame_cmd) {
e8f943c3
HR		 1967 case MFI_CMD_INIT:
1968 frame_status = megasas_init_firmware(s, cmd);
1969 break;
1970 case MFI_CMD_DCMD:
1971 frame_status = megasas_handle_dcmd(s, cmd);
1972 break;
1973 case MFI_CMD_ABORT:
1974 frame_status = megasas_handle_abort(s, cmd);
1975 break;
1976 case MFI_CMD_PD_SCSI_IO:
e8f943c3 1977 case MFI_CMD_LD_SCSI_IO:
36c327a6 1978 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
e8f943c3
HR		 1979 break;
1980 case MFI_CMD_LD_READ:
1981 case MFI_CMD_LD_WRITE:
36c327a6 1982 frame_status = megasas_handle_io(s, cmd, frame_cmd);
e8f943c3
HR		 1983 break;
1984 default:
36c327a6 1985 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
e8f943c3
HR		 1986 s->event_count++;
1987 break;
1988 }
1989 if (frame_status != MFI_STAT_INVALID_STATUS) {
421cc3e7
PB		 1990 if (cmd->frame) {
1991 cmd->frame->header.cmd_status = frame_status;
1992 } else {
1993 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1994 }
6df5718b 1995 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 1996 megasas_complete_frame(s, cmd->context);
1997 }
1998}
1999
a8170e5e 2000static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2001 unsigned size)
2002{
2003 MegasasState *s = opaque;
e23d0498 2004 PCIDevice *pci_dev = PCI_DEVICE(s);
2e0aec15 2005 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
e8f943c3
HR		 2006 uint32_t retval = 0;
2007
2008 switch (addr) {
2009 case MFI_IDB:
2010 retval = 0;
77bb6b17 2011 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2012 break;
2013 case MFI_OMSG0:
2014 case MFI_OSP0:
e23d0498 2015 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2016 (s->fw_state & MFI_FWSTATE_MASK) |
2017 ((s->fw_sge & 0xff) << 16) |
2018 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2019 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2020 retval);
e8f943c3
HR		 2021 break;
2022 case MFI_OSTS:
2023 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2024 retval = base_class->osts;
e8f943c3 2025 }
77bb6b17 2026 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2027 break;
2028 case MFI_OMSK:
2029 retval = s->intr_mask;
77bb6b17 2030 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2031 break;
2032 case MFI_ODCR0:
7957ee71 2033 retval = s->doorbell ? 1 : 0;
77bb6b17 2034 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2035 break;
e23d0498
HR		 2036 case MFI_DIAG:
2037 retval = s->diag;
77bb6b17 2038 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2039 break;
2040 case MFI_OSP1:
2041 retval = 15;
77bb6b17 2042 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2043 break;
e8f943c3
HR		 2044 default:
2045 trace_megasas_mmio_invalid_readl(addr);
2046 break;
2047 }
e8f943c3
HR		 2048 return retval;
2049}
2050
e23d0498
HR		 2051static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2052
a8170e5e 2053static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2054 uint64_t val, unsigned size)
2055{
2056 MegasasState *s = opaque;
52190c1e 2057 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2058 uint64_t frame_addr;
2059 uint32_t frame_count;
2060 int i;
2061
e8f943c3
HR		 2062 switch (addr) {
2063 case MFI_IDB:
77bb6b17 2064 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2065 if (val & MFI_FWINIT_ABORT) {
2066 /* Abort all pending cmds */
2067 for (i = 0; i < s->fw_cmds; i++) {
2068 megasas_abort_command(&s->frames[i]);
2069 }
2070 }
2071 if (val & MFI_FWINIT_READY) {
2072 /* move to FW READY */
2073 megasas_soft_reset(s);
2074 }
2075 if (val & MFI_FWINIT_MFIMODE) {
2076 /* discard MFIs */
2077 }
e23d0498
HR		 2078 if (val & MFI_FWINIT_STOP_ADP) {
2079 /* Terminal error, stop processing */
2080 s->fw_state = MFI_FWSTATE_FAULT;
2081 }
e8f943c3
HR		 2082 break;
2083 case MFI_OMSK:
77bb6b17 2084 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2085 s->intr_mask = val;
4522b69c
HR		 2086 if (!megasas_intr_enabled(s) &&
2087 !msi_enabled(pci_dev) &&
2088 !msix_enabled(pci_dev)) {
e8f943c3 2089 trace_megasas_irq_lower();
9e64f8a3 2090 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2091 }
2092 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2093 if (msix_enabled(pci_dev)) {
2094 trace_megasas_msix_enabled(0);
2095 } else if (msi_enabled(pci_dev)) {
2096 trace_megasas_msi_enabled(0);
2097 } else {
2098 trace_megasas_intr_enabled();
2099 }
e8f943c3
HR		 2100 } else {
2101 trace_megasas_intr_disabled();
e23d0498 2102 megasas_soft_reset(s);
e8f943c3
HR		 2103 }
2104 break;
2105 case MFI_ODCR0:
77bb6b17 2106 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3 2107 s->doorbell = 0;
7957ee71
HR		 2108 if (megasas_intr_enabled(s)) {
2109 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
e8f943c3 2110 trace_megasas_irq_lower();
9e64f8a3 2111 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2112 }
2113 }
2114 break;
2115 case MFI_IQPH:
77bb6b17 2116 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2117 /* Received high 32 bits of a 64 bit MFI frame address */
2118 s->frame_hi = val;
2119 break;
2120 case MFI_IQPL:
77bb6b17 2121 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2122 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2123 /* Fallthrough */
e8f943c3 2124 case MFI_IQP:
77bb6b17
HR		 2125 if (addr == MFI_IQP) {
2126 trace_megasas_mmio_writel("MFI_IQP", val);
2127 /* Received 64 bit MFI frame address */
2128 s->frame_hi = 0;
2129 }
e8f943c3
HR		 2130 frame_addr = (val & ~0x1F);
2131 /* Add possible 64 bit offset */
2132 frame_addr |= ((uint64_t)s->frame_hi << 32);
2133 s->frame_hi = 0;
2134 frame_count = (val >> 1) & 0xF;
2135 megasas_handle_frame(s, frame_addr, frame_count);
2136 break;
e23d0498 2137 case MFI_SEQ:
77bb6b17 2138 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498 2139 /* Magic sequence to start ADP reset */
24dfa9fa
PP		 2140 if (adp_reset_seq[s->adp_reset++] == val) {
2141 if (s->adp_reset == 6) {
2142 s->adp_reset = 0;
2143 s->diag = MFI_DIAG_WRITE_ENABLE;
2144 }
e23d0498
HR		 2145 } else {
2146 s->adp_reset = 0;
2147 s->diag = 0;
2148 }
e23d0498
HR		 2149 break;
2150 case MFI_DIAG:
77bb6b17 2151 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2152 /* ADP reset */
2153 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2154 (val & MFI_DIAG_RESET_ADP)) {
2155 s->diag |= MFI_DIAG_RESET_ADP;
2156 megasas_soft_reset(s);
2157 s->adp_reset = 0;
2158 s->diag = 0;
2159 }
2160 break;
e8f943c3
HR		 2161 default:
2162 trace_megasas_mmio_invalid_writel(addr, val);
2163 break;
2164 }
2165}
2166
2167static const MemoryRegionOps megasas_mmio_ops = {
2168 .read = megasas_mmio_read,
2169 .write = megasas_mmio_write,
2170 .endianness = DEVICE_LITTLE_ENDIAN,
2171 .impl = {
2172 .min_access_size = 8,
2173 .max_access_size = 8,
2174 }
2175};
2176
a8170e5e 2177static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2178 unsigned size)
2179{
2180 return megasas_mmio_read(opaque, addr & 0xff, size);
2181}
2182
a8170e5e 2183static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2184 uint64_t val, unsigned size)
2185{
2186 megasas_mmio_write(opaque, addr & 0xff, val, size);
2187}
2188
2189static const MemoryRegionOps megasas_port_ops = {
2190 .read = megasas_port_read,
2191 .write = megasas_port_write,
2192 .endianness = DEVICE_LITTLE_ENDIAN,
2193 .impl = {
2194 .min_access_size = 4,
2195 .max_access_size = 4,
2196 }
2197};
2198
a8170e5e 2199static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2200 unsigned size)
2201{
2202 return 0;
2203}
2204
55875fc4
SP		 2205static void megasas_queue_write(void *opaque, hwaddr addr,
2206 uint64_t val, unsigned size)
2207{
2208 return;
2209}
2210
e8f943c3
HR		 2211static const MemoryRegionOps megasas_queue_ops = {
2212 .read = megasas_queue_read,
55875fc4 2213 .write = megasas_queue_write,
e8f943c3
HR		 2214 .endianness = DEVICE_LITTLE_ENDIAN,
2215 .impl = {
2216 .min_access_size = 8,
2217 .max_access_size = 8,
2218 }
2219};
2220
2221static void megasas_soft_reset(MegasasState *s)
2222{
2223 int i;
2224 MegasasCmd *cmd;
2225
8d72db68 2226 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2227 for (i = 0; i < s->fw_cmds; i++) {
2228 cmd = &s->frames[i];
2229 megasas_abort_command(cmd);
2230 }
8d72db68
HR		 2231 if (s->fw_state == MFI_FWSTATE_READY) {
2232 BusChild *kid;
2233
2234 /*
2235 * The EFI firmware doesn't handle UA,
2236 * so we need to clear the Power On/Reset UA
2237 * after the initial reset.
2238 */
2239 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 2240 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
8d72db68
HR		 2241
2242 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2243 scsi_device_unit_attention_reported(sdev);
2244 }
2245 }
e8f943c3
HR		 2246 megasas_reset_frames(s);
2247 s->reply_queue_len = s->fw_cmds;
2248 s->reply_queue_pa = 0;
2249 s->consumer_pa = 0;
2250 s->producer_pa = 0;
2251 s->fw_state = MFI_FWSTATE_READY;
2252 s->doorbell = 0;
2253 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2254 s->frame_hi = 0;
2255 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2256 s->event_count++;
2257 s->boot_event = s->event_count;
2258}
2259
2260static void megasas_scsi_reset(DeviceState *dev)
2261{
c79e16ae 2262 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2263
2264 megasas_soft_reset(s);
2265}
2266
e23d0498 2267static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2268 .name = "megasas",
2269 .version_id = 0,
2270 .minimum_version_id = 0,
d49805ae 2271 .fields = (VMStateField[]) {
52190c1e 2272 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2273 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3 2274
2b151297
PP		 2275 VMSTATE_UINT32(fw_state, MegasasState),
2276 VMSTATE_UINT32(intr_mask, MegasasState),
2277 VMSTATE_UINT32(doorbell, MegasasState),
e8f943c3
HR		 2278 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2279 VMSTATE_UINT64(consumer_pa, MegasasState),
2280 VMSTATE_UINT64(producer_pa, MegasasState),
2281 VMSTATE_END_OF_LIST()
2282 }
2283};
2284
e23d0498
HR		 2285static const VMStateDescription vmstate_megasas_gen2 = {
2286 .name = "megasas-gen2",
2287 .version_id = 0,
2288 .minimum_version_id = 0,
2289 .minimum_version_id_old = 0,
2290 .fields = (VMStateField[]) {
20daa90a 2291 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
e23d0498
HR		 2292 VMSTATE_MSIX(parent_obj, MegasasState),
2293
2b151297
PP		 2294 VMSTATE_UINT32(fw_state, MegasasState),
2295 VMSTATE_UINT32(intr_mask, MegasasState),
2296 VMSTATE_UINT32(doorbell, MegasasState),
e23d0498
HR		 2297 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2298 VMSTATE_UINT64(consumer_pa, MegasasState),
2299 VMSTATE_UINT64(producer_pa, MegasasState),
2300 VMSTATE_END_OF_LIST()
2301 }
2302};
2303
18fc611b 2304static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2305{
c79e16ae 2306 MegasasState *s = MEGASAS(d);
e8f943c3 2307
4522b69c
HR		 2308 if (megasas_use_msix(s)) {
2309 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2310 }
afea4e14 2311 msi_uninit(d);
e8f943c3
HR		 2312}
2313
2314static const struct SCSIBusInfo megasas_scsi_info = {
2315 .tcq = true,
2316 .max_target = MFI_MAX_LD,
2317 .max_lun = 255,
2318
2319 .transfer_data = megasas_xfer_complete,
2320 .get_sg_list = megasas_get_sg_list,
2321 .complete = megasas_command_complete,
9e55d588 2322 .cancel = megasas_command_cancelled,
e8f943c3
HR		 2323};
2324
ae071cc8 2325static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
e8f943c3 2326{
c79e16ae 2327 MegasasState *s = MEGASAS(dev);
2e0aec15 2328 MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
e8f943c3
HR		 2329 uint8_t *pci_conf;
2330 int i, bar_type;
1108b2f8
C		 2331 Error *err = NULL;
2332 int ret;
e8f943c3 2333
52190c1e 2334 pci_conf = dev->config;
e8f943c3
HR		 2335
2336 /* PCI latency timer = 0 */
2337 pci_conf[PCI_LATENCY_TIMER] = 0;
2338 /* Interrupt pin 1 */
2339 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2340
afea4e14 2341 if (s->msi != ON_OFF_AUTO_OFF) {
1108b2f8
C		 2342 ret = msi_init(dev, 0x50, 1, true, false, &err);
2343 /* Any error other than -ENOTSUP(board's MSI support is broken)
2344 * is a programming error */
2345 assert(!ret || ret == -ENOTSUP);
2346 if (ret && s->msi == ON_OFF_AUTO_ON) {
2347 /* Can't satisfy user's explicit msi=on request, fail */
2348 error_append_hint(&err, "You have to use msi=auto (default) or "
2349 "msi=off with this machine type.\n");
2350 error_propagate(errp, err);
2351 return;
2352 } else if (ret) {
2353 /* With msi=auto, we fall back to MSI off silently */
2354 s->msi = ON_OFF_AUTO_OFF;
2355 error_free(err);
2356 }
2357 }
2358
29776739 2359 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2360 "megasas-mmio", 0x4000);
29776739 2361 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2362 "megasas-io", 256);
29776739 2363 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2364 "megasas-queue", 0x40000);
2365
e8f943c3 2366 if (megasas_use_msix(s) &&
e23d0498 2367 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
ee640c62
C		 2368 &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2369 /* TODO: check msix_init's error, and should fail on msix=on */
b4b4a57f 2370 s->msix = ON_OFF_AUTO_OFF;
e8f943c3 2371 }
ee640c62 2372
e23d0498
HR		 2373 if (pci_is_express(dev)) {
2374 pcie_endpoint_cap_init(dev, 0xa0);
2375 }
e8f943c3
HR		 2376
2377 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2378 pci_register_bar(dev, b->ioport_bar,
2379 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2380 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2381 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2382
2383 if (megasas_use_msix(s)) {
52190c1e 2384 msix_vector_use(dev, 0);
e8f943c3
HR		 2385 }
2386
8d72db68 2387 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2388 if (!s->sas_addr) {
2389 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2390 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
cdc57472 2391 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
76b523db
HR		 2392 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2393 s->sas_addr |= PCI_FUNC(dev->devfn);
2394 }
fb654157 2395 if (!s->hba_serial) {
23335f62 2396 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2397 }
e8f943c3
HR		 2398 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2399 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2400 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2401 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2402 } else {
2403 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2404 }
2405 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2406 s->fw_cmds = MEGASAS_MAX_FRAMES;
2407 }
2408 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2409 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2410
2411 if (megasas_is_jbod(s)) {
2412 s->fw_luns = MFI_MAX_SYS_PDS;
2413 } else {
2414 s->fw_luns = MFI_MAX_LD;
2415 }
e8f943c3
HR		 2416 s->producer_pa = 0;
2417 s->consumer_pa = 0;
2418 for (i = 0; i < s->fw_cmds; i++) {
2419 s->frames[i].index = i;
2420 s->frames[i].context = -1;
2421 s->frames[i].pa = 0;
2422 s->frames[i].state = s;
2423 }
2424
b1187b51
AF		 2425 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2426 &megasas_scsi_info, NULL);
e8f943c3
HR		 2427}
2428
e23d0498 2429static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2430 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2431 MEGASAS_DEFAULT_SGE),
2432 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2433 MEGASAS_DEFAULT_FRAMES),
fb654157 2434 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2435 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2436 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2437 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e8f943c3
HR		 2438 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2439 MEGASAS_FLAG_USE_JBOD, false),
2440 DEFINE_PROP_END_OF_LIST(),
2441};
2442
e23d0498
HR		 2443static Property megasas_properties_gen2[] = {
2444 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2445 MEGASAS_DEFAULT_SGE),
2446 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2447 MEGASAS_GEN2_DEFAULT_FRAMES),
2448 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2449 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2450 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2451 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e23d0498
HR		 2452 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2453 MEGASAS_FLAG_USE_JBOD, false),
2454 DEFINE_PROP_END_OF_LIST(),
2455};
2456
2457typedef struct MegasasInfo {
2458 const char *name;
2459 const char *desc;
2460 const char *product_name;
2461 const char *product_version;
2462 uint16_t device_id;
2463 uint16_t subsystem_id;
2464 int ioport_bar;
2465 int mmio_bar;
e23d0498
HR		 2466 int osts;
2467 const VMStateDescription *vmsd;
2468 Property *props;
71d78767 2469 InterfaceInfo *interfaces;
e23d0498
HR		 2470} MegasasInfo;
2471
2472static struct MegasasInfo megasas_devices[] = {
2473 {
2474 .name = TYPE_MEGASAS_GEN1,
2475 .desc = "LSI MegaRAID SAS 1078",
2476 .product_name = "LSI MegaRAID SAS 8708EM2",
2477 .product_version = MEGASAS_VERSION_GEN1,
2478 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2479 .subsystem_id = 0x1013,
2480 .ioport_bar = 2,
2481 .mmio_bar = 0,
2482 .osts = MFI_1078_RM | 1,
e23d0498
HR		 2483 .vmsd = &vmstate_megasas_gen1,
2484 .props = megasas_properties_gen1,
fd3b02c8
EH		 2485 .interfaces = (InterfaceInfo[]) {
2486 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2487 { },
2488 },
e23d0498
HR		 2489 },{
2490 .name = TYPE_MEGASAS_GEN2,
2491 .desc = "LSI MegaRAID SAS 2108",
2492 .product_name = "LSI MegaRAID SAS 9260-8i",
2493 .product_version = MEGASAS_VERSION_GEN2,
2494 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2495 .subsystem_id = 0x9261,
2496 .ioport_bar = 0,
2497 .mmio_bar = 1,
2498 .osts = MFI_GEN2_RM,
e23d0498
HR		 2499 .vmsd = &vmstate_megasas_gen2,
2500 .props = megasas_properties_gen2,
71d78767
EH		 2501 .interfaces = (InterfaceInfo[]) {
2502 { INTERFACE_PCIE_DEVICE },
2503 { }
2504 },
e23d0498
HR		 2505 }
2506};
2507
e8f943c3
HR		 2508static void megasas_class_init(ObjectClass *oc, void *data)
2509{
2510 DeviceClass *dc = DEVICE_CLASS(oc);
2511 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2e0aec15 2512 MegasasBaseClass *e = MEGASAS_CLASS(oc);
e23d0498 2513 const MegasasInfo *info = data;
e8f943c3 2514
ae071cc8 2515 pc->realize = megasas_scsi_realize;
e8f943c3
HR		 2516 pc->exit = megasas_scsi_uninit;
2517 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2518 pc->device_id = info->device_id;
e8f943c3 2519 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2520 pc->subsystem_id = info->subsystem_id;
e8f943c3 2521 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2522 e->mmio_bar = info->mmio_bar;
2523 e->ioport_bar = info->ioport_bar;
2524 e->osts = info->osts;
2525 e->product_name = info->product_name;
2526 e->product_version = info->product_version;
4f67d30b 2527 device_class_set_props(dc, info->props);
e8f943c3 2528 dc->reset = megasas_scsi_reset;
e23d0498 2529 dc->vmsd = info->vmsd;
125ee0ed 2530 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2531 dc->desc = info->desc;
e8f943c3
HR		 2532}
2533
2534static const TypeInfo megasas_info = {
e23d0498 2535 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2536 .parent = TYPE_PCI_DEVICE,
2537 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2538 .class_size = sizeof(MegasasBaseClass),
2539 .abstract = true,
e8f943c3
HR		 2540};
2541
2542static void megasas_register_types(void)
2543{
e23d0498
HR		 2544 int i;
2545
e8f943c3 2546 type_register_static(&megasas_info);
e23d0498
HR		 2547 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2548 const MegasasInfo *info = &megasas_devices[i];
2549 TypeInfo type_info = {};
2550
2551 type_info.name = info->name;
2552 type_info.parent = TYPE_MEGASAS_BASE;
2553 type_info.class_data = (void *)info;
2554 type_info.class_init = megasas_class_init;
71d78767 2555 type_info.interfaces = info->interfaces;
e23d0498
HR		 2556
2557 type_register(&type_info);
2558 }
e8f943c3
HR		 2559}
2560
2561type_init(megasas_register_types)
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