[thirdparty/qemu.git] / hw / sd / pxa2xx_mmci.c

/*
 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPLv2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
#include "hw/sd/sd.h"
#include "hw/qdev.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"

#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)

#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)

struct PXA2xxMMCIState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    qemu_irq inserted;
    qemu_irq readonly;

    BlockBackend *blk;
    SDBus sdbus;

    uint32_t status;
    uint32_t clkrt;
    uint32_t spi;
    uint32_t cmdat;
    uint32_t resp_tout;
    uint32_t read_tout;
    int32_t blklen;
    int32_t numblk;
    uint32_t intmask;
    uint32_t intreq;
    int32_t cmd;
    uint32_t arg;

    int32_t active;
    int32_t bytesleft;
    uint8_t tx_fifo[64];
    uint32_t tx_start;
    uint32_t tx_len;
    uint8_t rx_fifo[32];
    uint32_t rx_start;
    uint32_t rx_len;
    uint16_t resp_fifo[9];
    uint32_t resp_len;

    int32_t cmdreq;
};

static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
{
    PXA2xxMMCIState *s = opaque;

    return s->tx_start < ARRAY_SIZE(s->tx_fifo)
        && s->rx_start < ARRAY_SIZE(s->rx_fifo)
        && s->tx_len <= ARRAY_SIZE(s->tx_fifo)
        && s->rx_len <= ARRAY_SIZE(s->rx_fifo)
        && s->resp_len <= ARRAY_SIZE(s->resp_fifo);
}


static const VMStateDescription vmstate_pxa2xx_mmci = {
    .name = "pxa2xx-mmci",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(status, PXA2xxMMCIState),
        VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
        VMSTATE_UINT32(spi, PXA2xxMMCIState),
        VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
        VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
        VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
        VMSTATE_INT32(blklen, PXA2xxMMCIState),
        VMSTATE_INT32(numblk, PXA2xxMMCIState),
        VMSTATE_UINT32(intmask, PXA2xxMMCIState),
        VMSTATE_UINT32(intreq, PXA2xxMMCIState),
        VMSTATE_INT32(cmd, PXA2xxMMCIState),
        VMSTATE_UINT32(arg, PXA2xxMMCIState),
        VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
        VMSTATE_INT32(active, PXA2xxMMCIState),
        VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
        VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
        VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
        VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
        VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
        VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
        VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
        VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
        VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
        VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
        VMSTATE_END_OF_LIST()
    }
};

#define MMC_STRPCL	0x00	/* MMC Clock Start/Stop register */
#define MMC_STAT	0x04	/* MMC Status register */
#define MMC_CLKRT	0x08	/* MMC Clock Rate register */
#define MMC_SPI		0x0c	/* MMC SPI Mode register */
#define MMC_CMDAT	0x10	/* MMC Command/Data register */
#define MMC_RESTO	0x14	/* MMC Response Time-Out register */
#define MMC_RDTO	0x18	/* MMC Read Time-Out register */
#define MMC_BLKLEN	0x1c	/* MMC Block Length register */
#define MMC_NUMBLK	0x20	/* MMC Number of Blocks register */
#define MMC_PRTBUF	0x24	/* MMC Buffer Partly Full register */
#define MMC_I_MASK	0x28	/* MMC Interrupt Mask register */
#define MMC_I_REG	0x2c	/* MMC Interrupt Request register */
#define MMC_CMD		0x30	/* MMC Command register */
#define MMC_ARGH	0x34	/* MMC Argument High register */
#define MMC_ARGL	0x38	/* MMC Argument Low register */
#define MMC_RES		0x3c	/* MMC Response FIFO */
#define MMC_RXFIFO	0x40	/* MMC Receive FIFO */
#define MMC_TXFIFO	0x44	/* MMC Transmit FIFO */
#define MMC_RDWAIT	0x48	/* MMC RD_WAIT register */
#define MMC_BLKS_REM	0x4c	/* MMC Blocks Remaining register */

/* Bitfield masks */
#define STRPCL_STOP_CLK	(1 << 0)
#define STRPCL_STRT_CLK	(1 << 1)
#define STAT_TOUT_RES	(1 << 1)
#define STAT_CLK_EN	(1 << 8)
#define STAT_DATA_DONE	(1 << 11)
#define STAT_PRG_DONE	(1 << 12)
#define STAT_END_CMDRES	(1 << 13)
#define SPI_SPI_MODE	(1 << 0)
#define CMDAT_RES_TYPE	(3 << 0)
#define CMDAT_DATA_EN	(1 << 2)
#define CMDAT_WR_RD	(1 << 3)
#define CMDAT_DMA_EN	(1 << 7)
#define CMDAT_STOP_TRAN	(1 << 10)
#define INT_DATA_DONE	(1 << 0)
#define INT_PRG_DONE	(1 << 1)
#define INT_END_CMD	(1 << 2)
#define INT_STOP_CMD	(1 << 3)
#define INT_CLK_OFF	(1 << 4)
#define INT_RXFIFO_REQ	(1 << 5)
#define INT_TXFIFO_REQ	(1 << 6)
#define INT_TINT	(1 << 7)
#define INT_DAT_ERR	(1 << 8)
#define INT_RES_ERR	(1 << 9)
#define INT_RD_STALLED	(1 << 10)
#define INT_SDIO_INT	(1 << 11)
#define INT_SDIO_SACK	(1 << 12)
#define PRTBUF_PRT_BUF	(1 << 0)

/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
    uint32_t mask = s->intmask;
    if (s->cmdat & CMDAT_DMA_EN) {
        mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;

        qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
        qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
    }

    qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}

static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
    if (!s->active)
        return;

    if (s->cmdat & CMDAT_WR_RD) {
        while (s->bytesleft && s->tx_len) {
            sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
            s->tx_start &= 0x1f;
            s->tx_len --;
            s->bytesleft --;
        }
        if (s->bytesleft)
            s->intreq |= INT_TXFIFO_REQ;
    } else
        while (s->bytesleft && s->rx_len < 32) {
            s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
                sdbus_read_data(&s->sdbus);
            s->bytesleft --;
            s->intreq |= INT_RXFIFO_REQ;
        }

    if (!s->bytesleft) {
        s->active = 0;
        s->intreq |= INT_DATA_DONE;
        s->status |= STAT_DATA_DONE;

        if (s->cmdat & CMDAT_WR_RD) {
            s->intreq |= INT_PRG_DONE;
            s->status |= STAT_PRG_DONE;
        }
    }

    pxa2xx_mmci_int_update(s);
}

static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
    int rsplen, i;
    SDRequest request;
    uint8_t response[16];

    s->active = 1;
    s->rx_len = 0;
    s->tx_len = 0;
    s->cmdreq = 0;

    request.cmd = s->cmd;
    request.arg = s->arg;
    request.crc = 0;	/* FIXME */

    rsplen = sdbus_do_command(&s->sdbus, &request, response);
    s->intreq |= INT_END_CMD;

    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
    switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1)	\
        s->resp_fifo[(wd) + 0] |= (value0);	\
        s->resp_fifo[(wd) + 1] |= (value1) << 8;
    case 0:	/* No response */
        goto complete;

    case 1:	/* R1, R4, R5 or R6 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    case 2:	/* R2 */
        if (rsplen < 16)
            goto timeout;
        goto complete;

    case 3:	/* R3 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    complete:
        for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
            PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
        }
        s->status |= STAT_END_CMDRES;

        if (!(s->cmdat & CMDAT_DATA_EN))
            s->active = 0;
        else
            s->bytesleft = s->numblk * s->blklen;

        s->resp_len = 0;
        break;

    timeout:
        s->active = 0;
        s->status |= STAT_TOUT_RES;
        break;
    }

    pxa2xx_mmci_fifo_update(s);
}

static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    uint32_t ret = 0;

    switch (offset) {
    case MMC_STRPCL:
        break;
    case MMC_STAT:
        ret = s->status;
        break;
    case MMC_CLKRT:
        ret = s->clkrt;
        break;
    case MMC_SPI:
        ret = s->spi;
        break;
    case MMC_CMDAT:
        ret = s->cmdat;
        break;
    case MMC_RESTO:
        ret = s->resp_tout;
        break;
    case MMC_RDTO:
        ret = s->read_tout;
        break;
    case MMC_BLKLEN:
        ret = s->blklen;
        break;
    case MMC_NUMBLK:
        ret = s->numblk;
        break;
    case MMC_PRTBUF:
        break;
    case MMC_I_MASK:
        ret = s->intmask;
        break;
    case MMC_I_REG:
        ret = s->intreq;
        break;
    case MMC_CMD:
        ret = s->cmd | 0x40;
        break;
    case MMC_ARGH:
        ret = s->arg >> 16;
        break;
    case MMC_ARGL:
        ret = s->arg & 0xffff;
        break;
    case MMC_RES:
        ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
        break;
    case MMC_RXFIFO:
        while (size-- && s->rx_len) {
            ret |= s->rx_fifo[s->rx_start++] << (size << 3);
            s->rx_start &= 0x1f;
            s->rx_len --;
        }
        s->intreq &= ~INT_RXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;
    case MMC_RDWAIT:
        break;
    case MMC_BLKS_REM:
        ret = s->numblk;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
    }
    trace_pxa2xx_mmci_read(size, offset, ret);

    return ret;
}

static void pxa2xx_mmci_write(void *opaque,
                              hwaddr offset, uint64_t value, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;

    trace_pxa2xx_mmci_write(size, offset, value);
    switch (offset) {
    case MMC_STRPCL:
        if (value & STRPCL_STRT_CLK) {
            s->status |= STAT_CLK_EN;
            s->intreq &= ~INT_CLK_OFF;

            if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
                s->status &= STAT_CLK_EN;
                pxa2xx_mmci_wakequeues(s);
            }
        }

        if (value & STRPCL_STOP_CLK) {
            s->status &= ~STAT_CLK_EN;
            s->intreq |= INT_CLK_OFF;
            s->active = 0;
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CLKRT:
        s->clkrt = value & 7;
        break;

    case MMC_SPI:
        s->spi = value & 0xf;
        if (value & SPI_SPI_MODE) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: attempted to use card in SPI mode\n", __func__);
        }
        break;

    case MMC_CMDAT:
        s->cmdat = value & 0x3dff;
        s->active = 0;
        s->cmdreq = 1;
        if (!(value & CMDAT_STOP_TRAN)) {
            s->status &= STAT_CLK_EN;

            if (s->status & STAT_CLK_EN)
                pxa2xx_mmci_wakequeues(s);
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_RESTO:
        s->resp_tout = value & 0x7f;
        break;

    case MMC_RDTO:
        s->read_tout = value & 0xffff;
        break;

    case MMC_BLKLEN:
        s->blklen = value & 0xfff;
        break;

    case MMC_NUMBLK:
        s->numblk = value & 0xffff;
        break;

    case MMC_PRTBUF:
        if (value & PRTBUF_PRT_BUF) {
            s->tx_start ^= 32;
            s->tx_len = 0;
        }
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_I_MASK:
        s->intmask = value & 0x1fff;
        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CMD:
        s->cmd = value & 0x3f;
        break;

    case MMC_ARGH:
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case MMC_ARGL:
        s->arg &= 0xffff0000;
        s->arg |= value & 0x0000ffff;
        break;

    case MMC_TXFIFO:
        while (size-- && s->tx_len < 0x20)
            s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
                    (value >> (size << 3)) & 0xff;
        s->intreq &= ~INT_TXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_RDWAIT:
    case MMC_BLKS_REM:
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect reg 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
    }
}

static const MemoryRegionOps pxa2xx_mmci_ops = {
    .read = pxa2xx_mmci_read,
    .write = pxa2xx_mmci_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
                hwaddr base,
                BlockBackend *blk, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma)
{
    DeviceState *dev, *carddev;
    SysBusDevice *sbd;
    PXA2xxMMCIState *s;
    Error *err = NULL;

    dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
    s = PXA2XX_MMCI(dev);
    sbd = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sbd, 0, base);
    sysbus_connect_irq(sbd, 0, irq);
    qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
    qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);

    /* Create and plug in the sd card */
    carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
    qdev_prop_set_drive(carddev, "drive", blk, &err);
    if (err) {
        error_report("failed to init SD card: %s", error_get_pretty(err));
        return NULL;
    }
    object_property_set_bool(OBJECT(carddev), true, "realized", &err);
    if (err) {
        error_report("failed to init SD card: %s", error_get_pretty(err));
        return NULL;
    }

    return s;
}

static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->inserted, inserted);
}

static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->readonly, readonly);
}

void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                          qemu_irq coverswitch)
{
    DeviceState *dev = DEVICE(s);

    s->readonly = readonly;
    s->inserted = coverswitch;

    pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
    pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
}

static void pxa2xx_mmci_reset(DeviceState *d)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(d);

    s->status = 0;
    s->clkrt = 0;
    s->spi = 0;
    s->cmdat = 0;
    s->resp_tout = 0;
    s->read_tout = 0;
    s->blklen = 0;
    s->numblk = 0;
    s->intmask = 0;
    s->intreq = 0;
    s->cmd = 0;
    s->arg = 0;
    s->active = 0;
    s->bytesleft = 0;
    s->tx_start = 0;
    s->tx_len = 0;
    s->rx_start = 0;
    s->rx_len = 0;
    s->resp_len = 0;
    s->cmdreq = 0;
    memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
    memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
}

static void pxa2xx_mmci_instance_init(Object *obj)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
                          "pxa2xx-mmci", 0x00100000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
    qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
                        TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
}

static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_pxa2xx_mmci;
    dc->reset = pxa2xx_mmci_reset;
}

static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
{
    SDBusClass *sbc = SD_BUS_CLASS(klass);

    sbc->set_inserted = pxa2xx_mmci_set_inserted;
    sbc->set_readonly = pxa2xx_mmci_set_readonly;
}

static const TypeInfo pxa2xx_mmci_info = {
    .name = TYPE_PXA2XX_MMCI,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxMMCIState),
    .instance_init = pxa2xx_mmci_instance_init,
    .class_init = pxa2xx_mmci_class_init,
};

static const TypeInfo pxa2xx_mmci_bus_info = {
    .name = TYPE_PXA2XX_MMCI_BUS,
    .parent = TYPE_SD_BUS,
    .instance_size = sizeof(SDBus),
    .class_init = pxa2xx_mmci_bus_class_init,
};

static void pxa2xx_mmci_register_types(void)
{
    type_register_static(&pxa2xx_mmci_info);
    type_register_static(&pxa2xx_mmci_bus_info);
}

type_init(pxa2xx_mmci_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPLv2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
a171fe39 AZ	11	*/
a171fe39 AZ	12
8ef94f0b	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
64552b6b	15	#include "hw/irq.h"
7a9468c9	16	#include "hw/sysbus.h"
d6454270	17	#include "migration/vmstate.h"
0d09e41a	18	#include "hw/arm/pxa.h"
e3382ef0	19	#include "hw/sd/sd.h"
83c9f4ca	20	#include "hw/qdev.h"
7a9468c9	21	#include "hw/qdev-properties.h"
a9563e75	22	#include "qemu/error-report.h"
487b406a	23	#include "qemu/log.h"
0b8fa32f	24	#include "qemu/module.h"
487b406a	25	#include "trace.h"
7a9468c9 PM	26
	27	#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
	28	#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
a171fe39	29
a9563e75 PM	30	#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
	31	#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
	32
bc24a225	33	struct PXA2xxMMCIState {
7a9468c9 PM	34	SysBusDevice parent_obj;
7a9468c9 PM	35
2bf90458	36	MemoryRegion iomem;
a171fe39	37	qemu_irq irq;
2115c019 AZ	38	qemu_irq rx_dma;
2115c019 AZ	39	qemu_irq tx_dma;
a9563e75 PM	40	qemu_irq inserted;
a9563e75 PM	41	qemu_irq readonly;
a171fe39	42
7a9468c9	43	BlockBackend *blk;
a9563e75	44	SDBus sdbus;
a171fe39 AZ	45
	46	uint32_t status;
	47	uint32_t clkrt;
	48	uint32_t spi;
	49	uint32_t cmdat;
	50	uint32_t resp_tout;
	51	uint32_t read_tout;
19d25e0a PM	52	int32_t blklen;
19d25e0a PM	53	int32_t numblk;
a171fe39 AZ	54	uint32_t intmask;
a171fe39 AZ	55	uint32_t intreq;
19d25e0a	56	int32_t cmd;
a171fe39 AZ	57	uint32_t arg;
a171fe39 AZ	58
19d25e0a PM	59	int32_t active;
19d25e0a PM	60	int32_t bytesleft;
a171fe39	61	uint8_t tx_fifo[64];
19d25e0a PM	62	uint32_t tx_start;
19d25e0a PM	63	uint32_t tx_len;
a171fe39	64	uint8_t rx_fifo[32];
19d25e0a PM	65	uint32_t rx_start;
19d25e0a PM	66	uint32_t rx_len;
a171fe39	67	uint16_t resp_fifo[9];
19d25e0a	68	uint32_t resp_len;
a171fe39	69
19d25e0a PM	70	int32_t cmdreq;
	71	};
	72
	73	static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
	74	{
	75	PXA2xxMMCIState *s = opaque;
	76
	77	return s->tx_start < ARRAY_SIZE(s->tx_fifo)
	78	&& s->rx_start < ARRAY_SIZE(s->rx_fifo)
	79	&& s->tx_len <= ARRAY_SIZE(s->tx_fifo)
	80	&& s->rx_len <= ARRAY_SIZE(s->rx_fifo)
	81	&& s->resp_len <= ARRAY_SIZE(s->resp_fifo);
	82	}
	83
	84
	85	static const VMStateDescription vmstate_pxa2xx_mmci = {
	86	.name = "pxa2xx-mmci",
	87	.version_id = 2,
	88	.minimum_version_id = 2,
	89	.fields = (VMStateField[]) {
	90	VMSTATE_UINT32(status, PXA2xxMMCIState),
	91	VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
	92	VMSTATE_UINT32(spi, PXA2xxMMCIState),
	93	VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
	94	VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
	95	VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
	96	VMSTATE_INT32(blklen, PXA2xxMMCIState),
	97	VMSTATE_INT32(numblk, PXA2xxMMCIState),
	98	VMSTATE_UINT32(intmask, PXA2xxMMCIState),
	99	VMSTATE_UINT32(intreq, PXA2xxMMCIState),
	100	VMSTATE_INT32(cmd, PXA2xxMMCIState),
	101	VMSTATE_UINT32(arg, PXA2xxMMCIState),
	102	VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
	103	VMSTATE_INT32(active, PXA2xxMMCIState),
	104	VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
	105	VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
	106	VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
	107	VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
	108	VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
	109	VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
	110	VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
	111	VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
	112	VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
	113	VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
	114	VMSTATE_END_OF_LIST()
	115	}
a171fe39 AZ	116	};
	117
	118	#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
	119	#define MMC_STAT 0x04 /* MMC Status register */
	120	#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
	121	#define MMC_SPI 0x0c /* MMC SPI Mode register */
	122	#define MMC_CMDAT 0x10 /* MMC Command/Data register */
	123	#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
	124	#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
	125	#define MMC_BLKLEN 0x1c /* MMC Block Length register */
	126	#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
	127	#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
	128	#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
	129	#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
	130	#define MMC_CMD 0x30 /* MMC Command register */
	131	#define MMC_ARGH 0x34 /* MMC Argument High register */
	132	#define MMC_ARGL 0x38 /* MMC Argument Low register */
	133	#define MMC_RES 0x3c /* MMC Response FIFO */
	134	#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
	135	#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
	136	#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
	137	#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
	138
	139	/* Bitfield masks */
	140	#define STRPCL_STOP_CLK (1 << 0)
	141	#define STRPCL_STRT_CLK (1 << 1)
	142	#define STAT_TOUT_RES (1 << 1)
	143	#define STAT_CLK_EN (1 << 8)
	144	#define STAT_DATA_DONE (1 << 11)
	145	#define STAT_PRG_DONE (1 << 12)
	146	#define STAT_END_CMDRES (1 << 13)
	147	#define SPI_SPI_MODE (1 << 0)
	148	#define CMDAT_RES_TYPE (3 << 0)
	149	#define CMDAT_DATA_EN (1 << 2)
	150	#define CMDAT_WR_RD (1 << 3)
	151	#define CMDAT_DMA_EN (1 << 7)
	152	#define CMDAT_STOP_TRAN (1 << 10)
	153	#define INT_DATA_DONE (1 << 0)
	154	#define INT_PRG_DONE (1 << 1)
	155	#define INT_END_CMD (1 << 2)
	156	#define INT_STOP_CMD (1 << 3)
	157	#define INT_CLK_OFF (1 << 4)
	158	#define INT_RXFIFO_REQ (1 << 5)
	159	#define INT_TXFIFO_REQ (1 << 6)
	160	#define INT_TINT (1 << 7)
	161	#define INT_DAT_ERR (1 << 8)
	162	#define INT_RES_ERR (1 << 9)
	163	#define INT_RD_STALLED (1 << 10)
	164	#define INT_SDIO_INT (1 << 11)
	165	#define INT_SDIO_SACK (1 << 12)
	166	#define PRTBUF_PRT_BUF (1 << 0)
	167
	168	/* Route internal interrupt lines to the global IC and DMA */
bc24a225	169	static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
a171fe39 AZ	170	{
	171	uint32_t mask = s->intmask;
	172	if (s->cmdat & CMDAT_DMA_EN) {
	173	mask \|= INT_RXFIFO_REQ \| INT_TXFIFO_REQ;
	174
2115c019 AZ	175	qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
2115c019 AZ	176	qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
a171fe39 AZ	177	}
	178
	179	qemu_set_irq(s->irq, !!(s->intreq & ~mask));
	180	}
	181
bc24a225	182	static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
a171fe39 AZ	183	{
	184	if (!s->active)
	185	return;
	186
	187	if (s->cmdat & CMDAT_WR_RD) {
	188	while (s->bytesleft && s->tx_len) {
a9563e75	189	sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
a171fe39 AZ	190	s->tx_start &= 0x1f;
	191	s->tx_len --;
	192	s->bytesleft --;
	193	}
	194	if (s->bytesleft)
	195	s->intreq \|= INT_TXFIFO_REQ;
	196	} else
	197	while (s->bytesleft && s->rx_len < 32) {
	198	s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
a9563e75	199	sdbus_read_data(&s->sdbus);
a171fe39 AZ	200	s->bytesleft --;
	201	s->intreq \|= INT_RXFIFO_REQ;
	202	}
	203
	204	if (!s->bytesleft) {
	205	s->active = 0;
	206	s->intreq \|= INT_DATA_DONE;
	207	s->status \|= STAT_DATA_DONE;
	208
	209	if (s->cmdat & CMDAT_WR_RD) {
	210	s->intreq \|= INT_PRG_DONE;
	211	s->status \|= STAT_PRG_DONE;
	212	}
	213	}
	214
	215	pxa2xx_mmci_int_update(s);
	216	}
	217
bc24a225	218	static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
a171fe39 AZ	219	{
a171fe39 AZ	220	int rsplen, i;
bc24a225	221	SDRequest request;
a171fe39 AZ	222	uint8_t response[16];
	223
	224	s->active = 1;
	225	s->rx_len = 0;
	226	s->tx_len = 0;
	227	s->cmdreq = 0;
	228
	229	request.cmd = s->cmd;
	230	request.arg = s->arg;
	231	request.crc = 0; /* FIXME */
	232
a9563e75	233	rsplen = sdbus_do_command(&s->sdbus, &request, response);
a171fe39 AZ	234	s->intreq \|= INT_END_CMD;
	235
	236	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	237	switch (s->cmdat & CMDAT_RES_TYPE) {
	238	#define PXAMMCI_RESP(wd, value0, value1) \
	239	s->resp_fifo[(wd) + 0] \|= (value0); \
	240	s->resp_fifo[(wd) + 1] \|= (value1) << 8;
	241	case 0: /* No response */
	242	goto complete;
	243
	244	case 1: /* R1, R4, R5 or R6 */
	245	if (rsplen < 4)
	246	goto timeout;
	247	goto complete;
	248
	249	case 2: /* R2 */
	250	if (rsplen < 16)
	251	goto timeout;
	252	goto complete;
	253
	254	case 3: /* R3 */
	255	if (rsplen < 4)
	256	goto timeout;
	257	goto complete;
	258
	259	complete:
	260	for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
	261	PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
	262	}
	263	s->status \|= STAT_END_CMDRES;
	264
	265	if (!(s->cmdat & CMDAT_DATA_EN))
	266	s->active = 0;
	267	else
	268	s->bytesleft = s->numblk * s->blklen;
	269
	270	s->resp_len = 0;
	271	break;
	272
	273	timeout:
	274	s->active = 0;
	275	s->status \|= STAT_TOUT_RES;
	276	break;
	277	}
	278
	279	pxa2xx_mmci_fifo_update(s);
	280	}
	281
13e1e476	282	static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
a171fe39	283	{
bc24a225	284	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
487b406a	285	uint32_t ret = 0;
a171fe39 AZ	286
	287	switch (offset) {
	288	case MMC_STRPCL:
487b406a	289	break;
a171fe39	290	case MMC_STAT:
487b406a PMD	291	ret = s->status;
487b406a PMD	292	break;
a171fe39	293	case MMC_CLKRT:
487b406a PMD	294	ret = s->clkrt;
487b406a PMD	295	break;
a171fe39	296	case MMC_SPI:
487b406a PMD	297	ret = s->spi;
487b406a PMD	298	break;
a171fe39	299	case MMC_CMDAT:
487b406a PMD	300	ret = s->cmdat;
487b406a PMD	301	break;
a171fe39	302	case MMC_RESTO:
487b406a PMD	303	ret = s->resp_tout;
487b406a PMD	304	break;
a171fe39	305	case MMC_RDTO:
487b406a PMD	306	ret = s->read_tout;
487b406a PMD	307	break;
a171fe39	308	case MMC_BLKLEN:
487b406a PMD	309	ret = s->blklen;
487b406a PMD	310	break;
a171fe39	311	case MMC_NUMBLK:
487b406a PMD	312	ret = s->numblk;
487b406a PMD	313	break;
a171fe39	314	case MMC_PRTBUF:
487b406a	315	break;
a171fe39	316	case MMC_I_MASK:
487b406a PMD	317	ret = s->intmask;
487b406a PMD	318	break;
a171fe39	319	case MMC_I_REG:
487b406a PMD	320	ret = s->intreq;
487b406a PMD	321	break;
a171fe39	322	case MMC_CMD:
487b406a PMD	323	ret = s->cmd \| 0x40;
487b406a PMD	324	break;
a171fe39	325	case MMC_ARGH:
487b406a PMD	326	ret = s->arg >> 16;
487b406a PMD	327	break;
a171fe39	328	case MMC_ARGL:
487b406a PMD	329	ret = s->arg & 0xffff;
487b406a PMD	330	break;
a171fe39	331	case MMC_RES:
487b406a PMD	332	ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
487b406a PMD	333	break;
a171fe39	334	case MMC_RXFIFO:
13e1e476 PM	335	while (size-- && s->rx_len) {
13e1e476 PM	336	ret \|= s->rx_fifo[s->rx_start++] << (size << 3);
a171fe39 AZ	337	s->rx_start &= 0x1f;
	338	s->rx_len --;
	339	}
	340	s->intreq &= ~INT_RXFIFO_REQ;
	341	pxa2xx_mmci_fifo_update(s);
487b406a	342	break;
a171fe39	343	case MMC_RDWAIT:
487b406a	344	break;
a171fe39	345	case MMC_BLKS_REM:
487b406a PMD	346	ret = s->numblk;
487b406a PMD	347	break;
a171fe39	348	default:
487b406a PMD	349	qemu_log_mask(LOG_GUEST_ERROR,
	350	"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
	351	__func__, offset);
a171fe39	352	}
487b406a	353	trace_pxa2xx_mmci_read(size, offset, ret);
a171fe39	354
487b406a	355	return ret;
a171fe39 AZ	356	}
	357
	358	static void pxa2xx_mmci_write(void *opaque,
13e1e476	359	hwaddr offset, uint64_t value, unsigned size)
a171fe39	360	{
bc24a225	361	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39	362
487b406a	363	trace_pxa2xx_mmci_write(size, offset, value);
a171fe39 AZ	364	switch (offset) {
	365	case MMC_STRPCL:
	366	if (value & STRPCL_STRT_CLK) {
	367	s->status \|= STAT_CLK_EN;
	368	s->intreq &= ~INT_CLK_OFF;
	369
	370	if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
	371	s->status &= STAT_CLK_EN;
	372	pxa2xx_mmci_wakequeues(s);
	373	}
	374	}
	375
	376	if (value & STRPCL_STOP_CLK) {
	377	s->status &= ~STAT_CLK_EN;
	378	s->intreq \|= INT_CLK_OFF;
	379	s->active = 0;
	380	}
	381
	382	pxa2xx_mmci_int_update(s);
	383	break;
	384
	385	case MMC_CLKRT:
	386	s->clkrt = value & 7;
	387	break;
	388
	389	case MMC_SPI:
	390	s->spi = value & 0xf;
487b406a PMD	391	if (value & SPI_SPI_MODE) {
	392	qemu_log_mask(LOG_GUEST_ERROR,
	393	"%s: attempted to use card in SPI mode\n", __func__);
	394	}
a171fe39 AZ	395	break;
	396
	397	case MMC_CMDAT:
	398	s->cmdat = value & 0x3dff;
	399	s->active = 0;
	400	s->cmdreq = 1;
	401	if (!(value & CMDAT_STOP_TRAN)) {
	402	s->status &= STAT_CLK_EN;
	403
	404	if (s->status & STAT_CLK_EN)
	405	pxa2xx_mmci_wakequeues(s);
	406	}
	407
	408	pxa2xx_mmci_int_update(s);
	409	break;
	410
	411	case MMC_RESTO:
	412	s->resp_tout = value & 0x7f;
	413	break;
	414
	415	case MMC_RDTO:
	416	s->read_tout = value & 0xffff;
	417	break;
	418
	419	case MMC_BLKLEN:
	420	s->blklen = value & 0xfff;
	421	break;
	422
	423	case MMC_NUMBLK:
	424	s->numblk = value & 0xffff;
	425	break;
	426
	427	case MMC_PRTBUF:
	428	if (value & PRTBUF_PRT_BUF) {
	429	s->tx_start ^= 32;
	430	s->tx_len = 0;
	431	}
	432	pxa2xx_mmci_fifo_update(s);
	433	break;
	434
	435	case MMC_I_MASK:
	436	s->intmask = value & 0x1fff;
	437	pxa2xx_mmci_int_update(s);
	438	break;
	439
	440	case MMC_CMD:
	441	s->cmd = value & 0x3f;
	442	break;
	443
	444	case MMC_ARGH:
	445	s->arg &= 0x0000ffff;
	446	s->arg \|= value << 16;
	447	break;
	448
	449	case MMC_ARGL:
	450	s->arg &= 0xffff0000;
	451	s->arg \|= value & 0x0000ffff;
	452	break;
	453
	454	case MMC_TXFIFO:
13e1e476	455	while (size-- && s->tx_len < 0x20)
a171fe39	456	s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
13e1e476	457	(value >> (size << 3)) & 0xff;
a171fe39 AZ	458	s->intreq &= ~INT_TXFIFO_REQ;
	459	pxa2xx_mmci_fifo_update(s);
	460	break;
	461
	462	case MMC_RDWAIT:
	463	case MMC_BLKS_REM:
	464	break;
	465
	466	default:
487b406a PMD	467	qemu_log_mask(LOG_GUEST_ERROR,
	468	"%s: incorrect reg 0x%02" HWADDR_PRIx " "
	469	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
a171fe39 AZ	470	}
	471	}
	472
2bf90458	473	static const MemoryRegionOps pxa2xx_mmci_ops = {
13e1e476 PM	474	.read = pxa2xx_mmci_read,
13e1e476 PM	475	.write = pxa2xx_mmci_write,
2bf90458	476	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	477	};
a171fe39 AZ	478
2bf90458	479	PXA2xxMMCIState pxa2xx_mmci_init(MemoryRegion sysmem,
a8170e5e	480	hwaddr base,
4be74634	481	BlockBackend *blk, qemu_irq irq,
2115c019	482	qemu_irq rx_dma, qemu_irq tx_dma)
a171fe39	483	{
a9563e75	484	DeviceState dev, carddev;
7a9468c9	485	SysBusDevice *sbd;
bc24a225	486	PXA2xxMMCIState *s;
a9563e75	487	Error *err = NULL;
a171fe39	488
7a9468c9 PM	489	dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
7a9468c9 PM	490	s = PXA2XX_MMCI(dev);
7a9468c9 PM	491	sbd = SYS_BUS_DEVICE(dev);
	492	sysbus_mmio_map(sbd, 0, base);
	493	sysbus_connect_irq(sbd, 0, irq);
	494	qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
	495	qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
a9563e75 PM	496
	497	/* Create and plug in the sd card */
	498	carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
	499	qdev_prop_set_drive(carddev, "drive", blk, &err);
	500	if (err) {
	501	error_report("failed to init SD card: %s", error_get_pretty(err));
	502	return NULL;
	503	}
	504	object_property_set_bool(OBJECT(carddev), true, "realized", &err);
	505	if (err) {
	506	error_report("failed to init SD card: %s", error_get_pretty(err));
	507	return NULL;
	508	}
	509
a171fe39 AZ	510	return s;
	511	}
	512
a9563e75 PM	513	static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
	514	{
	515	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	516
	517	qemu_set_irq(s->inserted, inserted);
	518	}
	519
	520	static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
	521	{
	522	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	523
	524	qemu_set_irq(s->readonly, readonly);
	525	}
	526
bc24a225	527	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
7a9468c9	528	qemu_irq coverswitch)
a171fe39	529	{
a9563e75 PM	530	DeviceState *dev = DEVICE(s);
	531
	532	s->readonly = readonly;
	533	s->inserted = coverswitch;
	534
	535	pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
	536	pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
a171fe39	537	}
7a9468c9	538
6002915e PM	539	static void pxa2xx_mmci_reset(DeviceState *d)
	540	{
	541	PXA2xxMMCIState *s = PXA2XX_MMCI(d);
	542
	543	s->status = 0;
	544	s->clkrt = 0;
	545	s->spi = 0;
	546	s->cmdat = 0;
	547	s->resp_tout = 0;
	548	s->read_tout = 0;
	549	s->blklen = 0;
	550	s->numblk = 0;
	551	s->intmask = 0;
	552	s->intreq = 0;
	553	s->cmd = 0;
	554	s->arg = 0;
	555	s->active = 0;
	556	s->bytesleft = 0;
	557	s->tx_start = 0;
	558	s->tx_len = 0;
	559	s->rx_start = 0;
	560	s->rx_len = 0;
	561	s->resp_len = 0;
	562	s->cmdreq = 0;
	563	memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
	564	memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
	565	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	566	}
	567
7a9468c9 PM	568	static void pxa2xx_mmci_instance_init(Object *obj)
	569	{
	570	PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
	571	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	572	DeviceState *dev = DEVICE(obj);
	573
	574	memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
	575	"pxa2xx-mmci", 0x00100000);
	576	sysbus_init_mmio(sbd, &s->iomem);
	577	sysbus_init_irq(sbd, &s->irq);
	578	qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
	579	qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
	580
a9563e75 PM	581	qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
	582	TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
	583	}
	584
19d25e0a PM	585	static void pxa2xx_mmci_class_init(ObjectClass klass, void data)
	586	{
	587	DeviceClass *dc = DEVICE_CLASS(klass);
	588
	589	dc->vmsd = &vmstate_pxa2xx_mmci;
6002915e	590	dc->reset = pxa2xx_mmci_reset;
19d25e0a PM	591	}
19d25e0a PM	592
a9563e75 PM	593	static void pxa2xx_mmci_bus_class_init(ObjectClass klass, void data)
	594	{
	595	SDBusClass *sbc = SD_BUS_CLASS(klass);
	596
	597	sbc->set_inserted = pxa2xx_mmci_set_inserted;
	598	sbc->set_readonly = pxa2xx_mmci_set_readonly;
7a9468c9 PM	599	}
	600
	601	static const TypeInfo pxa2xx_mmci_info = {
	602	.name = TYPE_PXA2XX_MMCI,
	603	.parent = TYPE_SYS_BUS_DEVICE,
	604	.instance_size = sizeof(PXA2xxMMCIState),
	605	.instance_init = pxa2xx_mmci_instance_init,
19d25e0a	606	.class_init = pxa2xx_mmci_class_init,
7a9468c9 PM	607	};
7a9468c9 PM	608
a9563e75 PM	609	static const TypeInfo pxa2xx_mmci_bus_info = {
	610	.name = TYPE_PXA2XX_MMCI_BUS,
	611	.parent = TYPE_SD_BUS,
	612	.instance_size = sizeof(SDBus),
	613	.class_init = pxa2xx_mmci_bus_class_init,
	614	};
	615
7a9468c9 PM	616	static void pxa2xx_mmci_register_types(void)
	617	{
	618	type_register_static(&pxa2xx_mmci_info);
a9563e75	619	type_register_static(&pxa2xx_mmci_bus_info);
7a9468c9 PM	620	}
	621
	622	type_init(pxa2xx_mmci_register_types)