[thirdparty/qemu.git] / hw / sd / pxa2xx_mmci.c

/*
 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPLv2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/pxa.h"
#include "hw/sd/sd.h"
#include "hw/qdev-properties.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"

#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
/* This is reusing the SDBus typedef from SD_BUS */
DECLARE_INSTANCE_CHECKER(SDBus, PXA2XX_MMCI_BUS,
                         TYPE_PXA2XX_MMCI_BUS)

struct PXA2xxMMCIState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    qemu_irq inserted;
    qemu_irq readonly;

    BlockBackend *blk;
    SDBus sdbus;

    uint32_t status;
    uint32_t clkrt;
    uint32_t spi;
    uint32_t cmdat;
    uint32_t resp_tout;
    uint32_t read_tout;
    int32_t blklen;
    int32_t numblk;
    uint32_t intmask;
    uint32_t intreq;
    int32_t cmd;
    uint32_t arg;

    int32_t active;
    int32_t bytesleft;
    uint8_t tx_fifo[64];
    uint32_t tx_start;
    uint32_t tx_len;
    uint8_t rx_fifo[32];
    uint32_t rx_start;
    uint32_t rx_len;
    uint16_t resp_fifo[9];
    uint32_t resp_len;

    int32_t cmdreq;
};

static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
{
    PXA2xxMMCIState *s = opaque;

    return s->tx_start < ARRAY_SIZE(s->tx_fifo)
        && s->rx_start < ARRAY_SIZE(s->rx_fifo)
        && s->tx_len <= ARRAY_SIZE(s->tx_fifo)
        && s->rx_len <= ARRAY_SIZE(s->rx_fifo)
        && s->resp_len <= ARRAY_SIZE(s->resp_fifo);
}


static const VMStateDescription vmstate_pxa2xx_mmci = {
    .name = "pxa2xx-mmci",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(status, PXA2xxMMCIState),
        VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
        VMSTATE_UINT32(spi, PXA2xxMMCIState),
        VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
        VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
        VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
        VMSTATE_INT32(blklen, PXA2xxMMCIState),
        VMSTATE_INT32(numblk, PXA2xxMMCIState),
        VMSTATE_UINT32(intmask, PXA2xxMMCIState),
        VMSTATE_UINT32(intreq, PXA2xxMMCIState),
        VMSTATE_INT32(cmd, PXA2xxMMCIState),
        VMSTATE_UINT32(arg, PXA2xxMMCIState),
        VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
        VMSTATE_INT32(active, PXA2xxMMCIState),
        VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
        VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
        VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
        VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
        VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
        VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
        VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
        VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
        VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
        VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
        VMSTATE_END_OF_LIST()
    }
};

#define MMC_STRPCL	0x00	/* MMC Clock Start/Stop register */
#define MMC_STAT	0x04	/* MMC Status register */
#define MMC_CLKRT	0x08	/* MMC Clock Rate register */
#define MMC_SPI		0x0c	/* MMC SPI Mode register */
#define MMC_CMDAT	0x10	/* MMC Command/Data register */
#define MMC_RESTO	0x14	/* MMC Response Time-Out register */
#define MMC_RDTO	0x18	/* MMC Read Time-Out register */
#define MMC_BLKLEN	0x1c	/* MMC Block Length register */
#define MMC_NUMBLK	0x20	/* MMC Number of Blocks register */
#define MMC_PRTBUF	0x24	/* MMC Buffer Partly Full register */
#define MMC_I_MASK	0x28	/* MMC Interrupt Mask register */
#define MMC_I_REG	0x2c	/* MMC Interrupt Request register */
#define MMC_CMD		0x30	/* MMC Command register */
#define MMC_ARGH	0x34	/* MMC Argument High register */
#define MMC_ARGL	0x38	/* MMC Argument Low register */
#define MMC_RES		0x3c	/* MMC Response FIFO */
#define MMC_RXFIFO	0x40	/* MMC Receive FIFO */
#define MMC_TXFIFO	0x44	/* MMC Transmit FIFO */
#define MMC_RDWAIT	0x48	/* MMC RD_WAIT register */
#define MMC_BLKS_REM	0x4c	/* MMC Blocks Remaining register */

/* Bitfield masks */
#define STRPCL_STOP_CLK	(1 << 0)
#define STRPCL_STRT_CLK	(1 << 1)
#define STAT_TOUT_RES	(1 << 1)
#define STAT_CLK_EN	(1 << 8)
#define STAT_DATA_DONE	(1 << 11)
#define STAT_PRG_DONE	(1 << 12)
#define STAT_END_CMDRES	(1 << 13)
#define SPI_SPI_MODE	(1 << 0)
#define CMDAT_RES_TYPE	(3 << 0)
#define CMDAT_DATA_EN	(1 << 2)
#define CMDAT_WR_RD	(1 << 3)
#define CMDAT_DMA_EN	(1 << 7)
#define CMDAT_STOP_TRAN	(1 << 10)
#define INT_DATA_DONE	(1 << 0)
#define INT_PRG_DONE	(1 << 1)
#define INT_END_CMD	(1 << 2)
#define INT_STOP_CMD	(1 << 3)
#define INT_CLK_OFF	(1 << 4)
#define INT_RXFIFO_REQ	(1 << 5)
#define INT_TXFIFO_REQ	(1 << 6)
#define INT_TINT	(1 << 7)
#define INT_DAT_ERR	(1 << 8)
#define INT_RES_ERR	(1 << 9)
#define INT_RD_STALLED	(1 << 10)
#define INT_SDIO_INT	(1 << 11)
#define INT_SDIO_SACK	(1 << 12)
#define PRTBUF_PRT_BUF	(1 << 0)

/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
    uint32_t mask = s->intmask;
    if (s->cmdat & CMDAT_DMA_EN) {
        mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;

        qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
        qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
    }

    qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}

static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
    if (!s->active)
        return;

    if (s->cmdat & CMDAT_WR_RD) {
        while (s->bytesleft && s->tx_len) {
            sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]);
            s->tx_start &= 0x1f;
            s->tx_len --;
            s->bytesleft --;
        }
        if (s->bytesleft)
            s->intreq |= INT_TXFIFO_REQ;
    } else
        while (s->bytesleft && s->rx_len < 32) {
            s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
                sdbus_read_byte(&s->sdbus);
            s->bytesleft --;
            s->intreq |= INT_RXFIFO_REQ;
        }

    if (!s->bytesleft) {
        s->active = 0;
        s->intreq |= INT_DATA_DONE;
        s->status |= STAT_DATA_DONE;

        if (s->cmdat & CMDAT_WR_RD) {
            s->intreq |= INT_PRG_DONE;
            s->status |= STAT_PRG_DONE;
        }
    }

    pxa2xx_mmci_int_update(s);
}

static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
    int rsplen, i;
    SDRequest request;
    uint8_t response[16];

    s->active = 1;
    s->rx_len = 0;
    s->tx_len = 0;
    s->cmdreq = 0;

    request.cmd = s->cmd;
    request.arg = s->arg;
    request.crc = 0;	/* FIXME */

    rsplen = sdbus_do_command(&s->sdbus, &request, response);
    s->intreq |= INT_END_CMD;

    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
    switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1)	\
        s->resp_fifo[(wd) + 0] |= (value0);	\
        s->resp_fifo[(wd) + 1] |= (value1) << 8;
    case 0:	/* No response */
        goto complete;

    case 1:	/* R1, R4, R5 or R6 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    case 2:	/* R2 */
        if (rsplen < 16)
            goto timeout;
        goto complete;

    case 3:	/* R3 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    complete:
        for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
            PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
        }
        s->status |= STAT_END_CMDRES;

        if (!(s->cmdat & CMDAT_DATA_EN))
            s->active = 0;
        else
            s->bytesleft = s->numblk * s->blklen;

        s->resp_len = 0;
        break;

    timeout:
        s->active = 0;
        s->status |= STAT_TOUT_RES;
        break;
    }

    pxa2xx_mmci_fifo_update(s);
}

static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    uint32_t ret = 0;

    switch (offset) {
    case MMC_STRPCL:
        break;
    case MMC_STAT:
        ret = s->status;
        break;
    case MMC_CLKRT:
        ret = s->clkrt;
        break;
    case MMC_SPI:
        ret = s->spi;
        break;
    case MMC_CMDAT:
        ret = s->cmdat;
        break;
    case MMC_RESTO:
        ret = s->resp_tout;
        break;
    case MMC_RDTO:
        ret = s->read_tout;
        break;
    case MMC_BLKLEN:
        ret = s->blklen;
        break;
    case MMC_NUMBLK:
        ret = s->numblk;
        break;
    case MMC_PRTBUF:
        break;
    case MMC_I_MASK:
        ret = s->intmask;
        break;
    case MMC_I_REG:
        ret = s->intreq;
        break;
    case MMC_CMD:
        ret = s->cmd | 0x40;
        break;
    case MMC_ARGH:
        ret = s->arg >> 16;
        break;
    case MMC_ARGL:
        ret = s->arg & 0xffff;
        break;
    case MMC_RES:
        ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
        break;
    case MMC_RXFIFO:
        while (size-- && s->rx_len) {
            ret |= s->rx_fifo[s->rx_start++] << (size << 3);
            s->rx_start &= 0x1f;
            s->rx_len --;
        }
        s->intreq &= ~INT_RXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;
    case MMC_RDWAIT:
        break;
    case MMC_BLKS_REM:
        ret = s->numblk;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
    }
    trace_pxa2xx_mmci_read(size, offset, ret);

    return ret;
}

static void pxa2xx_mmci_write(void *opaque,
                              hwaddr offset, uint64_t value, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;

    trace_pxa2xx_mmci_write(size, offset, value);
    switch (offset) {
    case MMC_STRPCL:
        if (value & STRPCL_STRT_CLK) {
            s->status |= STAT_CLK_EN;
            s->intreq &= ~INT_CLK_OFF;

            if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
                s->status &= STAT_CLK_EN;
                pxa2xx_mmci_wakequeues(s);
            }
        }

        if (value & STRPCL_STOP_CLK) {
            s->status &= ~STAT_CLK_EN;
            s->intreq |= INT_CLK_OFF;
            s->active = 0;
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CLKRT:
        s->clkrt = value & 7;
        break;

    case MMC_SPI:
        s->spi = value & 0xf;
        if (value & SPI_SPI_MODE) {
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: attempted to use card in SPI mode\n", __func__);
        }
        break;

    case MMC_CMDAT:
        s->cmdat = value & 0x3dff;
        s->active = 0;
        s->cmdreq = 1;
        if (!(value & CMDAT_STOP_TRAN)) {
            s->status &= STAT_CLK_EN;

            if (s->status & STAT_CLK_EN)
                pxa2xx_mmci_wakequeues(s);
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_RESTO:
        s->resp_tout = value & 0x7f;
        break;

    case MMC_RDTO:
        s->read_tout = value & 0xffff;
        break;

    case MMC_BLKLEN:
        s->blklen = value & 0xfff;
        break;

    case MMC_NUMBLK:
        s->numblk = value & 0xffff;
        break;

    case MMC_PRTBUF:
        if (value & PRTBUF_PRT_BUF) {
            s->tx_start ^= 32;
            s->tx_len = 0;
        }
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_I_MASK:
        s->intmask = value & 0x1fff;
        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CMD:
        s->cmd = value & 0x3f;
        break;

    case MMC_ARGH:
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case MMC_ARGL:
        s->arg &= 0xffff0000;
        s->arg |= value & 0x0000ffff;
        break;

    case MMC_TXFIFO:
        while (size-- && s->tx_len < 0x20)
            s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
                    (value >> (size << 3)) & 0xff;
        s->intreq &= ~INT_TXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_RDWAIT:
    case MMC_BLKS_REM:
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect reg 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
    }
}

static const MemoryRegionOps pxa2xx_mmci_ops = {
    .read = pxa2xx_mmci_read,
    .write = pxa2xx_mmci_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
                hwaddr base,
                qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
{
    DeviceState *dev;
    SysBusDevice *sbd;

    dev = qdev_new(TYPE_PXA2XX_MMCI);
    sbd = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sbd, 0, base);
    sysbus_connect_irq(sbd, 0, irq);
    qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
    qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
    sysbus_realize_and_unref(sbd, &error_fatal);

    return PXA2XX_MMCI(dev);
}

static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->inserted, inserted);
}

static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->readonly, readonly);
}

void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                          qemu_irq coverswitch)
{
    DeviceState *dev = DEVICE(s);

    s->readonly = readonly;
    s->inserted = coverswitch;

    pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
    pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
}

static void pxa2xx_mmci_reset(DeviceState *d)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(d);

    s->status = 0;
    s->clkrt = 0;
    s->spi = 0;
    s->cmdat = 0;
    s->resp_tout = 0;
    s->read_tout = 0;
    s->blklen = 0;
    s->numblk = 0;
    s->intmask = 0;
    s->intreq = 0;
    s->cmd = 0;
    s->arg = 0;
    s->active = 0;
    s->bytesleft = 0;
    s->tx_start = 0;
    s->tx_len = 0;
    s->rx_start = 0;
    s->rx_len = 0;
    s->resp_len = 0;
    s->cmdreq = 0;
    memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
    memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
}

static void pxa2xx_mmci_instance_init(Object *obj)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
                          "pxa2xx-mmci", 0x00100000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
    qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
                        TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
}

static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_pxa2xx_mmci;
    dc->reset = pxa2xx_mmci_reset;
}

static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
{
    SDBusClass *sbc = SD_BUS_CLASS(klass);

    sbc->set_inserted = pxa2xx_mmci_set_inserted;
    sbc->set_readonly = pxa2xx_mmci_set_readonly;
}

static const TypeInfo pxa2xx_mmci_info = {
    .name = TYPE_PXA2XX_MMCI,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxMMCIState),
    .instance_init = pxa2xx_mmci_instance_init,
    .class_init = pxa2xx_mmci_class_init,
};

static const TypeInfo pxa2xx_mmci_bus_info = {
    .name = TYPE_PXA2XX_MMCI_BUS,
    .parent = TYPE_SD_BUS,
    .instance_size = sizeof(SDBus),
    .class_init = pxa2xx_mmci_bus_class_init,
};

static void pxa2xx_mmci_register_types(void)
{
    type_register_static(&pxa2xx_mmci_info);
    type_register_static(&pxa2xx_mmci_bus_info);
}

type_init(pxa2xx_mmci_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPLv2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
a171fe39 AZ	11	*/
a171fe39 AZ	12
8ef94f0b	13	#include "qemu/osdep.h"
da34e65c	14	#include "qapi/error.h"
64552b6b	15	#include "hw/irq.h"
7a9468c9	16	#include "hw/sysbus.h"
d6454270	17	#include "migration/vmstate.h"
0d09e41a	18	#include "hw/arm/pxa.h"
e3382ef0	19	#include "hw/sd/sd.h"
7a9468c9	20	#include "hw/qdev-properties.h"
487b406a	21	#include "qemu/log.h"
0b8fa32f	22	#include "qemu/module.h"
487b406a	23	#include "trace.h"
db1015e9	24	#include "qom/object.h"
7a9468c9	25
a9563e75	26	#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
fa34a3c5 EH	27	/* This is reusing the SDBus typedef from SD_BUS */
	28	DECLARE_INSTANCE_CHECKER(SDBus, PXA2XX_MMCI_BUS,
	29	TYPE_PXA2XX_MMCI_BUS)
a9563e75	30
bc24a225	31	struct PXA2xxMMCIState {
7a9468c9 PM	32	SysBusDevice parent_obj;
7a9468c9 PM	33
2bf90458	34	MemoryRegion iomem;
a171fe39	35	qemu_irq irq;
2115c019 AZ	36	qemu_irq rx_dma;
2115c019 AZ	37	qemu_irq tx_dma;
a9563e75 PM	38	qemu_irq inserted;
a9563e75 PM	39	qemu_irq readonly;
a171fe39	40
7a9468c9	41	BlockBackend *blk;
a9563e75	42	SDBus sdbus;
a171fe39 AZ	43
	44	uint32_t status;
	45	uint32_t clkrt;
	46	uint32_t spi;
	47	uint32_t cmdat;
	48	uint32_t resp_tout;
	49	uint32_t read_tout;
19d25e0a PM	50	int32_t blklen;
19d25e0a PM	51	int32_t numblk;
a171fe39 AZ	52	uint32_t intmask;
a171fe39 AZ	53	uint32_t intreq;
19d25e0a	54	int32_t cmd;
a171fe39 AZ	55	uint32_t arg;
a171fe39 AZ	56
19d25e0a PM	57	int32_t active;
19d25e0a PM	58	int32_t bytesleft;
a171fe39	59	uint8_t tx_fifo[64];
19d25e0a PM	60	uint32_t tx_start;
19d25e0a PM	61	uint32_t tx_len;
a171fe39	62	uint8_t rx_fifo[32];
19d25e0a PM	63	uint32_t rx_start;
19d25e0a PM	64	uint32_t rx_len;
a171fe39	65	uint16_t resp_fifo[9];
19d25e0a	66	uint32_t resp_len;
a171fe39	67
19d25e0a PM	68	int32_t cmdreq;
	69	};
	70
	71	static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
	72	{
	73	PXA2xxMMCIState *s = opaque;
	74
	75	return s->tx_start < ARRAY_SIZE(s->tx_fifo)
	76	&& s->rx_start < ARRAY_SIZE(s->rx_fifo)
	77	&& s->tx_len <= ARRAY_SIZE(s->tx_fifo)
	78	&& s->rx_len <= ARRAY_SIZE(s->rx_fifo)
	79	&& s->resp_len <= ARRAY_SIZE(s->resp_fifo);
	80	}
	81
	82
	83	static const VMStateDescription vmstate_pxa2xx_mmci = {
	84	.name = "pxa2xx-mmci",
	85	.version_id = 2,
	86	.minimum_version_id = 2,
	87	.fields = (VMStateField[]) {
	88	VMSTATE_UINT32(status, PXA2xxMMCIState),
	89	VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
	90	VMSTATE_UINT32(spi, PXA2xxMMCIState),
	91	VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
	92	VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
	93	VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
	94	VMSTATE_INT32(blklen, PXA2xxMMCIState),
	95	VMSTATE_INT32(numblk, PXA2xxMMCIState),
	96	VMSTATE_UINT32(intmask, PXA2xxMMCIState),
	97	VMSTATE_UINT32(intreq, PXA2xxMMCIState),
	98	VMSTATE_INT32(cmd, PXA2xxMMCIState),
	99	VMSTATE_UINT32(arg, PXA2xxMMCIState),
	100	VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
	101	VMSTATE_INT32(active, PXA2xxMMCIState),
	102	VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
	103	VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
	104	VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
	105	VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
	106	VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
	107	VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
	108	VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
	109	VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
	110	VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
	111	VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
	112	VMSTATE_END_OF_LIST()
	113	}
a171fe39 AZ	114	};
	115
	116	#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
	117	#define MMC_STAT 0x04 /* MMC Status register */
	118	#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
	119	#define MMC_SPI 0x0c /* MMC SPI Mode register */
	120	#define MMC_CMDAT 0x10 /* MMC Command/Data register */
	121	#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
	122	#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
	123	#define MMC_BLKLEN 0x1c /* MMC Block Length register */
	124	#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
	125	#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
	126	#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
	127	#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
	128	#define MMC_CMD 0x30 /* MMC Command register */
	129	#define MMC_ARGH 0x34 /* MMC Argument High register */
	130	#define MMC_ARGL 0x38 /* MMC Argument Low register */
	131	#define MMC_RES 0x3c /* MMC Response FIFO */
	132	#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
	133	#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
	134	#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
	135	#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
	136
	137	/* Bitfield masks */
	138	#define STRPCL_STOP_CLK (1 << 0)
	139	#define STRPCL_STRT_CLK (1 << 1)
	140	#define STAT_TOUT_RES (1 << 1)
	141	#define STAT_CLK_EN (1 << 8)
	142	#define STAT_DATA_DONE (1 << 11)
	143	#define STAT_PRG_DONE (1 << 12)
	144	#define STAT_END_CMDRES (1 << 13)
	145	#define SPI_SPI_MODE (1 << 0)
	146	#define CMDAT_RES_TYPE (3 << 0)
	147	#define CMDAT_DATA_EN (1 << 2)
	148	#define CMDAT_WR_RD (1 << 3)
	149	#define CMDAT_DMA_EN (1 << 7)
	150	#define CMDAT_STOP_TRAN (1 << 10)
	151	#define INT_DATA_DONE (1 << 0)
	152	#define INT_PRG_DONE (1 << 1)
	153	#define INT_END_CMD (1 << 2)
	154	#define INT_STOP_CMD (1 << 3)
	155	#define INT_CLK_OFF (1 << 4)
	156	#define INT_RXFIFO_REQ (1 << 5)
	157	#define INT_TXFIFO_REQ (1 << 6)
	158	#define INT_TINT (1 << 7)
	159	#define INT_DAT_ERR (1 << 8)
	160	#define INT_RES_ERR (1 << 9)
	161	#define INT_RD_STALLED (1 << 10)
	162	#define INT_SDIO_INT (1 << 11)
	163	#define INT_SDIO_SACK (1 << 12)
	164	#define PRTBUF_PRT_BUF (1 << 0)
	165
	166	/* Route internal interrupt lines to the global IC and DMA */
bc24a225	167	static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
a171fe39 AZ	168	{
	169	uint32_t mask = s->intmask;
	170	if (s->cmdat & CMDAT_DMA_EN) {
	171	mask \|= INT_RXFIFO_REQ \| INT_TXFIFO_REQ;
	172
2115c019 AZ	173	qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
2115c019 AZ	174	qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
a171fe39 AZ	175	}
	176
	177	qemu_set_irq(s->irq, !!(s->intreq & ~mask));
	178	}
	179
bc24a225	180	static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
a171fe39 AZ	181	{
	182	if (!s->active)
	183	return;
	184
	185	if (s->cmdat & CMDAT_WR_RD) {
	186	while (s->bytesleft && s->tx_len) {
39017143	187	sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]);
a171fe39 AZ	188	s->tx_start &= 0x1f;
	189	s->tx_len --;
	190	s->bytesleft --;
	191	}
	192	if (s->bytesleft)
	193	s->intreq \|= INT_TXFIFO_REQ;
	194	} else
	195	while (s->bytesleft && s->rx_len < 32) {
	196	s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
8467f622	197	sdbus_read_byte(&s->sdbus);
a171fe39 AZ	198	s->bytesleft --;
	199	s->intreq \|= INT_RXFIFO_REQ;
	200	}
	201
	202	if (!s->bytesleft) {
	203	s->active = 0;
	204	s->intreq \|= INT_DATA_DONE;
	205	s->status \|= STAT_DATA_DONE;
	206
	207	if (s->cmdat & CMDAT_WR_RD) {
	208	s->intreq \|= INT_PRG_DONE;
	209	s->status \|= STAT_PRG_DONE;
	210	}
	211	}
	212
	213	pxa2xx_mmci_int_update(s);
	214	}
	215
bc24a225	216	static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
a171fe39 AZ	217	{
a171fe39 AZ	218	int rsplen, i;
bc24a225	219	SDRequest request;
a171fe39 AZ	220	uint8_t response[16];
	221
	222	s->active = 1;
	223	s->rx_len = 0;
	224	s->tx_len = 0;
	225	s->cmdreq = 0;
	226
	227	request.cmd = s->cmd;
	228	request.arg = s->arg;
	229	request.crc = 0; /* FIXME */
	230
a9563e75	231	rsplen = sdbus_do_command(&s->sdbus, &request, response);
a171fe39 AZ	232	s->intreq \|= INT_END_CMD;
	233
	234	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	235	switch (s->cmdat & CMDAT_RES_TYPE) {
	236	#define PXAMMCI_RESP(wd, value0, value1) \
	237	s->resp_fifo[(wd) + 0] \|= (value0); \
	238	s->resp_fifo[(wd) + 1] \|= (value1) << 8;
	239	case 0: /* No response */
	240	goto complete;
	241
	242	case 1: /* R1, R4, R5 or R6 */
	243	if (rsplen < 4)
	244	goto timeout;
	245	goto complete;
	246
	247	case 2: /* R2 */
	248	if (rsplen < 16)
	249	goto timeout;
	250	goto complete;
	251
	252	case 3: /* R3 */
	253	if (rsplen < 4)
	254	goto timeout;
	255	goto complete;
	256
	257	complete:
	258	for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
	259	PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
	260	}
	261	s->status \|= STAT_END_CMDRES;
	262
	263	if (!(s->cmdat & CMDAT_DATA_EN))
	264	s->active = 0;
	265	else
	266	s->bytesleft = s->numblk * s->blklen;
	267
	268	s->resp_len = 0;
	269	break;
	270
	271	timeout:
	272	s->active = 0;
	273	s->status \|= STAT_TOUT_RES;
	274	break;
	275	}
	276
	277	pxa2xx_mmci_fifo_update(s);
	278	}
	279
13e1e476	280	static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
a171fe39	281	{
bc24a225	282	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
487b406a	283	uint32_t ret = 0;
a171fe39 AZ	284
	285	switch (offset) {
	286	case MMC_STRPCL:
487b406a	287	break;
a171fe39	288	case MMC_STAT:
487b406a PMD	289	ret = s->status;
487b406a PMD	290	break;
a171fe39	291	case MMC_CLKRT:
487b406a PMD	292	ret = s->clkrt;
487b406a PMD	293	break;
a171fe39	294	case MMC_SPI:
487b406a PMD	295	ret = s->spi;
487b406a PMD	296	break;
a171fe39	297	case MMC_CMDAT:
487b406a PMD	298	ret = s->cmdat;
487b406a PMD	299	break;
a171fe39	300	case MMC_RESTO:
487b406a PMD	301	ret = s->resp_tout;
487b406a PMD	302	break;
a171fe39	303	case MMC_RDTO:
487b406a PMD	304	ret = s->read_tout;
487b406a PMD	305	break;
a171fe39	306	case MMC_BLKLEN:
487b406a PMD	307	ret = s->blklen;
487b406a PMD	308	break;
a171fe39	309	case MMC_NUMBLK:
487b406a PMD	310	ret = s->numblk;
487b406a PMD	311	break;
a171fe39	312	case MMC_PRTBUF:
487b406a	313	break;
a171fe39	314	case MMC_I_MASK:
487b406a PMD	315	ret = s->intmask;
487b406a PMD	316	break;
a171fe39	317	case MMC_I_REG:
487b406a PMD	318	ret = s->intreq;
487b406a PMD	319	break;
a171fe39	320	case MMC_CMD:
487b406a PMD	321	ret = s->cmd \| 0x40;
487b406a PMD	322	break;
a171fe39	323	case MMC_ARGH:
487b406a PMD	324	ret = s->arg >> 16;
487b406a PMD	325	break;
a171fe39	326	case MMC_ARGL:
487b406a PMD	327	ret = s->arg & 0xffff;
487b406a PMD	328	break;
a171fe39	329	case MMC_RES:
487b406a PMD	330	ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
487b406a PMD	331	break;
a171fe39	332	case MMC_RXFIFO:
13e1e476 PM	333	while (size-- && s->rx_len) {
13e1e476 PM	334	ret \|= s->rx_fifo[s->rx_start++] << (size << 3);
a171fe39 AZ	335	s->rx_start &= 0x1f;
	336	s->rx_len --;
	337	}
	338	s->intreq &= ~INT_RXFIFO_REQ;
	339	pxa2xx_mmci_fifo_update(s);
487b406a	340	break;
a171fe39	341	case MMC_RDWAIT:
487b406a	342	break;
a171fe39	343	case MMC_BLKS_REM:
487b406a PMD	344	ret = s->numblk;
487b406a PMD	345	break;
a171fe39	346	default:
487b406a PMD	347	qemu_log_mask(LOG_GUEST_ERROR,
	348	"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
	349	__func__, offset);
a171fe39	350	}
487b406a	351	trace_pxa2xx_mmci_read(size, offset, ret);
a171fe39	352
487b406a	353	return ret;
a171fe39 AZ	354	}
	355
	356	static void pxa2xx_mmci_write(void *opaque,
13e1e476	357	hwaddr offset, uint64_t value, unsigned size)
a171fe39	358	{
bc24a225	359	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39	360
487b406a	361	trace_pxa2xx_mmci_write(size, offset, value);
a171fe39 AZ	362	switch (offset) {
	363	case MMC_STRPCL:
	364	if (value & STRPCL_STRT_CLK) {
	365	s->status \|= STAT_CLK_EN;
	366	s->intreq &= ~INT_CLK_OFF;
	367
	368	if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
	369	s->status &= STAT_CLK_EN;
	370	pxa2xx_mmci_wakequeues(s);
	371	}
	372	}
	373
	374	if (value & STRPCL_STOP_CLK) {
	375	s->status &= ~STAT_CLK_EN;
	376	s->intreq \|= INT_CLK_OFF;
	377	s->active = 0;
	378	}
	379
	380	pxa2xx_mmci_int_update(s);
	381	break;
	382
	383	case MMC_CLKRT:
	384	s->clkrt = value & 7;
	385	break;
	386
	387	case MMC_SPI:
	388	s->spi = value & 0xf;
487b406a PMD	389	if (value & SPI_SPI_MODE) {
	390	qemu_log_mask(LOG_GUEST_ERROR,
	391	"%s: attempted to use card in SPI mode\n", __func__);
	392	}
a171fe39 AZ	393	break;
	394
	395	case MMC_CMDAT:
	396	s->cmdat = value & 0x3dff;
	397	s->active = 0;
	398	s->cmdreq = 1;
	399	if (!(value & CMDAT_STOP_TRAN)) {
	400	s->status &= STAT_CLK_EN;
	401
	402	if (s->status & STAT_CLK_EN)
	403	pxa2xx_mmci_wakequeues(s);
	404	}
	405
	406	pxa2xx_mmci_int_update(s);
	407	break;
	408
	409	case MMC_RESTO:
	410	s->resp_tout = value & 0x7f;
	411	break;
	412
	413	case MMC_RDTO:
	414	s->read_tout = value & 0xffff;
	415	break;
	416
	417	case MMC_BLKLEN:
	418	s->blklen = value & 0xfff;
	419	break;
	420
	421	case MMC_NUMBLK:
	422	s->numblk = value & 0xffff;
	423	break;
	424
	425	case MMC_PRTBUF:
	426	if (value & PRTBUF_PRT_BUF) {
	427	s->tx_start ^= 32;
	428	s->tx_len = 0;
	429	}
	430	pxa2xx_mmci_fifo_update(s);
	431	break;
	432
	433	case MMC_I_MASK:
	434	s->intmask = value & 0x1fff;
	435	pxa2xx_mmci_int_update(s);
	436	break;
	437
	438	case MMC_CMD:
	439	s->cmd = value & 0x3f;
	440	break;
	441
	442	case MMC_ARGH:
	443	s->arg &= 0x0000ffff;
	444	s->arg \|= value << 16;
	445	break;
	446
	447	case MMC_ARGL:
	448	s->arg &= 0xffff0000;
	449	s->arg \|= value & 0x0000ffff;
	450	break;
	451
	452	case MMC_TXFIFO:
13e1e476	453	while (size-- && s->tx_len < 0x20)
a171fe39	454	s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
13e1e476	455	(value >> (size << 3)) & 0xff;
a171fe39 AZ	456	s->intreq &= ~INT_TXFIFO_REQ;
	457	pxa2xx_mmci_fifo_update(s);
	458	break;
	459
	460	case MMC_RDWAIT:
	461	case MMC_BLKS_REM:
	462	break;
	463
	464	default:
487b406a PMD	465	qemu_log_mask(LOG_GUEST_ERROR,
	466	"%s: incorrect reg 0x%02" HWADDR_PRIx " "
	467	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
a171fe39 AZ	468	}
	469	}
	470
2bf90458	471	static const MemoryRegionOps pxa2xx_mmci_ops = {
13e1e476 PM	472	.read = pxa2xx_mmci_read,
13e1e476 PM	473	.write = pxa2xx_mmci_write,
2bf90458	474	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	475	};
a171fe39 AZ	476
2bf90458	477	PXA2xxMMCIState pxa2xx_mmci_init(MemoryRegion sysmem,
a8170e5e	478	hwaddr base,
d7ebca74	479	qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
a171fe39	480	{
d7ebca74	481	DeviceState *dev;
7a9468c9	482	SysBusDevice *sbd;
a171fe39	483
3e80f690	484	dev = qdev_new(TYPE_PXA2XX_MMCI);
7a9468c9 PM	485	sbd = SYS_BUS_DEVICE(dev);
	486	sysbus_mmio_map(sbd, 0, base);
	487	sysbus_connect_irq(sbd, 0, irq);
	488	qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
	489	qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
3c6ef471	490	sysbus_realize_and_unref(sbd, &error_fatal);
a9563e75	491
a0e63983	492	return PXA2XX_MMCI(dev);
a171fe39 AZ	493	}
a171fe39 AZ	494
a9563e75 PM	495	static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
	496	{
	497	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	498
	499	qemu_set_irq(s->inserted, inserted);
	500	}
	501
	502	static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
	503	{
	504	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	505
	506	qemu_set_irq(s->readonly, readonly);
	507	}
	508
bc24a225	509	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
7a9468c9	510	qemu_irq coverswitch)
a171fe39	511	{
a9563e75 PM	512	DeviceState *dev = DEVICE(s);
	513
	514	s->readonly = readonly;
	515	s->inserted = coverswitch;
	516
	517	pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
	518	pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
a171fe39	519	}
7a9468c9	520
6002915e PM	521	static void pxa2xx_mmci_reset(DeviceState *d)
	522	{
	523	PXA2xxMMCIState *s = PXA2XX_MMCI(d);
	524
	525	s->status = 0;
	526	s->clkrt = 0;
	527	s->spi = 0;
	528	s->cmdat = 0;
	529	s->resp_tout = 0;
	530	s->read_tout = 0;
	531	s->blklen = 0;
	532	s->numblk = 0;
	533	s->intmask = 0;
	534	s->intreq = 0;
	535	s->cmd = 0;
	536	s->arg = 0;
	537	s->active = 0;
	538	s->bytesleft = 0;
	539	s->tx_start = 0;
	540	s->tx_len = 0;
	541	s->rx_start = 0;
	542	s->rx_len = 0;
	543	s->resp_len = 0;
	544	s->cmdreq = 0;
	545	memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
	546	memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
	547	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	548	}
	549
7a9468c9 PM	550	static void pxa2xx_mmci_instance_init(Object *obj)
	551	{
	552	PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
	553	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	554	DeviceState *dev = DEVICE(obj);
	555
	556	memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
	557	"pxa2xx-mmci", 0x00100000);
	558	sysbus_init_mmio(sbd, &s->iomem);
	559	sysbus_init_irq(sbd, &s->irq);
	560	qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
	561	qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
	562
a9563e75 PM	563	qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
	564	TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
	565	}
	566
19d25e0a PM	567	static void pxa2xx_mmci_class_init(ObjectClass klass, void data)
	568	{
	569	DeviceClass *dc = DEVICE_CLASS(klass);
	570
	571	dc->vmsd = &vmstate_pxa2xx_mmci;
6002915e	572	dc->reset = pxa2xx_mmci_reset;
19d25e0a PM	573	}
19d25e0a PM	574
a9563e75 PM	575	static void pxa2xx_mmci_bus_class_init(ObjectClass klass, void data)
	576	{
	577	SDBusClass *sbc = SD_BUS_CLASS(klass);
	578
	579	sbc->set_inserted = pxa2xx_mmci_set_inserted;
	580	sbc->set_readonly = pxa2xx_mmci_set_readonly;
7a9468c9 PM	581	}
	582
	583	static const TypeInfo pxa2xx_mmci_info = {
	584	.name = TYPE_PXA2XX_MMCI,
	585	.parent = TYPE_SYS_BUS_DEVICE,
	586	.instance_size = sizeof(PXA2xxMMCIState),
	587	.instance_init = pxa2xx_mmci_instance_init,
19d25e0a	588	.class_init = pxa2xx_mmci_class_init,
7a9468c9 PM	589	};
7a9468c9 PM	590
a9563e75 PM	591	static const TypeInfo pxa2xx_mmci_bus_info = {
	592	.name = TYPE_PXA2XX_MMCI_BUS,
	593	.parent = TYPE_SD_BUS,
	594	.instance_size = sizeof(SDBus),
	595	.class_init = pxa2xx_mmci_bus_class_init,
	596	};
	597
7a9468c9 PM	598	static void pxa2xx_mmci_register_types(void)
	599	{
	600	type_register_static(&pxa2xx_mmci_info);
a9563e75	601	type_register_static(&pxa2xx_mmci_bus_info);
7a9468c9 PM	602	}
	603
	604	type_init(pxa2xx_mmci_register_types)