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sdhci: use PRIx64 for uint64_t type
[thirdparty/qemu.git] / hw / sd / sdhci.c
CommitLineData
d7dfca08
IM		 1/*
2 * SD Association Host Standard Specification v2.0 controller emulation
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
7 *
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
be9c5dde 25#include <inttypes.h>
83c9f4ca 26#include "hw/hw.h"
fa1d36df 27#include "sysemu/block-backend.h"
d7dfca08
IM		 28#include "sysemu/blockdev.h"
29#include "sysemu/dma.h"
30#include "qemu/timer.h"
d7dfca08
IM		 31#include "qemu/bitops.h"
32
47b43a1f 33#include "sdhci.h"
d7dfca08
IM		 34
35/* host controller debug messages */
36#ifndef SDHC_DEBUG
37#define SDHC_DEBUG 0
38#endif
39
40#if SDHC_DEBUG == 0
41 #define DPRINT_L1(fmt, args...) do { } while (0)
42 #define DPRINT_L2(fmt, args...) do { } while (0)
43 #define ERRPRINT(fmt, args...) do { } while (0)
44#elif SDHC_DEBUG == 1
45 #define DPRINT_L1(fmt, args...) \
46 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
47 #define DPRINT_L2(fmt, args...) do { } while (0)
48 #define ERRPRINT(fmt, args...) \
49 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
50#else
51 #define DPRINT_L1(fmt, args...) \
52 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
53 #define DPRINT_L2(fmt, args...) \
54 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0)
55 #define ERRPRINT(fmt, args...) \
56 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0)
57#endif
58
59/* Default SD/MMC host controller features information, which will be
60 * presented in CAPABILITIES register of generic SD host controller at reset.
61 * If not stated otherwise:
62 * 0 - not supported, 1 - supported, other - prohibited.
63 */
64#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
65#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
66#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
67#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
68#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
69#define SDHC_CAPAB_SDMA 1ul /* SDMA support */
70#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
71#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
72#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
73/* Maximum host controller R/W buffers size
74 * Possible values: 512, 1024, 2048 bytes */
75#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
76/* Maximum clock frequency for SDclock in MHz
77 * value in range 10-63 MHz, 0 - not defined */
c7ff8daa 78#define SDHC_CAPAB_BASECLKFREQ 52ul
d7dfca08
IM		 79#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
80/* Timeout clock frequency 1-63, 0 - not defined */
c7ff8daa 81#define SDHC_CAPAB_TOCLKFREQ 52ul
d7dfca08
IM		 82
83/* Now check all parameters and calculate CAPABILITIES REGISTER value */
84#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
85 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
86 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
87 SDHC_CAPAB_TOUNIT > 1
88#error Capabilities features can have value 0 or 1 only!
89#endif
90
91#if SDHC_CAPAB_MAXBLOCKLENGTH == 512
92#define MAX_BLOCK_LENGTH 0ul
93#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
94#define MAX_BLOCK_LENGTH 1ul
95#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
96#define MAX_BLOCK_LENGTH 2ul
97#else
98#error Max host controller block size can have value 512, 1024 or 2048 only!
99#endif
100
101#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
102 SDHC_CAPAB_BASECLKFREQ > 63
103#error SDclock frequency can have value in range 0, 10-63 only!
104#endif
105
106#if SDHC_CAPAB_TOCLKFREQ > 63
107#error Timeout clock frequency can have value in range 0-63 only!
108#endif
109
110#define SDHC_CAPAB_REG_DEFAULT \
111 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
112 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
113 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
114 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
115 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
116 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
117 (SDHC_CAPAB_TOCLKFREQ))
118
119#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
120
121static uint8_t sdhci_slotint(SDHCIState *s)
122{
123 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) ||
124 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) ||
125 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
126}
127
128static inline void sdhci_update_irq(SDHCIState *s)
129{
130 qemu_set_irq(s->irq, sdhci_slotint(s));
131}
132
133static void sdhci_raise_insertion_irq(void *opaque)
134{
135 SDHCIState *s = (SDHCIState *)opaque;
136
137 if (s->norintsts & SDHC_NIS_REMOVE) {
bc72ad67
AB		 138 timer_mod(s->insert_timer,
139 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 140 } else {
141 s->prnsts = 0x1ff0000;
142 if (s->norintstsen & SDHC_NISEN_INSERT) {
143 s->norintsts |= SDHC_NIS_INSERT;
144 }
145 sdhci_update_irq(s);
146 }
147}
148
149static void sdhci_insert_eject_cb(void *opaque, int irq, int level)
150{
151 SDHCIState *s = (SDHCIState *)opaque;
152 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject");
153
154 if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
155 /* Give target some time to notice card ejection */
bc72ad67
AB		 156 timer_mod(s->insert_timer,
157 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
d7dfca08
IM		 158 } else {
159 if (level) {
160 s->prnsts = 0x1ff0000;
161 if (s->norintstsen & SDHC_NISEN_INSERT) {
162 s->norintsts |= SDHC_NIS_INSERT;
163 }
164 } else {
165 s->prnsts = 0x1fa0000;
166 s->pwrcon &= ~SDHC_POWER_ON;
167 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
168 if (s->norintstsen & SDHC_NISEN_REMOVE) {
169 s->norintsts |= SDHC_NIS_REMOVE;
170 }
171 }
172 sdhci_update_irq(s);
173 }
174}
175
176static void sdhci_card_readonly_cb(void *opaque, int irq, int level)
177{
178 SDHCIState *s = (SDHCIState *)opaque;
179
180 if (level) {
181 s->prnsts &= ~SDHC_WRITE_PROTECT;
182 } else {
183 /* Write enabled */
184 s->prnsts |= SDHC_WRITE_PROTECT;
185 }
186}
187
188static void sdhci_reset(SDHCIState *s)
189{
bc72ad67
AB		 190 timer_del(s->insert_timer);
191 timer_del(s->transfer_timer);
d7dfca08
IM		 192 /* Set all registers to 0. Capabilities registers are not cleared
193 * and assumed to always preserve their value, given to them during
194 * initialization */
195 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
196
197 sd_set_cb(s->card, s->ro_cb, s->eject_cb);
198 s->data_count = 0;
199 s->stopped_state = sdhc_not_stopped;
200}
201
d368ba43 202static void sdhci_data_transfer(void *opaque);
d7dfca08
IM		 203
204static void sdhci_send_command(SDHCIState *s)
205{
206 SDRequest request;
207 uint8_t response[16];
208 int rlen;
209
210 s->errintsts = 0;
211 s->acmd12errsts = 0;
212 request.cmd = s->cmdreg >> 8;
213 request.arg = s->argument;
214 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
215 rlen = sd_do_command(s->card, &request, response);
216
217 if (s->cmdreg & SDHC_CMD_RESPONSE) {
218 if (rlen == 4) {
219 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
220 (response[2] << 8) | response[3];
221 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
222 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]);
223 } else if (rlen == 16) {
224 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
225 (response[13] << 8) | response[14];
226 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) |
227 (response[9] << 8) | response[10];
228 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) |
229 (response[5] << 8) | response[6];
230 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
231 response[2];
232 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
233 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
234 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]);
235 } else {
236 ERRPRINT("Timeout waiting for command response\n");
237 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
238 s->errintsts |= SDHC_EIS_CMDTIMEOUT;
239 s->norintsts |= SDHC_NIS_ERR;
240 }
241 }
242
243 if ((s->norintstsen & SDHC_NISEN_TRSCMP) &&
244 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
245 s->norintsts |= SDHC_NIS_TRSCMP;
246 }
247 } else if (rlen != 0 && (s->errintstsen & SDHC_EISEN_CMDIDX)) {
248 s->errintsts |= SDHC_EIS_CMDIDX;
249 s->norintsts |= SDHC_NIS_ERR;
250 }
251
252 if (s->norintstsen & SDHC_NISEN_CMDCMP) {
253 s->norintsts |= SDHC_NIS_CMDCMP;
254 }
255
256 sdhci_update_irq(s);
257
258 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
656f416c 259 s->data_count = 0;
d368ba43 260 sdhci_data_transfer(s);
d7dfca08
IM		 261 }
262}
263
264static void sdhci_end_transfer(SDHCIState *s)
265{
266 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
267 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
268 SDRequest request;
269 uint8_t response[16];
270
271 request.cmd = 0x0C;
272 request.arg = 0;
273 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
274 sd_do_command(s->card, &request, response);
275 /* Auto CMD12 response goes to the upper Response register */
276 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
277 (response[2] << 8) | response[3];
278 }
279
280 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE |
281 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT |
282 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE);
283
284 if (s->norintstsen & SDHC_NISEN_TRSCMP) {
285 s->norintsts |= SDHC_NIS_TRSCMP;
286 }
287
288 sdhci_update_irq(s);
289}
290
291/*
292 * Programmed i/o data transfer
293 */
294
295/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
296static void sdhci_read_block_from_card(SDHCIState *s)
297{
298 int index = 0;
299
300 if ((s->trnmod & SDHC_TRNS_MULTI) &&
301 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
302 return;
303 }
304
305 for (index = 0; index < (s->blksize & 0x0fff); index++) {
306 s->fifo_buffer[index] = sd_read_data(s->card);
307 }
308
309 /* New data now available for READ through Buffer Port Register */
310 s->prnsts |= SDHC_DATA_AVAILABLE;
311 if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
312 s->norintsts |= SDHC_NIS_RBUFRDY;
313 }
314
315 /* Clear DAT line active status if that was the last block */
316 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
317 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
318 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
319 }
320
321 /* If stop at block gap request was set and it's not the last block of
322 * data - generate Block Event interrupt */
323 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
324 s->blkcnt != 1) {
325 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
326 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
327 s->norintsts |= SDHC_EIS_BLKGAP;
328 }
329 }
330
331 sdhci_update_irq(s);
332}
333
334/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
335static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
336{
337 uint32_t value = 0;
338 int i;
339
340 /* first check that a valid data exists in host controller input buffer */
341 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
342 ERRPRINT("Trying to read from empty buffer\n");
343 return 0;
344 }
345
346 for (i = 0; i < size; i++) {
347 value |= s->fifo_buffer[s->data_count] << i * 8;
348 s->data_count++;
349 /* check if we've read all valid data (blksize bytes) from buffer */
350 if ((s->data_count) >= (s->blksize & 0x0fff)) {
351 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
352 s->data_count);
353 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
354 s->data_count = 0; /* next buff read must start at position [0] */
355
356 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
357 s->blkcnt--;
358 }
359
360 /* if that was the last block of data */
361 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
362 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) ||
363 /* stop at gap request */
364 (s->stopped_state == sdhc_gap_read &&
365 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
d368ba43 366 sdhci_end_transfer(s);
d7dfca08 367 } else { /* if there are more data, read next block from card */
d368ba43 368 sdhci_read_block_from_card(s);
d7dfca08
IM		 369 }
370 break;
371 }
372 }
373
374 return value;
375}
376
377/* Write data from host controller FIFO to card */
378static void sdhci_write_block_to_card(SDHCIState *s)
379{
380 int index = 0;
381
382 if (s->prnsts & SDHC_SPACE_AVAILABLE) {
383 if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
384 s->norintsts |= SDHC_NIS_WBUFRDY;
385 }
386 sdhci_update_irq(s);
387 return;
388 }
389
390 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
391 if (s->blkcnt == 0) {
392 return;
393 } else {
394 s->blkcnt--;
395 }
396 }
397
398 for (index = 0; index < (s->blksize & 0x0fff); index++) {
399 sd_write_data(s->card, s->fifo_buffer[index]);
400 }
401
402 /* Next data can be written through BUFFER DATORT register */
403 s->prnsts |= SDHC_SPACE_AVAILABLE;
d7dfca08
IM		 404
405 /* Finish transfer if that was the last block of data */
406 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 ||
407 ((s->trnmod & SDHC_TRNS_MULTI) &&
408 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
d368ba43 409 sdhci_end_transfer(s);
dcdb4cd8
PC		 410 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
411 s->norintsts |= SDHC_NIS_WBUFRDY;
d7dfca08
IM		 412 }
413
414 /* Generate Block Gap Event if requested and if not the last block */
415 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
416 s->blkcnt > 0) {
417 s->prnsts &= ~SDHC_DOING_WRITE;
418 if (s->norintstsen & SDHC_EISEN_BLKGAP) {
419 s->norintsts |= SDHC_EIS_BLKGAP;
420 }
d368ba43 421 sdhci_end_transfer(s);
d7dfca08
IM		 422 }
423
424 sdhci_update_irq(s);
425}
426
427/* Write @size bytes of @value data to host controller @s Buffer Data Port
428 * register */
429static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
430{
431 unsigned i;
432
433 /* Check that there is free space left in a buffer */
434 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
435 ERRPRINT("Can't write to data buffer: buffer full\n");
436 return;
437 }
438
439 for (i = 0; i < size; i++) {
440 s->fifo_buffer[s->data_count] = value & 0xFF;
441 s->data_count++;
442 value >>= 8;
443 if (s->data_count >= (s->blksize & 0x0fff)) {
444 DPRINT_L2("write buffer filled with %u bytes of data\n",
445 s->data_count);
446 s->data_count = 0;
447 s->prnsts &= ~SDHC_SPACE_AVAILABLE;
448 if (s->prnsts & SDHC_DOING_WRITE) {
d368ba43 449 sdhci_write_block_to_card(s);
d7dfca08
IM		 450 }
451 }
452 }
453}
454
455/*
456 * Single DMA data transfer
457 */
458
459/* Multi block SDMA transfer */
460static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
461{
462 bool page_aligned = false;
463 unsigned int n, begin;
464 const uint16_t block_size = s->blksize & 0x0fff;
465 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
466 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
467
468 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
469 * possible stop at page boundary if initial address is not page aligned,
470 * allow them to work properly */
471 if ((s->sdmasysad % boundary_chk) == 0) {
472 page_aligned = true;
473 }
474
475 if (s->trnmod & SDHC_TRNS_READ) {
476 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
477 SDHC_DAT_LINE_ACTIVE;
478 while (s->blkcnt) {
479 if (s->data_count == 0) {
480 for (n = 0; n < block_size; n++) {
481 s->fifo_buffer[n] = sd_read_data(s->card);
482 }
483 }
484 begin = s->data_count;
485 if (((boundary_count + begin) < block_size) && page_aligned) {
486 s->data_count = boundary_count + begin;
487 boundary_count = 0;
488 } else {
489 s->data_count = block_size;
490 boundary_count -= block_size - begin;
491 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
492 s->blkcnt--;
493 }
494 }
df32fd1c 495 dma_memory_write(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 496 &s->fifo_buffer[begin], s->data_count - begin);
497 s->sdmasysad += s->data_count - begin;
498 if (s->data_count == block_size) {
499 s->data_count = 0;
500 }
501 if (page_aligned && boundary_count == 0) {
502 break;
503 }
504 }
505 } else {
506 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT |
507 SDHC_DAT_LINE_ACTIVE;
508 while (s->blkcnt) {
509 begin = s->data_count;
510 if (((boundary_count + begin) < block_size) && page_aligned) {
511 s->data_count = boundary_count + begin;
512 boundary_count = 0;
513 } else {
514 s->data_count = block_size;
515 boundary_count -= block_size - begin;
516 }
df32fd1c 517 dma_memory_read(&address_space_memory, s->sdmasysad,
d7dfca08
IM		 518 &s->fifo_buffer[begin], s->data_count);
519 s->sdmasysad += s->data_count - begin;
520 if (s->data_count == block_size) {
521 for (n = 0; n < block_size; n++) {
522 sd_write_data(s->card, s->fifo_buffer[n]);
523 }
524 s->data_count = 0;
525 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
526 s->blkcnt--;
527 }
528 }
529 if (page_aligned && boundary_count == 0) {
530 break;
531 }
532 }
533 }
534
535 if (s->blkcnt == 0) {
d368ba43 536 sdhci_end_transfer(s);
d7dfca08
IM		 537 } else {
538 if (s->norintstsen & SDHC_NISEN_DMA) {
539 s->norintsts |= SDHC_NIS_DMA;
540 }
541 sdhci_update_irq(s);
542 }
543}
544
545/* single block SDMA transfer */
546
547static void sdhci_sdma_transfer_single_block(SDHCIState *s)
548{
549 int n;
550 uint32_t datacnt = s->blksize & 0x0fff;
551
552 if (s->trnmod & SDHC_TRNS_READ) {
553 for (n = 0; n < datacnt; n++) {
554 s->fifo_buffer[n] = sd_read_data(s->card);
555 }
df32fd1c 556 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 557 datacnt);
558 } else {
df32fd1c 559 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
d7dfca08
IM		 560 datacnt);
561 for (n = 0; n < datacnt; n++) {
562 sd_write_data(s->card, s->fifo_buffer[n]);
563 }
564 }
565
566 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
567 s->blkcnt--;
568 }
569
d368ba43 570 sdhci_end_transfer(s);
d7dfca08
IM		 571}
572
573typedef struct ADMADescr {
574 hwaddr addr;
575 uint16_t length;
576 uint8_t attr;
577 uint8_t incr;
578} ADMADescr;
579
580static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
581{
582 uint32_t adma1 = 0;
583 uint64_t adma2 = 0;
584 hwaddr entry_addr = (hwaddr)s->admasysaddr;
585 switch (SDHC_DMA_TYPE(s->hostctl)) {
586 case SDHC_CTRL_ADMA2_32:
df32fd1c 587 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
d7dfca08
IM		 588 sizeof(adma2));
589 adma2 = le64_to_cpu(adma2);
590 /* The spec does not specify endianness of descriptor table.
591 * We currently assume that it is LE.
592 */
593 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
594 dscr->length = (uint16_t)extract64(adma2, 16, 16);
595 dscr->attr = (uint8_t)extract64(adma2, 0, 7);
596 dscr->incr = 8;
597 break;
598 case SDHC_CTRL_ADMA1_32:
df32fd1c 599 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
d7dfca08
IM		 600 sizeof(adma1));
601 adma1 = le32_to_cpu(adma1);
602 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
603 dscr->attr = (uint8_t)extract32(adma1, 0, 7);
604 dscr->incr = 4;
605 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
606 dscr->length = (uint16_t)extract32(adma1, 12, 16);
607 } else {
608 dscr->length = 4096;
609 }
610 break;
611 case SDHC_CTRL_ADMA2_64:
df32fd1c 612 dma_memory_read(&address_space_memory, entry_addr,
d7dfca08 613 (uint8_t *)(&dscr->attr), 1);
df32fd1c 614 dma_memory_read(&address_space_memory, entry_addr + 2,
d7dfca08
IM		 615 (uint8_t *)(&dscr->length), 2);
616 dscr->length = le16_to_cpu(dscr->length);
df32fd1c 617 dma_memory_read(&address_space_memory, entry_addr + 4,
d7dfca08
IM		 618 (uint8_t *)(&dscr->addr), 8);
619 dscr->attr = le64_to_cpu(dscr->attr);
620 dscr->attr &= 0xfffffff8;
621 dscr->incr = 12;
622 break;
623 }
624}
625
626/* Advanced DMA data transfer */
627
628static void sdhci_do_adma(SDHCIState *s)
629{
630 unsigned int n, begin, length;
631 const uint16_t block_size = s->blksize & 0x0fff;
632 ADMADescr dscr;
633 int i;
634
635 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
636 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
637
638 get_adma_description(s, &dscr);
639 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n",
640 dscr.addr, dscr.length, dscr.attr);
641
642 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
643 /* Indicate that error occurred in ST_FDS state */
644 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
645 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS;
646
647 /* Generate ADMA error interrupt */
648 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
649 s->errintsts |= SDHC_EIS_ADMAERR;
650 s->norintsts |= SDHC_NIS_ERR;
651 }
652
653 sdhci_update_irq(s);
654 return;
655 }
656
657 length = dscr.length ? dscr.length : 65536;
658
659 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
660 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
661
662 if (s->trnmod & SDHC_TRNS_READ) {
663 while (length) {
664 if (s->data_count == 0) {
665 for (n = 0; n < block_size; n++) {
666 s->fifo_buffer[n] = sd_read_data(s->card);
667 }
668 }
669 begin = s->data_count;
670 if ((length + begin) < block_size) {
671 s->data_count = length + begin;
672 length = 0;
673 } else {
674 s->data_count = block_size;
675 length -= block_size - begin;
676 }
df32fd1c 677 dma_memory_write(&address_space_memory, dscr.addr,
d7dfca08
IM		 678 &s->fifo_buffer[begin],
679 s->data_count - begin);
680 dscr.addr += s->data_count - begin;
681 if (s->data_count == block_size) {
682 s->data_count = 0;
683 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
684 s->blkcnt--;
685 if (s->blkcnt == 0) {
686 break;
687 }
688 }
689 }
690 }
691 } else {
692 while (length) {
693 begin = s->data_count;
694 if ((length + begin) < block_size) {
695 s->data_count = length + begin;
696 length = 0;
697 } else {
698 s->data_count = block_size;
699 length -= block_size - begin;
700 }
df32fd1c 701 dma_memory_read(&address_space_memory, dscr.addr,
9db11cef
PC		 702 &s->fifo_buffer[begin],
703 s->data_count - begin);
d7dfca08
IM		 704 dscr.addr += s->data_count - begin;
705 if (s->data_count == block_size) {
706 for (n = 0; n < block_size; n++) {
707 sd_write_data(s->card, s->fifo_buffer[n]);
708 }
709 s->data_count = 0;
710 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
711 s->blkcnt--;
712 if (s->blkcnt == 0) {
713 break;
714 }
715 }
716 }
717 }
718 }
719 s->admasysaddr += dscr.incr;
720 break;
721 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
722 s->admasysaddr = dscr.addr;
be9c5dde
SPB		 723 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n",
724 s->admasysaddr);
d7dfca08
IM		 725 break;
726 default:
727 s->admasysaddr += dscr.incr;
728 break;
729 }
730
1d32c26f 731 if (dscr.attr & SDHC_ADMA_ATTR_INT) {
be9c5dde
SPB		 732 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n",
733 s->admasysaddr);
1d32c26f
PC		 734 if (s->norintstsen & SDHC_NISEN_DMA) {
735 s->norintsts |= SDHC_NIS_DMA;
736 }
737
738 sdhci_update_irq(s);
739 }
740
d7dfca08
IM		 741 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
742 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
743 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
744 DPRINT_L2("ADMA transfer completed\n");
745 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
746 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
747 s->blkcnt != 0)) {
748 ERRPRINT("SD/MMC host ADMA length mismatch\n");
749 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
750 SDHC_ADMAERR_STATE_ST_TFR;
751 if (s->errintstsen & SDHC_EISEN_ADMAERR) {
752 ERRPRINT("Set ADMA error flag\n");
753 s->errintsts |= SDHC_EIS_ADMAERR;
754 s->norintsts |= SDHC_NIS_ERR;
755 }
756
757 sdhci_update_irq(s);
758 }
d368ba43 759 sdhci_end_transfer(s);
d7dfca08
IM		 760 return;
761 }
762
d7dfca08
IM		 763 }
764
085d8134 765 /* we have unfinished business - reschedule to continue ADMA */
bc72ad67
AB		 766 timer_mod(s->transfer_timer,
767 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
d7dfca08
IM		 768}
769
770/* Perform data transfer according to controller configuration */
771
d368ba43 772static void sdhci_data_transfer(void *opaque)
d7dfca08 773{
d368ba43 774 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 775
776 if (s->trnmod & SDHC_TRNS_DMA) {
777 switch (SDHC_DMA_TYPE(s->hostctl)) {
778 case SDHC_CTRL_SDMA:
779 if ((s->trnmod & SDHC_TRNS_MULTI) &&
780 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
781 break;
782 }
783
784 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
d368ba43 785 sdhci_sdma_transfer_single_block(s);
d7dfca08 786 } else {
d368ba43 787 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 788 }
789
790 break;
791 case SDHC_CTRL_ADMA1_32:
792 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
793 ERRPRINT("ADMA1 not supported\n");
794 break;
795 }
796
d368ba43 797 sdhci_do_adma(s);
d7dfca08
IM		 798 break;
799 case SDHC_CTRL_ADMA2_32:
800 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
801 ERRPRINT("ADMA2 not supported\n");
802 break;
803 }
804
d368ba43 805 sdhci_do_adma(s);
d7dfca08
IM		 806 break;
807 case SDHC_CTRL_ADMA2_64:
808 if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
809 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
810 ERRPRINT("64 bit ADMA not supported\n");
811 break;
812 }
813
d368ba43 814 sdhci_do_adma(s);
d7dfca08
IM		 815 break;
816 default:
817 ERRPRINT("Unsupported DMA type\n");
818 break;
819 }
820 } else {
821 if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) {
822 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT |
823 SDHC_DAT_LINE_ACTIVE;
d368ba43 824 sdhci_read_block_from_card(s);
d7dfca08
IM		 825 } else {
826 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE |
827 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT;
d368ba43 828 sdhci_write_block_to_card(s);
d7dfca08
IM		 829 }
830 }
831}
832
833static bool sdhci_can_issue_command(SDHCIState *s)
834{
835 if (!SDHC_CLOCK_IS_ON(s->clkcon) || !(s->pwrcon & SDHC_POWER_ON) ||
836 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) &&
837 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) ||
838 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
839 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
840 return false;
841 }
842
843 return true;
844}
845
846/* The Buffer Data Port register must be accessed in sequential and
847 * continuous manner */
848static inline bool
849sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
850{
851 if ((s->data_count & 0x3) != byte_num) {
852 ERRPRINT("Non-sequential access to Buffer Data Port register"
853 "is prohibited\n");
854 return false;
855 }
856 return true;
857}
858
d368ba43 859static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
d7dfca08 860{
d368ba43 861 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 862 uint32_t ret = 0;
863
864 switch (offset & ~0x3) {
865 case SDHC_SYSAD:
866 ret = s->sdmasysad;
867 break;
868 case SDHC_BLKSIZE:
869 ret = s->blksize | (s->blkcnt << 16);
870 break;
871 case SDHC_ARGUMENT:
872 ret = s->argument;
873 break;
874 case SDHC_TRNMOD:
875 ret = s->trnmod | (s->cmdreg << 16);
876 break;
877 case SDHC_RSPREG0 ... SDHC_RSPREG3:
878 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
879 break;
880 case SDHC_BDATA:
881 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43
KC		 882 ret = sdhci_read_dataport(s, size);
883 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset,
677ff2ae 884 ret, ret);
d7dfca08
IM		 885 return ret;
886 }
887 break;
888 case SDHC_PRNSTS:
889 ret = s->prnsts;
890 break;
891 case SDHC_HOSTCTL:
892 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) |
893 (s->wakcon << 24);
894 break;
895 case SDHC_CLKCON:
896 ret = s->clkcon | (s->timeoutcon << 16);
897 break;
898 case SDHC_NORINTSTS:
899 ret = s->norintsts | (s->errintsts << 16);
900 break;
901 case SDHC_NORINTSTSEN:
902 ret = s->norintstsen | (s->errintstsen << 16);
903 break;
904 case SDHC_NORINTSIGEN:
905 ret = s->norintsigen | (s->errintsigen << 16);
906 break;
907 case SDHC_ACMD12ERRSTS:
908 ret = s->acmd12errsts;
909 break;
910 case SDHC_CAPAREG:
911 ret = s->capareg;
912 break;
913 case SDHC_MAXCURR:
914 ret = s->maxcurr;
915 break;
916 case SDHC_ADMAERR:
917 ret = s->admaerr;
918 break;
919 case SDHC_ADMASYSADDR:
920 ret = (uint32_t)s->admasysaddr;
921 break;
922 case SDHC_ADMASYSADDR + 4:
923 ret = (uint32_t)(s->admasysaddr >> 32);
924 break;
925 case SDHC_SLOT_INT_STATUS:
926 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
927 break;
928 default:
d368ba43 929 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset);
d7dfca08
IM		 930 break;
931 }
932
933 ret >>= (offset & 0x3) * 8;
934 ret &= (1ULL << (size * 8)) - 1;
d368ba43 935 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret);
d7dfca08
IM		 936 return ret;
937}
938
939static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
940{
941 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
942 return;
943 }
944 s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
945
946 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
947 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
948 if (s->stopped_state == sdhc_gap_read) {
949 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ;
d368ba43 950 sdhci_read_block_from_card(s);
d7dfca08
IM		 951 } else {
952 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE;
d368ba43 953 sdhci_write_block_to_card(s);
d7dfca08
IM		 954 }
955 s->stopped_state = sdhc_not_stopped;
956 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
957 if (s->prnsts & SDHC_DOING_READ) {
958 s->stopped_state = sdhc_gap_read;
959 } else if (s->prnsts & SDHC_DOING_WRITE) {
960 s->stopped_state = sdhc_gap_write;
961 }
962 }
963}
964
965static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
966{
967 switch (value) {
968 case SDHC_RESET_ALL:
d368ba43 969 sdhci_reset(s);
d7dfca08
IM		 970 break;
971 case SDHC_RESET_CMD:
972 s->prnsts &= ~SDHC_CMD_INHIBIT;
973 s->norintsts &= ~SDHC_NIS_CMDCMP;
974 break;
975 case SDHC_RESET_DATA:
976 s->data_count = 0;
977 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE |
978 SDHC_DOING_READ | SDHC_DOING_WRITE |
979 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
980 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
981 s->stopped_state = sdhc_not_stopped;
982 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
983 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
984 break;
985 }
986}
987
988static void
d368ba43 989sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
d7dfca08 990{
d368ba43 991 SDHCIState *s = (SDHCIState *)opaque;
d7dfca08
IM		 992 unsigned shift = 8 * (offset & 0x3);
993 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
d368ba43 994 uint32_t value = val;
d7dfca08
IM		 995 value <<= shift;
996
997 switch (offset & ~0x3) {
998 case SDHC_SYSAD:
999 s->sdmasysad = (s->sdmasysad & mask) | value;
1000 MASKED_WRITE(s->sdmasysad, mask, value);
1001 /* Writing to last byte of sdmasysad might trigger transfer */
1002 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt &&
1003 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) {
d368ba43 1004 sdhci_sdma_transfer_multi_blocks(s);
d7dfca08
IM		 1005 }
1006 break;
1007 case SDHC_BLKSIZE:
1008 if (!TRANSFERRING_DATA(s->prnsts)) {
1009 MASKED_WRITE(s->blksize, mask, value);
1010 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1011 }
1012 break;
1013 case SDHC_ARGUMENT:
1014 MASKED_WRITE(s->argument, mask, value);
1015 break;
1016 case SDHC_TRNMOD:
1017 /* DMA can be enabled only if it is supported as indicated by
1018 * capabilities register */
1019 if (!(s->capareg & SDHC_CAN_DO_DMA)) {
1020 value &= ~SDHC_TRNS_DMA;
1021 }
1022 MASKED_WRITE(s->trnmod, mask, value);
1023 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1024
1025 /* Writing to the upper byte of CMDREG triggers SD command generation */
d368ba43 1026 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) {
d7dfca08
IM		 1027 break;
1028 }
1029
d368ba43 1030 sdhci_send_command(s);
d7dfca08
IM		 1031 break;
1032 case SDHC_BDATA:
1033 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
d368ba43 1034 sdhci_write_dataport(s, value >> shift, size);
d7dfca08
IM		 1035 }
1036 break;
1037 case SDHC_HOSTCTL:
1038 if (!(mask & 0xFF0000)) {
1039 sdhci_blkgap_write(s, value >> 16);
1040 }
1041 MASKED_WRITE(s->hostctl, mask, value);
1042 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1043 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1044 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 ||
1045 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1046 s->pwrcon &= ~SDHC_POWER_ON;
1047 }
1048 break;
1049 case SDHC_CLKCON:
1050 if (!(mask & 0xFF000000)) {
1051 sdhci_reset_write(s, value >> 24);
1052 }
1053 MASKED_WRITE(s->clkcon, mask, value);
1054 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1055 if (s->clkcon & SDHC_CLOCK_INT_EN) {
1056 s->clkcon |= SDHC_CLOCK_INT_STABLE;
1057 } else {
1058 s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1059 }
1060 break;
1061 case SDHC_NORINTSTS:
1062 if (s->norintstsen & SDHC_NISEN_CARDINT) {
1063 value &= ~SDHC_NIS_CARDINT;
1064 }
1065 s->norintsts &= mask | ~value;
1066 s->errintsts &= (mask >> 16) | ~(value >> 16);
1067 if (s->errintsts) {
1068 s->norintsts |= SDHC_NIS_ERR;
1069 } else {
1070 s->norintsts &= ~SDHC_NIS_ERR;
1071 }
1072 sdhci_update_irq(s);
1073 break;
1074 case SDHC_NORINTSTSEN:
1075 MASKED_WRITE(s->norintstsen, mask, value);
1076 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1077 s->norintsts &= s->norintstsen;
1078 s->errintsts &= s->errintstsen;
1079 if (s->errintsts) {
1080 s->norintsts |= SDHC_NIS_ERR;
1081 } else {
1082 s->norintsts &= ~SDHC_NIS_ERR;
1083 }
1084 sdhci_update_irq(s);
1085 break;
1086 case SDHC_NORINTSIGEN:
1087 MASKED_WRITE(s->norintsigen, mask, value);
1088 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1089 sdhci_update_irq(s);
1090 break;
1091 case SDHC_ADMAERR:
1092 MASKED_WRITE(s->admaerr, mask, value);
1093 break;
1094 case SDHC_ADMASYSADDR:
1095 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
1096 (uint64_t)mask)) | (uint64_t)value;
1097 break;
1098 case SDHC_ADMASYSADDR + 4:
1099 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
1100 ((uint64_t)mask << 32))) | ((uint64_t)value << 32);
1101 break;
1102 case SDHC_FEAER:
1103 s->acmd12errsts |= value;
1104 s->errintsts |= (value >> 16) & s->errintstsen;
1105 if (s->acmd12errsts) {
1106 s->errintsts |= SDHC_EIS_CMD12ERR;
1107 }
1108 if (s->errintsts) {
1109 s->norintsts |= SDHC_NIS_ERR;
1110 }
1111 sdhci_update_irq(s);
1112 break;
1113 default:
1114 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
d368ba43 1115 size, (int)offset, value >> shift, value >> shift);
d7dfca08
IM		 1116 break;
1117 }
1118 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
d368ba43 1119 size, (int)offset, value >> shift, value >> shift);
d7dfca08
IM		 1120}
1121
1122static const MemoryRegionOps sdhci_mmio_ops = {
d368ba43
KC		 1123 .read = sdhci_read,
1124 .write = sdhci_write,
d7dfca08
IM		 1125 .valid = {
1126 .min_access_size = 1,
1127 .max_access_size = 4,
1128 .unaligned = false
1129 },
1130 .endianness = DEVICE_LITTLE_ENDIAN,
1131};
1132
1133static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
1134{
1135 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) {
1136 case 0:
1137 return 512;
1138 case 1:
1139 return 1024;
1140 case 2:
1141 return 2048;
1142 default:
1143 hw_error("SDHC: unsupported value for maximum block size\n");
1144 return 0;
1145 }
1146}
1147
7302dcd6 1148static void sdhci_initfn(SDHCIState *s)
d7dfca08 1149{
d7dfca08
IM		 1150 DriveInfo *di;
1151
af9e40aa 1152 /* FIXME use a qdev drive property instead of drive_get_next() */
d7dfca08 1153 di = drive_get_next(IF_SD);
4be74634 1154 s->card = sd_init(di ? blk_by_legacy_dinfo(di) : NULL, false);
4f8a066b
KW		 1155 if (s->card == NULL) {
1156 exit(1);
1157 }
f3c7d038
AF		 1158 s->eject_cb = qemu_allocate_irq(sdhci_insert_eject_cb, s, 0);
1159 s->ro_cb = qemu_allocate_irq(sdhci_card_readonly_cb, s, 0);
d7dfca08
IM		 1160 sd_set_cb(s->card, s->ro_cb, s->eject_cb);
1161
bc72ad67 1162 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
d368ba43 1163 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
d7dfca08
IM		 1164}
1165
7302dcd6 1166static void sdhci_uninitfn(SDHCIState *s)
d7dfca08 1167{
bc72ad67
AB		 1168 timer_del(s->insert_timer);
1169 timer_free(s->insert_timer);
1170 timer_del(s->transfer_timer);
1171 timer_free(s->transfer_timer);
127a4e1a
AF		 1172 qemu_free_irq(s->eject_cb);
1173 qemu_free_irq(s->ro_cb);
d7dfca08 1174
012aef07
MA		 1175 g_free(s->fifo_buffer);
1176 s->fifo_buffer = NULL;
d7dfca08
IM		 1177}
1178
1179const VMStateDescription sdhci_vmstate = {
1180 .name = "sdhci",
1181 .version_id = 1,
1182 .minimum_version_id = 1,
35d08458 1183 .fields = (VMStateField[]) {
d7dfca08
IM		 1184 VMSTATE_UINT32(sdmasysad, SDHCIState),
1185 VMSTATE_UINT16(blksize, SDHCIState),
1186 VMSTATE_UINT16(blkcnt, SDHCIState),
1187 VMSTATE_UINT32(argument, SDHCIState),
1188 VMSTATE_UINT16(trnmod, SDHCIState),
1189 VMSTATE_UINT16(cmdreg, SDHCIState),
1190 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1191 VMSTATE_UINT32(prnsts, SDHCIState),
1192 VMSTATE_UINT8(hostctl, SDHCIState),
1193 VMSTATE_UINT8(pwrcon, SDHCIState),
1194 VMSTATE_UINT8(blkgap, SDHCIState),
1195 VMSTATE_UINT8(wakcon, SDHCIState),
1196 VMSTATE_UINT16(clkcon, SDHCIState),
1197 VMSTATE_UINT8(timeoutcon, SDHCIState),
1198 VMSTATE_UINT8(admaerr, SDHCIState),
1199 VMSTATE_UINT16(norintsts, SDHCIState),
1200 VMSTATE_UINT16(errintsts, SDHCIState),
1201 VMSTATE_UINT16(norintstsen, SDHCIState),
1202 VMSTATE_UINT16(errintstsen, SDHCIState),
1203 VMSTATE_UINT16(norintsigen, SDHCIState),
1204 VMSTATE_UINT16(errintsigen, SDHCIState),
1205 VMSTATE_UINT16(acmd12errsts, SDHCIState),
1206 VMSTATE_UINT16(data_count, SDHCIState),
1207 VMSTATE_UINT64(admasysaddr, SDHCIState),
1208 VMSTATE_UINT8(stopped_state, SDHCIState),
1209 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz),
e720677e
PB		 1210 VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1211 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
d7dfca08
IM		 1212 VMSTATE_END_OF_LIST()
1213 }
1214};
1215
1216/* Capabilities registers provide information on supported features of this
1217 * specific host controller implementation */
1218static Property sdhci_properties[] = {
c7bcc85d 1219 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
d7dfca08 1220 SDHC_CAPAB_REG_DEFAULT),
c7bcc85d 1221 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
d7dfca08
IM		 1222 DEFINE_PROP_END_OF_LIST(),
1223};
1224
9af21dbe 1225static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
224d10ff
KC		 1226{
1227 SDHCIState *s = PCI_SDHCI(dev);
1228 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
1229 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
1230 sdhci_initfn(s);
1231 s->buf_maxsz = sdhci_get_fifolen(s);
1232 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1233 s->irq = pci_allocate_irq(dev);
1234 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
1235 SDHC_REGISTERS_MAP_SIZE);
1236 pci_register_bar(dev, 0, 0, &s->iomem);
224d10ff
KC		 1237}
1238
1239static void sdhci_pci_exit(PCIDevice *dev)
1240{
1241 SDHCIState *s = PCI_SDHCI(dev);
1242 sdhci_uninitfn(s);
1243}
1244
1245static void sdhci_pci_class_init(ObjectClass *klass, void *data)
1246{
1247 DeviceClass *dc = DEVICE_CLASS(klass);
1248 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1249
9af21dbe 1250 k->realize = sdhci_pci_realize;
224d10ff
KC		 1251 k->exit = sdhci_pci_exit;
1252 k->vendor_id = PCI_VENDOR_ID_REDHAT;
1253 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
1254 k->class_id = PCI_CLASS_SYSTEM_SDHCI;
1255 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1256 dc->vmsd = &sdhci_vmstate;
1257 dc->props = sdhci_properties;
19109131
MA		 1258 /* Reason: realize() method uses drive_get_next() */
1259 dc->cannot_instantiate_with_device_add_yet = true;
224d10ff
KC		 1260}
1261
1262static const TypeInfo sdhci_pci_info = {
1263 .name = TYPE_PCI_SDHCI,
1264 .parent = TYPE_PCI_DEVICE,
1265 .instance_size = sizeof(SDHCIState),
1266 .class_init = sdhci_pci_class_init,
1267};
1268
7302dcd6
KC		 1269static void sdhci_sysbus_init(Object *obj)
1270{
1271 SDHCIState *s = SYSBUS_SDHCI(obj);
1272 sdhci_initfn(s);
1273}
1274
1275static void sdhci_sysbus_finalize(Object *obj)
1276{
1277 SDHCIState *s = SYSBUS_SDHCI(obj);
1278 sdhci_uninitfn(s);
1279}
1280
1281static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
d7dfca08 1282{
7302dcd6 1283 SDHCIState *s = SYSBUS_SDHCI(dev);
d7dfca08
IM		 1284 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1285
1286 s->buf_maxsz = sdhci_get_fifolen(s);
1287 s->fifo_buffer = g_malloc0(s->buf_maxsz);
1288 sysbus_init_irq(sbd, &s->irq);
29776739 1289 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
d7dfca08
IM		 1290 SDHC_REGISTERS_MAP_SIZE);
1291 sysbus_init_mmio(sbd, &s->iomem);
1292}
1293
7302dcd6 1294static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
d7dfca08
IM		 1295{
1296 DeviceClass *dc = DEVICE_CLASS(klass);
d7dfca08
IM		 1297
1298 dc->vmsd = &sdhci_vmstate;
1299 dc->props = sdhci_properties;
7302dcd6 1300 dc->realize = sdhci_sysbus_realize;
9f9bdf43
MA		 1301 /* Reason: instance_init() method uses drive_get_next() */
1302 dc->cannot_instantiate_with_device_add_yet = true;
d7dfca08
IM		 1303}
1304
7302dcd6
KC		 1305static const TypeInfo sdhci_sysbus_info = {
1306 .name = TYPE_SYSBUS_SDHCI,
d7dfca08
IM		 1307 .parent = TYPE_SYS_BUS_DEVICE,
1308 .instance_size = sizeof(SDHCIState),
7302dcd6
KC		 1309 .instance_init = sdhci_sysbus_init,
1310 .instance_finalize = sdhci_sysbus_finalize,
1311 .class_init = sdhci_sysbus_class_init,
d7dfca08
IM		 1312};
1313
1314static void sdhci_register_types(void)
1315{
224d10ff 1316 type_register_static(&sdhci_pci_info);
7302dcd6 1317 type_register_static(&sdhci_sysbus_info);
d7dfca08
IM		 1318}
1319
1320type_init(sdhci_register_types)
Mirror of https://git.qemu.org/git/qemu.git