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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
d6454270 | 24 | |
db5ebe5f | 25 | #include "qemu/osdep.h" |
0a2e467b | 26 | #include "qemu/units.h" |
29bd7231 | 27 | #include "qemu/error-report.h" |
da34e65c | 28 | #include "qapi/error.h" |
2c65db5e | 29 | #include "qemu/datadir.h" |
4771d756 | 30 | #include "cpu.h" |
83c9f4ca | 31 | #include "hw/pci/pci.h" |
4272ad40 | 32 | #include "hw/pci/pci_bridge.h" |
6864fa38 | 33 | #include "hw/pci/pci_bus.h" |
0ea833c2 | 34 | #include "hw/pci/pci_host.h" |
a27bd6c7 | 35 | #include "hw/qdev-properties.h" |
9b301794 | 36 | #include "hw/pci-host/sabre.h" |
0d09e41a | 37 | #include "hw/char/serial.h" |
bb3d5ea8 | 38 | #include "hw/char/parallel.h" |
819ce6b2 | 39 | #include "hw/rtc/m48t59.h" |
d6454270 | 40 | #include "migration/vmstate.h" |
47973a2d | 41 | #include "hw/input/i8042.h" |
0d09e41a | 42 | #include "hw/block/fdc.h" |
1422e32d | 43 | #include "net/net.h" |
1de7afc9 | 44 | #include "qemu/timer.h" |
54d31236 | 45 | #include "sysemu/runstate.h" |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
83c9f4ca | 47 | #include "hw/boards.h" |
c6363bae | 48 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 49 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 50 | #include "hw/sparc/sparc64.h" |
0d09e41a | 51 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca | 52 | #include "hw/sysbus.h" |
6864fa38 | 53 | #include "hw/ide/pci.h" |
83c9f4ca | 54 | #include "hw/loader.h" |
0a1d5c45 | 55 | #include "hw/fw-path-provider.h" |
ca20cf32 | 56 | #include "elf.h" |
69520948 | 57 | #include "trace.h" |
db1015e9 | 58 | #include "qom/object.h" |
3475187d | 59 | |
83469015 FB |
60 | #define KERNEL_LOAD_ADDR 0x00404000 |
61 | #define CMDLINE_ADDR 0x003ff000 | |
0a2e467b | 62 | #define PROM_SIZE_MAX (4 * MiB) |
f930d07e | 63 | #define PROM_VADDR 0x000ffd00000ULL |
5795162a MCA |
64 | #define PBM_SPECIAL_BASE 0x1fe00000000ULL |
65 | #define PBM_MEM_BASE 0x1ff00000000ULL | |
66 | #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) | |
f930d07e | 67 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 68 | #define NVRAM_SIZE 0x2000 |
3cce6243 | 69 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
70 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
71 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
72 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 73 | |
852e82f3 | 74 | #define IVEC_MAX 0x40 |
9d926598 | 75 | |
c7ba218d | 76 | struct hwdef { |
905fdcb5 | 77 | uint16_t machine_id; |
e87231d4 BS |
78 | uint64_t prom_addr; |
79 | uint64_t console_serial_base; | |
c7ba218d BS |
80 | }; |
81 | ||
db1015e9 | 82 | struct EbusState { |
ad6856e8 MCA |
83 | /*< private >*/ |
84 | PCIDevice parent_obj; | |
85 | ||
8c40b8d9 | 86 | ISABus *isa_bus; |
eba24565 PMD |
87 | qemu_irq *isa_irqs_in; |
88 | qemu_irq isa_irqs_out[ISA_NUM_IRQS]; | |
0fe22ffb | 89 | uint64_t console_serial_base; |
c5e6fb7e AK |
90 | MemoryRegion bar0; |
91 | MemoryRegion bar1; | |
db1015e9 | 92 | }; |
c5e6fb7e | 93 | |
ad6856e8 | 94 | #define TYPE_EBUS "ebus" |
8063396b | 95 | OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS) |
ad6856e8 | 96 | |
a2b45ea5 PMD |
97 | const char *fw_cfg_arch_key_name(uint16_t key) |
98 | { | |
99 | static const struct { | |
100 | uint16_t key; | |
101 | const char *name; | |
102 | } fw_cfg_arch_wellknown_keys[] = { | |
103 | {FW_CFG_SPARC64_WIDTH, "width"}, | |
104 | {FW_CFG_SPARC64_HEIGHT, "height"}, | |
105 | {FW_CFG_SPARC64_DEPTH, "depth"}, | |
106 | }; | |
107 | ||
108 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { | |
109 | if (fw_cfg_arch_wellknown_keys[i].key == key) { | |
110 | return fw_cfg_arch_wellknown_keys[i].name; | |
111 | } | |
112 | } | |
113 | return NULL; | |
114 | } | |
115 | ||
ddcd5531 GA |
116 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
117 | Error **errp) | |
81864572 | 118 | { |
48779e50 | 119 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
120 | } |
121 | ||
31688246 | 122 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
123 | const char *arch, ram_addr_t RAM_size, |
124 | const char *boot_devices, | |
125 | uint32_t kernel_image, uint32_t kernel_size, | |
126 | const char *cmdline, | |
127 | uint32_t initrd_image, uint32_t initrd_size, | |
128 | uint32_t NVRAM_image, | |
129 | int width, int height, int depth, | |
130 | const uint8_t *macaddr) | |
83469015 | 131 | { |
66508601 | 132 | unsigned int i; |
2024c014 | 133 | int sysp_end; |
d2c63fc1 | 134 | uint8_t image[0x1ff0]; |
31688246 | 135 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
136 | |
137 | memset(image, '\0', sizeof(image)); | |
138 | ||
2024c014 | 139 | /* OpenBIOS nvram variables partition */ |
37035df5 | 140 | sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); |
83469015 | 141 | |
2024c014 TH |
142 | /* Free space partition */ |
143 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 144 | |
0d31cb99 BS |
145 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
146 | ||
31688246 HP |
147 | for (i = 0; i < sizeof(image); i++) { |
148 | (k->write)(nvram, i, image[i]); | |
149 | } | |
66508601 | 150 | |
83469015 | 151 | return 0; |
3475187d | 152 | } |
5f2bf0fe BS |
153 | |
154 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
155 | const char *initrd_filename, | |
156 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
157 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
158 | uint64_t *kernel_entry) | |
636aa70a BS |
159 | { |
160 | int linux_boot; | |
161 | unsigned int i; | |
162 | long kernel_size; | |
6908d9ce | 163 | uint8_t *ptr; |
3ac24188 | 164 | uint64_t kernel_top = 0; |
636aa70a BS |
165 | |
166 | linux_boot = (kernel_filename != NULL); | |
167 | ||
168 | kernel_size = 0; | |
169 | if (linux_boot) { | |
ca20cf32 BS |
170 | int bswap_needed; |
171 | ||
172 | #ifdef BSWAP_NEEDED | |
173 | bswap_needed = 1; | |
174 | #else | |
175 | bswap_needed = 0; | |
176 | #endif | |
4366e1db | 177 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, |
6cdda0ff AM |
178 | kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0, |
179 | 0); | |
5f2bf0fe BS |
180 | if (kernel_size < 0) { |
181 | *kernel_addr = KERNEL_LOAD_ADDR; | |
182 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 183 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
184 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
185 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
186 | } |
187 | if (kernel_size < 0) { | |
636aa70a BS |
188 | kernel_size = load_image_targphys(kernel_filename, |
189 | KERNEL_LOAD_ADDR, | |
190 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 191 | } |
636aa70a | 192 | if (kernel_size < 0) { |
29bd7231 | 193 | error_report("could not load kernel '%s'", kernel_filename); |
636aa70a BS |
194 | exit(1); |
195 | } | |
5f2bf0fe | 196 | /* load initrd above kernel */ |
636aa70a | 197 | *initrd_size = 0; |
3ac24188 | 198 | if (initrd_filename && kernel_top) { |
5f2bf0fe BS |
199 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
200 | ||
636aa70a | 201 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
202 | *initrd_addr, |
203 | RAM_size - *initrd_addr); | |
204 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
205 | error_report("could not load initial ram disk '%s'", |
206 | initrd_filename); | |
636aa70a BS |
207 | exit(1); |
208 | } | |
209 | } | |
210 | if (*initrd_size > 0) { | |
211 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
0f0f8b61 TH |
212 | ptr = rom_ptr(*kernel_addr + i, 32); |
213 | if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ | |
5f2bf0fe | 214 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 215 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
216 | break; |
217 | } | |
218 | } | |
219 | } | |
220 | } | |
221 | return kernel_size; | |
222 | } | |
3475187d | 223 | |
e87231d4 | 224 | typedef struct ResetData { |
403d7a2d | 225 | SPARCCPU *cpu; |
44a99354 | 226 | uint64_t prom_addr; |
e87231d4 BS |
227 | } ResetData; |
228 | ||
25c5d5ac | 229 | #define TYPE_SUN4U_POWER "power" |
8063396b | 230 | OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER) |
25c5d5ac | 231 | |
db1015e9 | 232 | struct PowerDevice { |
25c5d5ac MCA |
233 | SysBusDevice parent_obj; |
234 | ||
235 | MemoryRegion power_mmio; | |
db1015e9 | 236 | }; |
25c5d5ac MCA |
237 | |
238 | /* Power */ | |
ad280559 PP |
239 | static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) |
240 | { | |
241 | return 0; | |
242 | } | |
243 | ||
25c5d5ac MCA |
244 | static void power_mem_write(void *opaque, hwaddr addr, |
245 | uint64_t val, unsigned size) | |
246 | { | |
247 | /* According to a real Ultra 5, bit 24 controls the power */ | |
248 | if (val & 0x1000000) { | |
249 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
250 | } | |
251 | } | |
252 | ||
253 | static const MemoryRegionOps power_mem_ops = { | |
ad280559 | 254 | .read = power_mem_read, |
25c5d5ac MCA |
255 | .write = power_mem_write, |
256 | .endianness = DEVICE_NATIVE_ENDIAN, | |
257 | .valid = { | |
258 | .min_access_size = 4, | |
259 | .max_access_size = 4, | |
260 | }, | |
261 | }; | |
262 | ||
263 | static void power_realize(DeviceState *dev, Error **errp) | |
264 | { | |
265 | PowerDevice *d = SUN4U_POWER(dev); | |
266 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
267 | ||
268 | memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, | |
269 | "power", sizeof(uint32_t)); | |
270 | ||
271 | sysbus_init_mmio(sbd, &d->power_mmio); | |
272 | } | |
273 | ||
274 | static void power_class_init(ObjectClass *klass, void *data) | |
275 | { | |
276 | DeviceClass *dc = DEVICE_CLASS(klass); | |
277 | ||
278 | dc->realize = power_realize; | |
279 | } | |
280 | ||
281 | static const TypeInfo power_info = { | |
282 | .name = TYPE_SUN4U_POWER, | |
283 | .parent = TYPE_SYS_BUS_DEVICE, | |
284 | .instance_size = sizeof(PowerDevice), | |
285 | .class_init = power_class_init, | |
286 | }; | |
287 | ||
4b10c8d7 | 288 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 289 | { |
4b10c8d7 | 290 | EbusState *s = EBUS(opaque); |
eba24565 | 291 | qemu_irq irq = s->isa_irqs_out[n]; |
4b10c8d7 MCA |
292 | |
293 | /* Pass ISA bus IRQs onto their gpio equivalent */ | |
69520948 | 294 | trace_ebus_isa_irq_handler(n, level); |
4b10c8d7 MCA |
295 | if (irq) { |
296 | qemu_set_irq(irq, level); | |
361dea40 | 297 | } |
1387fe4a BS |
298 | } |
299 | ||
c190ea07 | 300 | /* EBUS (Eight bit bus) bridge */ |
ad6856e8 | 301 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 302 | { |
ad6856e8 | 303 | EbusState *s = EBUS(pci_dev); |
96927c74 | 304 | ISADevice *isa_dev; |
25c5d5ac | 305 | SysBusDevice *sbd; |
0fe22ffb | 306 | DeviceState *dev; |
0fe22ffb MCA |
307 | DriveInfo *fd[MAX_FD]; |
308 | int i; | |
c5e6fb7e | 309 | |
8c40b8d9 MCA |
310 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
311 | pci_address_space_io(pci_dev), errp); | |
312 | if (!s->isa_bus) { | |
313 | error_setg(errp, "unable to instantiate EBUS ISA bus"); | |
d10e5432 MA |
314 | return; |
315 | } | |
c5e6fb7e | 316 | |
4b10c8d7 | 317 | /* ISA bus */ |
eba24565 | 318 | s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); |
7067887e | 319 | isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in); |
eba24565 | 320 | qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq", |
4b10c8d7 | 321 | ISA_NUM_IRQS); |
c796edda | 322 | |
0fe22ffb MCA |
323 | /* Serial ports */ |
324 | i = 0; | |
325 | if (s->console_serial_base) { | |
326 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, | |
9bca0edb | 327 | 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); |
0fe22ffb MCA |
328 | i++; |
329 | } | |
def337ff | 330 | serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); |
0fe22ffb MCA |
331 | |
332 | /* Parallel ports */ | |
333 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); | |
334 | ||
335 | /* Keyboard */ | |
aa2e535c | 336 | isa_create_simple(s->isa_bus, TYPE_I8042); |
0fe22ffb MCA |
337 | |
338 | /* Floppy */ | |
339 | for (i = 0; i < MAX_FD; i++) { | |
340 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
341 | } | |
96927c74 MA |
342 | isa_dev = isa_new(TYPE_ISA_FDC); |
343 | dev = DEVICE(isa_dev); | |
0fe22ffb | 344 | qdev_prop_set_uint32(dev, "dma", -1); |
96927c74 | 345 | isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal); |
6172e067 | 346 | isa_fdc_init_drives(isa_dev, fd); |
0fe22ffb | 347 | |
25c5d5ac | 348 | /* Power */ |
3e80f690 | 349 | dev = qdev_new(TYPE_SUN4U_POWER); |
25c5d5ac | 350 | sbd = SYS_BUS_DEVICE(dev); |
3c6ef471 | 351 | sysbus_realize_and_unref(sbd, &error_fatal); |
25c5d5ac MCA |
352 | memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, |
353 | sysbus_mmio_get_region(sbd, 0)); | |
354 | ||
0fe22ffb | 355 | /* PCI */ |
c5e6fb7e AK |
356 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
357 | pci_dev->config[0x05] = 0x00; | |
358 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
359 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
360 | pci_dev->config[0x09] = 0x00; // programming i/f | |
361 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
362 | ||
0a70e094 PB |
363 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
364 | 0, 0x1000000); | |
e824b2cc | 365 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 366 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
25c5d5ac | 367 | 0, 0x8000); |
a1cf8be5 | 368 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
369 | } |
370 | ||
0fe22ffb MCA |
371 | static Property ebus_properties[] = { |
372 | DEFINE_PROP_UINT64("console-serial-base", EbusState, | |
373 | console_serial_base, 0), | |
374 | DEFINE_PROP_END_OF_LIST(), | |
375 | }; | |
376 | ||
40021f08 AL |
377 | static void ebus_class_init(ObjectClass *klass, void *data) |
378 | { | |
379 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0fe22ffb | 380 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 381 | |
ad6856e8 | 382 | k->realize = ebus_realize; |
40021f08 AL |
383 | k->vendor_id = PCI_VENDOR_ID_SUN; |
384 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
385 | k->revision = 0x01; | |
386 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
4f67d30b | 387 | device_class_set_props(dc, ebus_properties); |
40021f08 AL |
388 | } |
389 | ||
8c43a6f0 | 390 | static const TypeInfo ebus_info = { |
ad6856e8 | 391 | .name = TYPE_EBUS, |
39bffca2 | 392 | .parent = TYPE_PCI_DEVICE, |
39bffca2 | 393 | .class_init = ebus_class_init, |
ad6856e8 | 394 | .instance_size = sizeof(EbusState), |
fd3b02c8 EH |
395 | .interfaces = (InterfaceInfo[]) { |
396 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
397 | { }, | |
398 | }, | |
53e3c4f9 BS |
399 | }; |
400 | ||
13575cf6 | 401 | #define TYPE_OPENPROM "openprom" |
db1015e9 | 402 | typedef struct PROMState PROMState; |
8110fa1d EH |
403 | DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, |
404 | TYPE_OPENPROM) | |
13575cf6 | 405 | |
db1015e9 | 406 | struct PROMState { |
13575cf6 AF |
407 | SysBusDevice parent_obj; |
408 | ||
d4edce38 | 409 | MemoryRegion prom; |
db1015e9 | 410 | }; |
d4edce38 | 411 | |
409dbce5 AJ |
412 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
413 | { | |
a8170e5e | 414 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
415 | return addr + *base_addr - PROM_VADDR; |
416 | } | |
417 | ||
1baffa46 | 418 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 419 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
420 | { |
421 | DeviceState *dev; | |
422 | SysBusDevice *s; | |
423 | char *filename; | |
424 | int ret; | |
425 | ||
3e80f690 | 426 | dev = qdev_new(TYPE_OPENPROM); |
1356b98d | 427 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 428 | sysbus_realize_and_unref(s, &error_fatal); |
1baffa46 BS |
429 | |
430 | sysbus_mmio_map(s, 0, addr); | |
431 | ||
432 | /* load boot prom */ | |
433 | if (bios_name == NULL) { | |
434 | bios_name = PROM_FILENAME; | |
435 | } | |
436 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
437 | if (filename) { | |
4366e1db | 438 | ret = load_elf(filename, NULL, translate_prom_address, &addr, |
6cdda0ff | 439 | NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
440 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
441 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
442 | } | |
7267c094 | 443 | g_free(filename); |
1baffa46 BS |
444 | } else { |
445 | ret = -1; | |
446 | } | |
447 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 448 | error_report("could not load prom '%s'", bios_name); |
1baffa46 BS |
449 | exit(1); |
450 | } | |
451 | } | |
452 | ||
92b19880 | 453 | static void prom_realize(DeviceState *ds, Error **errp) |
1baffa46 | 454 | { |
92b19880 TH |
455 | PROMState *s = OPENPROM(ds); |
456 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
457 | Error *local_err = NULL; | |
458 | ||
459 | memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", | |
460 | PROM_SIZE_MAX, &local_err); | |
461 | if (local_err) { | |
462 | error_propagate(errp, local_err); | |
463 | return; | |
464 | } | |
1baffa46 | 465 | |
c5705a77 | 466 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 467 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 468 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
469 | } |
470 | ||
999e12bb AL |
471 | static Property prom_properties[] = { |
472 | {/* end of property list */}, | |
473 | }; | |
474 | ||
475 | static void prom_class_init(ObjectClass *klass, void *data) | |
476 | { | |
39bffca2 | 477 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 478 | |
4f67d30b | 479 | device_class_set_props(dc, prom_properties); |
92b19880 | 480 | dc->realize = prom_realize; |
999e12bb AL |
481 | } |
482 | ||
8c43a6f0 | 483 | static const TypeInfo prom_info = { |
13575cf6 | 484 | .name = TYPE_OPENPROM, |
39bffca2 AL |
485 | .parent = TYPE_SYS_BUS_DEVICE, |
486 | .instance_size = sizeof(PROMState), | |
487 | .class_init = prom_class_init, | |
1baffa46 BS |
488 | }; |
489 | ||
bda42033 | 490 | |
88c034d5 | 491 | #define TYPE_SUN4U_MEMORY "memory" |
db1015e9 | 492 | typedef struct RamDevice RamDevice; |
8110fa1d EH |
493 | DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM, |
494 | TYPE_SUN4U_MEMORY) | |
88c034d5 | 495 | |
db1015e9 | 496 | struct RamDevice { |
88c034d5 AF |
497 | SysBusDevice parent_obj; |
498 | ||
d4edce38 | 499 | MemoryRegion ram; |
04843626 | 500 | uint64_t size; |
db1015e9 | 501 | }; |
bda42033 BS |
502 | |
503 | /* System RAM */ | |
78fb261d | 504 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 505 | { |
88c034d5 | 506 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 507 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 508 | |
1cfe48c1 | 509 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 510 | &error_fatal); |
c5705a77 | 511 | vmstate_register_ram_global(&d->ram); |
78fb261d | 512 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
513 | } |
514 | ||
a8170e5e | 515 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
516 | { |
517 | DeviceState *dev; | |
518 | SysBusDevice *s; | |
519 | RamDevice *d; | |
520 | ||
521 | /* allocate RAM */ | |
3e80f690 | 522 | dev = qdev_new(TYPE_SUN4U_MEMORY); |
1356b98d | 523 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 524 | |
88c034d5 | 525 | d = SUN4U_RAM(dev); |
bda42033 | 526 | d->size = RAM_size; |
3c6ef471 | 527 | sysbus_realize_and_unref(s, &error_fatal); |
bda42033 BS |
528 | |
529 | sysbus_mmio_map(s, 0, addr); | |
530 | } | |
531 | ||
999e12bb AL |
532 | static Property ram_properties[] = { |
533 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
534 | DEFINE_PROP_END_OF_LIST(), | |
535 | }; | |
536 | ||
537 | static void ram_class_init(ObjectClass *klass, void *data) | |
538 | { | |
39bffca2 | 539 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 540 | |
78fb261d | 541 | dc->realize = ram_realize; |
4f67d30b | 542 | device_class_set_props(dc, ram_properties); |
999e12bb AL |
543 | } |
544 | ||
8c43a6f0 | 545 | static const TypeInfo ram_info = { |
88c034d5 | 546 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
547 | .parent = TYPE_SYS_BUS_DEVICE, |
548 | .instance_size = sizeof(RamDevice), | |
549 | .class_init = ram_class_init, | |
bda42033 BS |
550 | }; |
551 | ||
38bc50f7 | 552 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 553 | MachineState *machine, |
7b833f5b BS |
554 | const struct hwdef *hwdef) |
555 | { | |
f9d1465f | 556 | SPARCCPU *cpu; |
31688246 | 557 | Nvram *nvram; |
7b833f5b | 558 | unsigned int i; |
5f2bf0fe | 559 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
5795162a | 560 | SabreState *sabre; |
311f2b7a | 561 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 562 | PCIDevice *ebus, *pci_dev; |
f3b18f35 | 563 | SysBusDevice *s; |
aea5b071 | 564 | DeviceState *iommu, *dev; |
a88b362c | 565 | FWCfgState *fw_cfg; |
8d932971 | 566 | NICInfo *nd; |
6864fa38 MCA |
567 | MACAddr macaddr; |
568 | bool onboard_nic; | |
7b833f5b | 569 | |
7b833f5b | 570 | /* init CPUs */ |
58530461 | 571 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
7b833f5b | 572 | |
aea5b071 | 573 | /* IOMMU */ |
3e80f690 | 574 | iommu = qdev_new(TYPE_SUN4U_IOMMU); |
3c6ef471 | 575 | sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); |
aea5b071 | 576 | |
bda42033 | 577 | /* set up devices */ |
3ef96221 | 578 | ram_init(0, machine->ram_size); |
3475187d | 579 | |
377ce9cb | 580 | prom_init(hwdef->prom_addr, machine->firmware); |
3475187d | 581 | |
b14dcaf4 | 582 | /* Init sabre (PCI host bridge) */ |
5b07883c | 583 | sabre = SABRE(qdev_new(TYPE_SABRE)); |
5795162a MCA |
584 | qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); |
585 | qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); | |
5325cc34 | 586 | object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), |
5795162a | 587 | &error_abort); |
3c6ef471 | 588 | sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); |
2a4d6af5 | 589 | |
e237e1c2 MCA |
590 | /* sabre_config */ |
591 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE); | |
592 | /* PCI configuration space */ | |
593 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL); | |
594 | /* pci_ioport */ | |
595 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL); | |
596 | ||
2a4d6af5 MCA |
597 | /* Wire up PCI interrupts to CPU */ |
598 | for (i = 0; i < IVEC_MAX; i++) { | |
5795162a | 599 | qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, |
2a4d6af5 MCA |
600 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); |
601 | } | |
602 | ||
5795162a MCA |
603 | pci_bus = PCI_HOST_BRIDGE(sabre)->bus; |
604 | pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); | |
605 | pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); | |
83469015 | 606 | |
5795162a | 607 | /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is |
6864fa38 MCA |
608 | reserved (leaving no slots free after on-board devices) however slots |
609 | 0-3 are free on busB */ | |
610 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
611 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
612 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
613 | ||
9307d06d | 614 | ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS); |
0fe22ffb MCA |
615 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
616 | hwdef->console_serial_base); | |
9307d06d | 617 | pci_realize_and_unref(ebus, pci_busA, &error_fatal); |
6864fa38 | 618 | |
5795162a | 619 | /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ |
4b10c8d7 | 620 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, |
5795162a | 621 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); |
4b10c8d7 | 622 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, |
5795162a | 623 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); |
4b10c8d7 | 624 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, |
5795162a | 625 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); |
4b10c8d7 | 626 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, |
5795162a | 627 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); |
4b10c8d7 | 628 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, |
5795162a | 629 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); |
4b10c8d7 | 630 | |
c3019efc TH |
631 | switch (vga_interface_type) { |
632 | case VGA_STD: | |
633 | pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); | |
f9bcb2d6 | 634 | vga_interface_created = true; |
c3019efc TH |
635 | break; |
636 | case VGA_NONE: | |
637 | break; | |
638 | default: | |
639 | abort(); /* Should not happen - types are checked in vl.c already */ | |
640 | } | |
6864fa38 MCA |
641 | |
642 | memset(&macaddr, 0, sizeof(MACAddr)); | |
643 | onboard_nic = false; | |
8d932971 | 644 | for (i = 0; i < nb_nics; i++) { |
db232246 | 645 | PCIBus *bus; |
8d932971 MCA |
646 | nd = &nd_table[i]; |
647 | ||
6864fa38 MCA |
648 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
649 | if (!onboard_nic) { | |
db232246 | 650 | pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), |
6864fa38 | 651 | true, "sunhme"); |
db232246 | 652 | bus = pci_busA; |
6864fa38 MCA |
653 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); |
654 | onboard_nic = true; | |
655 | } else { | |
db232246 MA |
656 | pci_dev = pci_new(-1, "sunhme"); |
657 | bus = pci_busB; | |
6864fa38 | 658 | } |
8d932971 | 659 | } else { |
db232246 MA |
660 | pci_dev = pci_new(-1, nd->model); |
661 | bus = pci_busB; | |
8d932971 | 662 | } |
6864fa38 MCA |
663 | |
664 | dev = &pci_dev->qdev; | |
665 | qdev_set_nic_properties(dev, nd); | |
db232246 | 666 | pci_realize_and_unref(pci_dev, bus, &error_fatal); |
6864fa38 MCA |
667 | } |
668 | ||
669 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
670 | * we have a valid machine id */ | |
671 | if (!onboard_nic) { | |
672 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 673 | } |
83469015 | 674 | |
9307d06d | 675 | pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide"); |
6864fa38 | 676 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); |
9307d06d | 677 | pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); |
be1765f3 | 678 | pci_ide_create_devs(pci_dev); |
3b898dda | 679 | |
f3b18f35 | 680 | /* Map NVRAM into I/O (ebus) space */ |
dc7a05da MCA |
681 | dev = qdev_new("sysbus-m48t59"); |
682 | qdev_prop_set_int32(dev, "base-year", 1968); | |
683 | s = SYS_BUS_DEVICE(dev); | |
684 | sysbus_realize_and_unref(s, &error_fatal); | |
07c84741 | 685 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 | 686 | sysbus_mmio_get_region(s, 0)); |
dc7a05da | 687 | nvram = NVRAM(dev); |
f3b18f35 | 688 | |
636aa70a | 689 | initrd_size = 0; |
5f2bf0fe | 690 | initrd_addr = 0; |
3ef96221 MA |
691 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
692 | machine->initrd_filename, | |
48c0b1e4 | 693 | machine->ram_size, &initrd_size, &initrd_addr, |
5f2bf0fe | 694 | &kernel_addr, &kernel_entry); |
636aa70a | 695 | |
3ef96221 | 696 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
97ec4d21 | 697 | machine->boot_config.order, |
5f2bf0fe | 698 | kernel_addr, kernel_size, |
3ef96221 | 699 | machine->kernel_cmdline, |
5f2bf0fe | 700 | initrd_addr, initrd_size, |
0d31cb99 BS |
701 | /* XXX: need an option to load a NVRAM image */ |
702 | 0, | |
703 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 704 | (uint8_t *)&macaddr); |
83469015 | 705 | |
3e80f690 | 706 | dev = qdev_new(TYPE_FW_CFG_IO); |
d6acc8a5 | 707 | qdev_prop_set_bit(dev, "dma_enabled", false); |
d2623129 | 708 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); |
3c6ef471 | 709 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
07c84741 | 710 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
711 | &FW_CFG_IO(dev)->comb_iomem); |
712 | ||
713 | fw_cfg = FW_CFG(dev); | |
33decbd2 LX |
714 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); |
715 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); | |
48c0b1e4 | 716 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
905fdcb5 | 717 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
5f2bf0fe BS |
718 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
719 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 720 | if (machine->kernel_cmdline) { |
9c9b0512 | 721 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
722 | strlen(machine->kernel_cmdline) + 1); |
723 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 724 | } else { |
9c9b0512 | 725 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 726 | } |
5f2bf0fe BS |
727 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
728 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
97ec4d21 | 729 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); |
7589690c BS |
730 | |
731 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
732 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
733 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
734 | ||
513f789f | 735 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
736 | } |
737 | ||
905fdcb5 BS |
738 | enum { |
739 | sun4u_id = 0, | |
740 | sun4v_id = 64, | |
741 | }; | |
742 | ||
0a1d5c45 MCA |
743 | /* |
744 | * Implementation of an interface to adjust firmware path | |
745 | * for the bootindex property handling. | |
746 | */ | |
747 | static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, | |
748 | DeviceState *dev) | |
749 | { | |
750 | PCIDevice *pci; | |
0a1d5c45 MCA |
751 | |
752 | if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { | |
753 | pci = PCI_DEVICE(dev); | |
754 | ||
755 | if (PCI_FUNC(pci->devfn)) { | |
756 | return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), | |
757 | PCI_FUNC(pci->devfn)); | |
758 | } else { | |
759 | return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); | |
760 | } | |
761 | } | |
762 | ||
0a1d5c45 MCA |
763 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { |
764 | return g_strdup("disk"); | |
765 | } | |
766 | ||
767 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { | |
768 | return g_strdup("cdrom"); | |
769 | } | |
770 | ||
771 | if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { | |
772 | return g_strdup("disk"); | |
773 | } | |
774 | ||
775 | return NULL; | |
776 | } | |
777 | ||
c7ba218d BS |
778 | static const struct hwdef hwdefs[] = { |
779 | /* Sun4u generic PC-like machine */ | |
780 | { | |
905fdcb5 | 781 | .machine_id = sun4u_id, |
e87231d4 BS |
782 | .prom_addr = 0x1fff0000000ULL, |
783 | .console_serial_base = 0, | |
c7ba218d BS |
784 | }, |
785 | /* Sun4v generic PC-like machine */ | |
786 | { | |
905fdcb5 | 787 | .machine_id = sun4v_id, |
e87231d4 BS |
788 | .prom_addr = 0x1fff0000000ULL, |
789 | .console_serial_base = 0, | |
790 | }, | |
c7ba218d BS |
791 | }; |
792 | ||
793 | /* Sun4u hardware initialisation */ | |
3ef96221 | 794 | static void sun4u_init(MachineState *machine) |
5f072e1f | 795 | { |
3ef96221 | 796 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
797 | } |
798 | ||
799 | /* Sun4v hardware initialisation */ | |
3ef96221 | 800 | static void sun4v_init(MachineState *machine) |
5f072e1f | 801 | { |
3ef96221 | 802 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
803 | } |
804 | ||
8a661aea | 805 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 806 | { |
8a661aea | 807 | MachineClass *mc = MACHINE_CLASS(oc); |
0a1d5c45 | 808 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
8a661aea | 809 | |
e264d29d EH |
810 | mc->desc = "Sun4u platform"; |
811 | mc->init = sun4u_init; | |
2059839b | 812 | mc->block_default_type = IF_IDE; |
e264d29d | 813 | mc->max_cpus = 1; /* XXX for now */ |
ea0ac7f6 | 814 | mc->is_default = true; |
e264d29d | 815 | mc->default_boot_order = "c"; |
58530461 | 816 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
0a1d5c45 | 817 | mc->ignore_boot_device_suffixes = true; |
9aed808e | 818 | mc->default_display = "std"; |
0a1d5c45 | 819 | fwc->get_dev_path = sun4u_fw_dev_path; |
e264d29d | 820 | } |
c7ba218d | 821 | |
8a661aea AF |
822 | static const TypeInfo sun4u_type = { |
823 | .name = MACHINE_TYPE_NAME("sun4u"), | |
824 | .parent = TYPE_MACHINE, | |
825 | .class_init = sun4u_class_init, | |
0a1d5c45 MCA |
826 | .interfaces = (InterfaceInfo[]) { |
827 | { TYPE_FW_PATH_PROVIDER }, | |
828 | { } | |
829 | }, | |
8a661aea | 830 | }; |
e87231d4 | 831 | |
8a661aea | 832 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 833 | { |
8a661aea AF |
834 | MachineClass *mc = MACHINE_CLASS(oc); |
835 | ||
e264d29d EH |
836 | mc->desc = "Sun4v platform"; |
837 | mc->init = sun4v_init; | |
2059839b | 838 | mc->block_default_type = IF_IDE; |
e264d29d EH |
839 | mc->max_cpus = 1; /* XXX for now */ |
840 | mc->default_boot_order = "c"; | |
58530461 | 841 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
9aed808e | 842 | mc->default_display = "std"; |
e264d29d EH |
843 | } |
844 | ||
8a661aea AF |
845 | static const TypeInfo sun4v_type = { |
846 | .name = MACHINE_TYPE_NAME("sun4v"), | |
847 | .parent = TYPE_MACHINE, | |
848 | .class_init = sun4v_class_init, | |
849 | }; | |
e264d29d | 850 | |
83f7d43a AF |
851 | static void sun4u_register_types(void) |
852 | { | |
25c5d5ac | 853 | type_register_static(&power_info); |
83f7d43a AF |
854 | type_register_static(&ebus_info); |
855 | type_register_static(&prom_info); | |
856 | type_register_static(&ram_info); | |
83f7d43a | 857 | |
8a661aea AF |
858 | type_register_static(&sun4u_type); |
859 | type_register_static(&sun4v_type); | |
8a661aea AF |
860 | } |
861 | ||
83f7d43a | 862 | type_init(sun4u_register_types) |