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b9dc07d4 PM |
1 | /* |
2 | * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Paul Brook, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
8ef94f0b | 22 | #include "qemu/osdep.h" |
650d103d | 23 | #include "hw/hw.h" |
64552b6b | 24 | #include "hw/irq.h" |
226fb5aa | 25 | #include "hw/ptimer.h" |
eb110bd8 | 26 | #include "hw/timer/arm_mptimer.h" |
d6454270 | 27 | #include "migration/vmstate.h" |
da34e65c | 28 | #include "qapi/error.h" |
226fb5aa | 29 | #include "qemu/main-loop.h" |
0b8fa32f | 30 | #include "qemu/module.h" |
de6db419 | 31 | #include "qom/cpu.h" |
b9dc07d4 | 32 | |
226fb5aa DO |
33 | #define PTIMER_POLICY \ |
34 | (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ | |
35 | PTIMER_POLICY_CONTINUOUS_TRIGGER | \ | |
36 | PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | \ | |
37 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | \ | |
38 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) | |
39 | ||
b9dc07d4 PM |
40 | /* This device implements the per-cpu private timer and watchdog block |
41 | * which is used in both the ARM11MPCore and Cortex-A9MP. | |
42 | */ | |
43 | ||
c6205ddf | 44 | static inline int get_current_cpu(ARMMPTimerState *s) |
b9dc07d4 | 45 | { |
226fb5aa DO |
46 | int cpu_id = current_cpu ? current_cpu->cpu_index : 0; |
47 | ||
48 | if (cpu_id >= s->num_cpu) { | |
b9dc07d4 | 49 | hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", |
226fb5aa | 50 | s->num_cpu, cpu_id); |
b9dc07d4 | 51 | } |
226fb5aa DO |
52 | |
53 | return cpu_id; | |
b9dc07d4 PM |
54 | } |
55 | ||
c6205ddf | 56 | static inline void timerblock_update_irq(TimerBlock *tb) |
b9dc07d4 | 57 | { |
257621a9 | 58 | qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); |
b9dc07d4 PM |
59 | } |
60 | ||
61 | /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ | |
226fb5aa | 62 | static inline uint32_t timerblock_scale(uint32_t control) |
b9dc07d4 | 63 | { |
226fb5aa | 64 | return (((control >> 8) & 0xff) + 1) * 10; |
b9dc07d4 PM |
65 | } |
66 | ||
226fb5aa DO |
67 | static inline void timerblock_set_count(struct ptimer_state *timer, |
68 | uint32_t control, uint64_t *count) | |
b9dc07d4 | 69 | { |
226fb5aa DO |
70 | /* PTimer would trigger interrupt for periodic timer when counter set |
71 | * to 0, MPtimer under certain condition only. | |
72 | */ | |
73 | if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { | |
74 | *count = ptimer_get_limit(timer); | |
b9dc07d4 | 75 | } |
226fb5aa DO |
76 | ptimer_set_count(timer, *count); |
77 | } | |
78 | ||
79 | static inline void timerblock_run(struct ptimer_state *timer, | |
80 | uint32_t control, uint32_t load) | |
81 | { | |
82 | if ((control & 1) && ((control & 0xff00) || load != 0)) { | |
83 | ptimer_run(timer, !(control & 2)); | |
b9dc07d4 | 84 | } |
b9dc07d4 PM |
85 | } |
86 | ||
87 | static void timerblock_tick(void *opaque) | |
88 | { | |
c6205ddf | 89 | TimerBlock *tb = (TimerBlock *)opaque; |
226fb5aa DO |
90 | /* Periodic timer with load = 0 and prescaler != 0 would re-trigger |
91 | * IRQ after one period, otherwise it either stops or wraps around. | |
92 | */ | |
93 | if ((tb->control & 2) && (tb->control & 0xff00) == 0 && | |
94 | ptimer_get_limit(tb->timer) == 0) { | |
95 | ptimer_stop(tb->timer); | |
b9dc07d4 | 96 | } |
226fb5aa | 97 | tb->status = 1; |
b9dc07d4 PM |
98 | timerblock_update_irq(tb); |
99 | } | |
100 | ||
a8170e5e | 101 | static uint64_t timerblock_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
102 | unsigned size) |
103 | { | |
c6205ddf | 104 | TimerBlock *tb = (TimerBlock *)opaque; |
b9dc07d4 PM |
105 | switch (addr) { |
106 | case 0: /* Load */ | |
226fb5aa | 107 | return ptimer_get_limit(tb->timer); |
b9dc07d4 | 108 | case 4: /* Counter. */ |
226fb5aa | 109 | return ptimer_get_count(tb->timer); |
b9dc07d4 PM |
110 | case 8: /* Control. */ |
111 | return tb->control; | |
112 | case 12: /* Interrupt status. */ | |
113 | return tb->status; | |
114 | default: | |
115 | return 0; | |
116 | } | |
117 | } | |
118 | ||
a8170e5e | 119 | static void timerblock_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
120 | uint64_t value, unsigned size) |
121 | { | |
c6205ddf | 122 | TimerBlock *tb = (TimerBlock *)opaque; |
226fb5aa | 123 | uint32_t control = tb->control; |
b9dc07d4 PM |
124 | switch (addr) { |
125 | case 0: /* Load */ | |
226fb5aa DO |
126 | /* Setting load to 0 stops the timer without doing the tick if |
127 | * prescaler = 0. | |
128 | */ | |
129 | if ((control & 1) && (control & 0xff00) == 0 && value == 0) { | |
130 | ptimer_stop(tb->timer); | |
b9dc07d4 | 131 | } |
226fb5aa DO |
132 | ptimer_set_limit(tb->timer, value, 1); |
133 | timerblock_run(tb->timer, control, value); | |
134 | break; | |
135 | case 4: /* Counter. */ | |
136 | /* Setting counter to 0 stops the one-shot timer, or periodic with | |
137 | * load = 0, without doing the tick if prescaler = 0. | |
138 | */ | |
139 | if ((control & 1) && (control & 0xff00) == 0 && value == 0 && | |
140 | (!(control & 2) || ptimer_get_limit(tb->timer) == 0)) { | |
141 | ptimer_stop(tb->timer); | |
b9dc07d4 | 142 | } |
226fb5aa DO |
143 | timerblock_set_count(tb->timer, control, &value); |
144 | timerblock_run(tb->timer, control, value); | |
b9dc07d4 PM |
145 | break; |
146 | case 8: /* Control. */ | |
226fb5aa DO |
147 | if ((control & 3) != (value & 3)) { |
148 | ptimer_stop(tb->timer); | |
149 | } | |
150 | if ((control & 0xff00) != (value & 0xff00)) { | |
151 | ptimer_set_period(tb->timer, timerblock_scale(value)); | |
152 | } | |
8a52340c | 153 | if (value & 1) { |
226fb5aa DO |
154 | uint64_t count = ptimer_get_count(tb->timer); |
155 | /* Re-load periodic timer counter if needed. */ | |
156 | if ((value & 2) && count == 0) { | |
157 | timerblock_set_count(tb->timer, value, &count); | |
8a52340c | 158 | } |
226fb5aa | 159 | timerblock_run(tb->timer, value, count); |
b9dc07d4 | 160 | } |
226fb5aa | 161 | tb->control = value; |
b9dc07d4 PM |
162 | break; |
163 | case 12: /* Interrupt status. */ | |
164 | tb->status &= ~value; | |
165 | timerblock_update_irq(tb); | |
166 | break; | |
167 | } | |
168 | } | |
169 | ||
170 | /* Wrapper functions to implement the "read timer/watchdog for | |
171 | * the current CPU" memory regions. | |
172 | */ | |
a8170e5e | 173 | static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
174 | unsigned size) |
175 | { | |
c6205ddf | 176 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 177 | int id = get_current_cpu(s); |
cde4577f | 178 | return timerblock_read(&s->timerblock[id], addr, size); |
b9dc07d4 PM |
179 | } |
180 | ||
a8170e5e | 181 | static void arm_thistimer_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
182 | uint64_t value, unsigned size) |
183 | { | |
c6205ddf | 184 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 185 | int id = get_current_cpu(s); |
cde4577f | 186 | timerblock_write(&s->timerblock[id], addr, value, size); |
b9dc07d4 PM |
187 | } |
188 | ||
189 | static const MemoryRegionOps arm_thistimer_ops = { | |
190 | .read = arm_thistimer_read, | |
191 | .write = arm_thistimer_write, | |
192 | .valid = { | |
193 | .min_access_size = 4, | |
194 | .max_access_size = 4, | |
195 | }, | |
196 | .endianness = DEVICE_NATIVE_ENDIAN, | |
197 | }; | |
198 | ||
b9dc07d4 PM |
199 | static const MemoryRegionOps timerblock_ops = { |
200 | .read = timerblock_read, | |
201 | .write = timerblock_write, | |
202 | .valid = { | |
203 | .min_access_size = 4, | |
204 | .max_access_size = 4, | |
205 | }, | |
206 | .endianness = DEVICE_NATIVE_ENDIAN, | |
207 | }; | |
208 | ||
c6205ddf | 209 | static void timerblock_reset(TimerBlock *tb) |
b9dc07d4 | 210 | { |
b9dc07d4 PM |
211 | tb->control = 0; |
212 | tb->status = 0; | |
bdac1c1e | 213 | if (tb->timer) { |
226fb5aa DO |
214 | ptimer_stop(tb->timer); |
215 | ptimer_set_limit(tb->timer, 0, 1); | |
216 | ptimer_set_period(tb->timer, timerblock_scale(0)); | |
bdac1c1e | 217 | } |
b9dc07d4 PM |
218 | } |
219 | ||
220 | static void arm_mptimer_reset(DeviceState *dev) | |
221 | { | |
68653fd6 | 222 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
b9dc07d4 | 223 | int i; |
68653fd6 | 224 | |
b9dc07d4 PM |
225 | for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { |
226 | timerblock_reset(&s->timerblock[i]); | |
227 | } | |
228 | } | |
229 | ||
0aadb490 | 230 | static void arm_mptimer_init(Object *obj) |
b9dc07d4 | 231 | { |
0aadb490 AF |
232 | ARMMPTimerState *s = ARM_MPTIMER(obj); |
233 | ||
234 | memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, | |
235 | "arm_mptimer_timer", 0x20); | |
236 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | |
237 | } | |
238 | ||
239 | static void arm_mptimer_realize(DeviceState *dev, Error **errp) | |
240 | { | |
241 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
68653fd6 | 242 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
b9dc07d4 | 243 | int i; |
68653fd6 | 244 | |
eb110bd8 | 245 | if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { |
b097e481 MA |
246 | error_setg(errp, "num-cpu must be between 1 and %d", |
247 | ARM_MPTIMER_MAX_CPUS); | |
248 | return; | |
b9dc07d4 | 249 | } |
cde4577f | 250 | /* We implement one timer block per CPU, and expose multiple MMIO regions: |
b9dc07d4 | 251 | * * region 0 is "timer for this core" |
cde4577f PC |
252 | * * region 1 is "timer for core 0" |
253 | * * region 2 is "timer for core 1" | |
b9dc07d4 PM |
254 | * and so on. |
255 | * The outgoing interrupt lines are | |
256 | * * timer for core 0 | |
b9dc07d4 | 257 | * * timer for core 1 |
b9dc07d4 PM |
258 | * and so on. |
259 | */ | |
cde4577f | 260 | for (i = 0; i < s->num_cpu; i++) { |
c6205ddf | 261 | TimerBlock *tb = &s->timerblock[i]; |
226fb5aa DO |
262 | QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); |
263 | tb->timer = ptimer_init(bh, PTIMER_POLICY); | |
0aadb490 | 264 | sysbus_init_irq(sbd, &tb->irq); |
853dca12 | 265 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, |
b9dc07d4 | 266 | "arm_mptimer_timerblock", 0x20); |
0aadb490 | 267 | sysbus_init_mmio(sbd, &tb->iomem); |
b9dc07d4 | 268 | } |
b9dc07d4 PM |
269 | } |
270 | ||
271 | static const VMStateDescription vmstate_timerblock = { | |
272 | .name = "arm_mptimer_timerblock", | |
226fb5aa DO |
273 | .version_id = 3, |
274 | .minimum_version_id = 3, | |
b9dc07d4 | 275 | .fields = (VMStateField[]) { |
c6205ddf PC |
276 | VMSTATE_UINT32(control, TimerBlock), |
277 | VMSTATE_UINT32(status, TimerBlock), | |
226fb5aa | 278 | VMSTATE_PTIMER(timer, TimerBlock), |
b9dc07d4 PM |
279 | VMSTATE_END_OF_LIST() |
280 | } | |
281 | }; | |
282 | ||
283 | static const VMStateDescription vmstate_arm_mptimer = { | |
284 | .name = "arm_mptimer", | |
226fb5aa DO |
285 | .version_id = 3, |
286 | .minimum_version_id = 3, | |
b9dc07d4 | 287 | .fields = (VMStateField[]) { |
cde4577f | 288 | VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, |
226fb5aa | 289 | 3, vmstate_timerblock, TimerBlock), |
b9dc07d4 PM |
290 | VMSTATE_END_OF_LIST() |
291 | } | |
292 | }; | |
293 | ||
39bffca2 | 294 | static Property arm_mptimer_properties[] = { |
c6205ddf | 295 | DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), |
39bffca2 AL |
296 | DEFINE_PROP_END_OF_LIST() |
297 | }; | |
298 | ||
999e12bb AL |
299 | static void arm_mptimer_class_init(ObjectClass *klass, void *data) |
300 | { | |
39bffca2 | 301 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 302 | |
0aadb490 | 303 | dc->realize = arm_mptimer_realize; |
39bffca2 AL |
304 | dc->vmsd = &vmstate_arm_mptimer; |
305 | dc->reset = arm_mptimer_reset; | |
39bffca2 | 306 | dc->props = arm_mptimer_properties; |
999e12bb AL |
307 | } |
308 | ||
8c43a6f0 | 309 | static const TypeInfo arm_mptimer_info = { |
68653fd6 | 310 | .name = TYPE_ARM_MPTIMER, |
39bffca2 | 311 | .parent = TYPE_SYS_BUS_DEVICE, |
c6205ddf | 312 | .instance_size = sizeof(ARMMPTimerState), |
0aadb490 | 313 | .instance_init = arm_mptimer_init, |
39bffca2 | 314 | .class_init = arm_mptimer_class_init, |
b9dc07d4 PM |
315 | }; |
316 | ||
83f7d43a | 317 | static void arm_mptimer_register_types(void) |
b9dc07d4 | 318 | { |
39bffca2 | 319 | type_register_static(&arm_mptimer_info); |
b9dc07d4 PM |
320 | } |
321 | ||
83f7d43a | 322 | type_init(arm_mptimer_register_types) |