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0f3a4a01 FC |
1 | /* |
2 | * QEMU GRLIB GPTimer Emulator | |
3 | * | |
948caec8 | 4 | * Copyright (c) 2010-2019 AdaCore |
0f3a4a01 FC |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
db5ebe5f | 25 | #include "qemu/osdep.h" |
948caec8 | 26 | #include "hw/sparc/grlib.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
64552b6b | 29 | #include "hw/irq.h" |
83c9f4ca | 30 | #include "hw/ptimer.h" |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
0b8fa32f | 32 | #include "qemu/module.h" |
0f3a4a01 FC |
33 | |
34 | #include "trace.h" | |
db1015e9 | 35 | #include "qom/object.h" |
0f3a4a01 FC |
36 | |
37 | #define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */ | |
38 | #define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */ | |
39 | ||
40 | #define GPTIMER_MAX_TIMERS 8 | |
41 | ||
42 | /* GPTimer Config register fields */ | |
43 | #define GPTIMER_ENABLE (1 << 0) | |
44 | #define GPTIMER_RESTART (1 << 1) | |
45 | #define GPTIMER_LOAD (1 << 2) | |
46 | #define GPTIMER_INT_ENABLE (1 << 3) | |
47 | #define GPTIMER_INT_PENDING (1 << 4) | |
48 | #define GPTIMER_CHAIN (1 << 5) /* Not supported */ | |
49 | #define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */ | |
50 | ||
51 | /* Memory mapped register offsets */ | |
52 | #define SCALER_OFFSET 0x00 | |
53 | #define SCALER_RELOAD_OFFSET 0x04 | |
54 | #define CONFIG_OFFSET 0x08 | |
55 | #define COUNTER_OFFSET 0x00 | |
56 | #define COUNTER_RELOAD_OFFSET 0x04 | |
57 | #define TIMER_BASE 0x10 | |
58 | ||
db1015e9 | 59 | typedef struct GPTimerUnit GPTimerUnit; |
541ab55f AF |
60 | #define GRLIB_GPTIMER(obj) \ |
61 | OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER) | |
62 | ||
0f3a4a01 | 63 | typedef struct GPTimer GPTimer; |
0f3a4a01 FC |
64 | |
65 | struct GPTimer { | |
0f3a4a01 FC |
66 | struct ptimer_state *ptimer; |
67 | ||
68 | qemu_irq irq; | |
69 | int id; | |
70 | GPTimerUnit *unit; | |
71 | ||
72 | /* registers */ | |
73 | uint32_t counter; | |
74 | uint32_t reload; | |
75 | uint32_t config; | |
76 | }; | |
77 | ||
78 | struct GPTimerUnit { | |
541ab55f AF |
79 | SysBusDevice parent_obj; |
80 | ||
cde844fa | 81 | MemoryRegion iomem; |
0f3a4a01 FC |
82 | |
83 | uint32_t nr_timers; /* Number of timers available */ | |
84 | uint32_t freq_hz; /* System frequency */ | |
85 | uint32_t irq_line; /* Base irq line */ | |
86 | ||
87 | GPTimer *timers; | |
88 | ||
89 | /* registers */ | |
90 | uint32_t scaler; | |
91 | uint32_t reload; | |
92 | uint32_t config; | |
93 | }; | |
94 | ||
663e475f PM |
95 | static void grlib_gptimer_tx_begin(GPTimer *timer) |
96 | { | |
97 | ptimer_transaction_begin(timer->ptimer); | |
98 | } | |
99 | ||
100 | static void grlib_gptimer_tx_commit(GPTimer *timer) | |
101 | { | |
102 | ptimer_transaction_commit(timer->ptimer); | |
103 | } | |
104 | ||
105 | /* Must be called within grlib_gptimer_tx_begin/commit block */ | |
0f3a4a01 FC |
106 | static void grlib_gptimer_enable(GPTimer *timer) |
107 | { | |
108 | assert(timer != NULL); | |
109 | ||
110 | ||
111 | ptimer_stop(timer->ptimer); | |
112 | ||
113 | if (!(timer->config & GPTIMER_ENABLE)) { | |
114 | /* Timer disabled */ | |
115 | trace_grlib_gptimer_disabled(timer->id, timer->config); | |
116 | return; | |
117 | } | |
118 | ||
119 | /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at | |
120 | underflow. Set count + 1 to simulate the GPTimer behavior. */ | |
121 | ||
9d5614d5 | 122 | trace_grlib_gptimer_enable(timer->id, timer->counter); |
0f3a4a01 | 123 | |
9d5614d5 | 124 | ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1); |
0f3a4a01 FC |
125 | ptimer_run(timer->ptimer, 1); |
126 | } | |
127 | ||
663e475f | 128 | /* Must be called within grlib_gptimer_tx_begin/commit block */ |
0f3a4a01 FC |
129 | static void grlib_gptimer_restart(GPTimer *timer) |
130 | { | |
131 | assert(timer != NULL); | |
132 | ||
133 | trace_grlib_gptimer_restart(timer->id, timer->reload); | |
134 | ||
135 | timer->counter = timer->reload; | |
136 | grlib_gptimer_enable(timer); | |
137 | } | |
138 | ||
139 | static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler) | |
140 | { | |
141 | int i = 0; | |
142 | uint32_t value = 0; | |
143 | ||
144 | assert(unit != NULL); | |
145 | ||
146 | if (scaler > 0) { | |
147 | value = unit->freq_hz / (scaler + 1); | |
148 | } else { | |
149 | value = unit->freq_hz; | |
150 | } | |
151 | ||
152 | trace_grlib_gptimer_set_scaler(scaler, value); | |
153 | ||
154 | for (i = 0; i < unit->nr_timers; i++) { | |
663e475f | 155 | ptimer_transaction_begin(unit->timers[i].ptimer); |
0f3a4a01 | 156 | ptimer_set_freq(unit->timers[i].ptimer, value); |
663e475f | 157 | ptimer_transaction_commit(unit->timers[i].ptimer); |
0f3a4a01 FC |
158 | } |
159 | } | |
160 | ||
161 | static void grlib_gptimer_hit(void *opaque) | |
162 | { | |
163 | GPTimer *timer = opaque; | |
164 | assert(timer != NULL); | |
165 | ||
166 | trace_grlib_gptimer_hit(timer->id); | |
167 | ||
168 | /* Timer expired */ | |
169 | ||
170 | if (timer->config & GPTIMER_INT_ENABLE) { | |
171 | /* Set the pending bit (only unset by write in the config register) */ | |
172 | timer->config |= GPTIMER_INT_PENDING; | |
173 | qemu_irq_pulse(timer->irq); | |
174 | } | |
175 | ||
176 | if (timer->config & GPTIMER_RESTART) { | |
177 | grlib_gptimer_restart(timer); | |
178 | } | |
179 | } | |
180 | ||
a8170e5e | 181 | static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr, |
cde844fa | 182 | unsigned size) |
0f3a4a01 FC |
183 | { |
184 | GPTimerUnit *unit = opaque; | |
a8170e5e | 185 | hwaddr timer_addr; |
0f3a4a01 FC |
186 | int id; |
187 | uint32_t value = 0; | |
188 | ||
189 | addr &= 0xff; | |
190 | ||
191 | /* Unit registers */ | |
192 | switch (addr) { | |
193 | case SCALER_OFFSET: | |
b4548fcc | 194 | trace_grlib_gptimer_readl(-1, addr, unit->scaler); |
0f3a4a01 FC |
195 | return unit->scaler; |
196 | ||
197 | case SCALER_RELOAD_OFFSET: | |
b4548fcc | 198 | trace_grlib_gptimer_readl(-1, addr, unit->reload); |
0f3a4a01 FC |
199 | return unit->reload; |
200 | ||
201 | case CONFIG_OFFSET: | |
b4548fcc | 202 | trace_grlib_gptimer_readl(-1, addr, unit->config); |
0f3a4a01 FC |
203 | return unit->config; |
204 | ||
205 | default: | |
206 | break; | |
207 | } | |
208 | ||
209 | timer_addr = (addr % TIMER_BASE); | |
210 | id = (addr - TIMER_BASE) / TIMER_BASE; | |
211 | ||
212 | if (id >= 0 && id < unit->nr_timers) { | |
213 | ||
214 | /* GPTimer registers */ | |
215 | switch (timer_addr) { | |
216 | case COUNTER_OFFSET: | |
217 | value = ptimer_get_count(unit->timers[id].ptimer); | |
b4548fcc | 218 | trace_grlib_gptimer_readl(id, addr, value); |
0f3a4a01 FC |
219 | return value; |
220 | ||
221 | case COUNTER_RELOAD_OFFSET: | |
222 | value = unit->timers[id].reload; | |
b4548fcc | 223 | trace_grlib_gptimer_readl(id, addr, value); |
0f3a4a01 FC |
224 | return value; |
225 | ||
226 | case CONFIG_OFFSET: | |
b4548fcc | 227 | trace_grlib_gptimer_readl(id, addr, unit->timers[id].config); |
0f3a4a01 FC |
228 | return unit->timers[id].config; |
229 | ||
230 | default: | |
231 | break; | |
232 | } | |
233 | ||
234 | } | |
235 | ||
b4548fcc | 236 | trace_grlib_gptimer_readl(-1, addr, 0); |
0f3a4a01 FC |
237 | return 0; |
238 | } | |
239 | ||
a8170e5e | 240 | static void grlib_gptimer_write(void *opaque, hwaddr addr, |
cde844fa | 241 | uint64_t value, unsigned size) |
0f3a4a01 FC |
242 | { |
243 | GPTimerUnit *unit = opaque; | |
a8170e5e | 244 | hwaddr timer_addr; |
0f3a4a01 FC |
245 | int id; |
246 | ||
247 | addr &= 0xff; | |
248 | ||
249 | /* Unit registers */ | |
250 | switch (addr) { | |
251 | case SCALER_OFFSET: | |
252 | value &= 0xFFFF; /* clean up the value */ | |
253 | unit->scaler = value; | |
b4548fcc | 254 | trace_grlib_gptimer_writel(-1, addr, unit->scaler); |
0f3a4a01 FC |
255 | return; |
256 | ||
257 | case SCALER_RELOAD_OFFSET: | |
258 | value &= 0xFFFF; /* clean up the value */ | |
259 | unit->reload = value; | |
b4548fcc | 260 | trace_grlib_gptimer_writel(-1, addr, unit->reload); |
0f3a4a01 FC |
261 | grlib_gptimer_set_scaler(unit, value); |
262 | return; | |
263 | ||
264 | case CONFIG_OFFSET: | |
265 | /* Read Only (disable timer freeze not supported) */ | |
b4548fcc | 266 | trace_grlib_gptimer_writel(-1, addr, 0); |
0f3a4a01 FC |
267 | return; |
268 | ||
269 | default: | |
270 | break; | |
271 | } | |
272 | ||
273 | timer_addr = (addr % TIMER_BASE); | |
274 | id = (addr - TIMER_BASE) / TIMER_BASE; | |
275 | ||
276 | if (id >= 0 && id < unit->nr_timers) { | |
277 | ||
278 | /* GPTimer registers */ | |
279 | switch (timer_addr) { | |
280 | case COUNTER_OFFSET: | |
b4548fcc | 281 | trace_grlib_gptimer_writel(id, addr, value); |
663e475f | 282 | grlib_gptimer_tx_begin(&unit->timers[id]); |
0f3a4a01 FC |
283 | unit->timers[id].counter = value; |
284 | grlib_gptimer_enable(&unit->timers[id]); | |
663e475f | 285 | grlib_gptimer_tx_commit(&unit->timers[id]); |
0f3a4a01 FC |
286 | return; |
287 | ||
288 | case COUNTER_RELOAD_OFFSET: | |
b4548fcc | 289 | trace_grlib_gptimer_writel(id, addr, value); |
0f3a4a01 FC |
290 | unit->timers[id].reload = value; |
291 | return; | |
292 | ||
293 | case CONFIG_OFFSET: | |
b4548fcc | 294 | trace_grlib_gptimer_writel(id, addr, value); |
0f3a4a01 FC |
295 | |
296 | if (value & GPTIMER_INT_PENDING) { | |
297 | /* clear pending bit */ | |
298 | value &= ~GPTIMER_INT_PENDING; | |
299 | } else { | |
300 | /* keep pending bit */ | |
301 | value |= unit->timers[id].config & GPTIMER_INT_PENDING; | |
302 | } | |
303 | ||
304 | unit->timers[id].config = value; | |
305 | ||
306 | /* gptimer_restart calls gptimer_enable, so if "enable" and "load" | |
307 | bits are present, we just have to call restart. */ | |
308 | ||
663e475f | 309 | grlib_gptimer_tx_begin(&unit->timers[id]); |
0f3a4a01 FC |
310 | if (value & GPTIMER_LOAD) { |
311 | grlib_gptimer_restart(&unit->timers[id]); | |
312 | } else if (value & GPTIMER_ENABLE) { | |
313 | grlib_gptimer_enable(&unit->timers[id]); | |
314 | } | |
315 | ||
316 | /* These fields must always be read as 0 */ | |
317 | value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT); | |
318 | ||
319 | unit->timers[id].config = value; | |
663e475f | 320 | grlib_gptimer_tx_commit(&unit->timers[id]); |
0f3a4a01 FC |
321 | return; |
322 | ||
323 | default: | |
324 | break; | |
325 | } | |
326 | ||
327 | } | |
328 | ||
b4548fcc | 329 | trace_grlib_gptimer_writel(-1, addr, value); |
0f3a4a01 FC |
330 | } |
331 | ||
cde844fa AK |
332 | static const MemoryRegionOps grlib_gptimer_ops = { |
333 | .read = grlib_gptimer_read, | |
334 | .write = grlib_gptimer_write, | |
335 | .endianness = DEVICE_NATIVE_ENDIAN, | |
336 | .valid = { | |
337 | .min_access_size = 4, | |
338 | .max_access_size = 4, | |
339 | }, | |
0f3a4a01 FC |
340 | }; |
341 | ||
342 | static void grlib_gptimer_reset(DeviceState *d) | |
343 | { | |
541ab55f | 344 | GPTimerUnit *unit = GRLIB_GPTIMER(d); |
0f3a4a01 FC |
345 | int i = 0; |
346 | ||
347 | assert(unit != NULL); | |
348 | ||
349 | unit->scaler = 0; | |
350 | unit->reload = 0; | |
0f3a4a01 FC |
351 | |
352 | unit->config = unit->nr_timers; | |
353 | unit->config |= unit->irq_line << 3; | |
354 | unit->config |= 1 << 8; /* separate interrupt */ | |
355 | unit->config |= 1 << 9; /* Disable timer freeze */ | |
356 | ||
357 | ||
358 | for (i = 0; i < unit->nr_timers; i++) { | |
359 | GPTimer *timer = &unit->timers[i]; | |
360 | ||
361 | timer->counter = 0; | |
362 | timer->reload = 0; | |
363 | timer->config = 0; | |
663e475f | 364 | ptimer_transaction_begin(timer->ptimer); |
0f3a4a01 FC |
365 | ptimer_stop(timer->ptimer); |
366 | ptimer_set_count(timer->ptimer, 0); | |
367 | ptimer_set_freq(timer->ptimer, unit->freq_hz); | |
663e475f | 368 | ptimer_transaction_commit(timer->ptimer); |
0f3a4a01 FC |
369 | } |
370 | } | |
371 | ||
23251fb8 | 372 | static void grlib_gptimer_realize(DeviceState *dev, Error **errp) |
0f3a4a01 | 373 | { |
541ab55f | 374 | GPTimerUnit *unit = GRLIB_GPTIMER(dev); |
0f3a4a01 | 375 | unsigned int i; |
23251fb8 | 376 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
0f3a4a01 FC |
377 | |
378 | assert(unit->nr_timers > 0); | |
379 | assert(unit->nr_timers <= GPTIMER_MAX_TIMERS); | |
380 | ||
7267c094 | 381 | unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers); |
0f3a4a01 FC |
382 | |
383 | for (i = 0; i < unit->nr_timers; i++) { | |
384 | GPTimer *timer = &unit->timers[i]; | |
385 | ||
386 | timer->unit = unit; | |
663e475f PM |
387 | timer->ptimer = ptimer_init(grlib_gptimer_hit, timer, |
388 | PTIMER_POLICY_DEFAULT); | |
0f3a4a01 FC |
389 | timer->id = i; |
390 | ||
391 | /* One IRQ line for each timer */ | |
23251fb8 | 392 | sysbus_init_irq(sbd, &timer->irq); |
0f3a4a01 | 393 | |
663e475f | 394 | ptimer_transaction_begin(timer->ptimer); |
0f3a4a01 | 395 | ptimer_set_freq(timer->ptimer, unit->freq_hz); |
663e475f | 396 | ptimer_transaction_commit(timer->ptimer); |
0f3a4a01 FC |
397 | } |
398 | ||
853dca12 PB |
399 | memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops, |
400 | unit, "gptimer", | |
cde844fa | 401 | UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers); |
0f3a4a01 | 402 | |
23251fb8 | 403 | sysbus_init_mmio(sbd, &unit->iomem); |
0f3a4a01 FC |
404 | } |
405 | ||
999e12bb AL |
406 | static Property grlib_gptimer_properties[] = { |
407 | DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000), | |
408 | DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8), | |
409 | DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2), | |
410 | DEFINE_PROP_END_OF_LIST(), | |
411 | }; | |
412 | ||
413 | static void grlib_gptimer_class_init(ObjectClass *klass, void *data) | |
414 | { | |
39bffca2 | 415 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 416 | |
23251fb8 | 417 | dc->realize = grlib_gptimer_realize; |
39bffca2 | 418 | dc->reset = grlib_gptimer_reset; |
4f67d30b | 419 | device_class_set_props(dc, grlib_gptimer_properties); |
999e12bb AL |
420 | } |
421 | ||
8c43a6f0 | 422 | static const TypeInfo grlib_gptimer_info = { |
541ab55f | 423 | .name = TYPE_GRLIB_GPTIMER, |
39bffca2 AL |
424 | .parent = TYPE_SYS_BUS_DEVICE, |
425 | .instance_size = sizeof(GPTimerUnit), | |
426 | .class_init = grlib_gptimer_class_init, | |
0f3a4a01 FC |
427 | }; |
428 | ||
83f7d43a | 429 | static void grlib_gptimer_register_types(void) |
0f3a4a01 | 430 | { |
39bffca2 | 431 | type_register_static(&grlib_gptimer_info); |
0f3a4a01 FC |
432 | } |
433 | ||
83f7d43a | 434 | type_init(grlib_gptimer_register_types) |