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Commit | Line | Data |
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bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
0b8fa32f | 28 | |
e532b2e0 | 29 | #include "qemu/osdep.h" |
f1ae32a1 | 30 | #include "hw/usb.h" |
9a1d111e | 31 | #include "hw/usb/uhci-regs.h" |
d6454270 | 32 | #include "migration/vmstate.h" |
a2cb15b0 | 33 | #include "hw/pci/pci.h" |
a27bd6c7 | 34 | #include "hw/qdev-properties.h" |
da34e65c | 35 | #include "qapi/error.h" |
1de7afc9 PB |
36 | #include "qemu/timer.h" |
37 | #include "qemu/iov.h" | |
9c17d615 | 38 | #include "sysemu/dma.h" |
50dcc0f8 | 39 | #include "trace.h" |
6a1751b7 | 40 | #include "qemu/main-loop.h" |
0b8fa32f | 41 | #include "qemu/module.h" |
db1015e9 | 42 | #include "qom/object.h" |
bb36d470 | 43 | |
bb36d470 FB |
44 | #define FRAME_TIMER_FREQ 1000 |
45 | ||
3200d108 | 46 | #define FRAME_MAX_LOOPS 256 |
bb36d470 | 47 | |
475443cf HG |
48 | /* Must be large enough to handle 10 frame delay for initial isoc requests */ |
49 | #define QH_VALID 32 | |
50 | ||
f8f48b69 HG |
51 | #define MAX_FRAMES_PER_TICK (QH_VALID / 2) |
52 | ||
bb36d470 FB |
53 | #define NB_PORTS 2 |
54 | ||
60e1b2a6 | 55 | enum { |
0cd178ca GH |
56 | TD_RESULT_STOP_FRAME = 10, |
57 | TD_RESULT_COMPLETE, | |
58 | TD_RESULT_NEXT_QH, | |
4efe4ef3 GH |
59 | TD_RESULT_ASYNC_START, |
60 | TD_RESULT_ASYNC_CONT, | |
60e1b2a6 GH |
61 | }; |
62 | ||
7b5a44c5 | 63 | typedef struct UHCIState UHCIState; |
f8af1e88 GH |
64 | typedef struct UHCIAsync UHCIAsync; |
65 | typedef struct UHCIQueue UHCIQueue; | |
2c2e8525 | 66 | typedef struct UHCIInfo UHCIInfo; |
8f3f90b0 | 67 | typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; |
2c2e8525 GH |
68 | |
69 | struct UHCIInfo { | |
70 | const char *name; | |
71 | uint16_t vendor_id; | |
72 | uint16_t device_id; | |
73 | uint8_t revision; | |
8f3f90b0 | 74 | uint8_t irq_pin; |
63216dc7 | 75 | void (*realize)(PCIDevice *dev, Error **errp); |
2c2e8525 GH |
76 | bool unplug; |
77 | }; | |
7b5a44c5 | 78 | |
8f3f90b0 GH |
79 | struct UHCIPCIDeviceClass { |
80 | PCIDeviceClass parent_class; | |
81 | UHCIInfo info; | |
82 | }; | |
83 | ||
54f254f9 AL |
84 | /* |
85 | * Pending async transaction. | |
86 | * 'packet' must be the first field because completion | |
87 | * handler does "(UHCIAsync *) pkt" cast. | |
88 | */ | |
f8af1e88 GH |
89 | |
90 | struct UHCIAsync { | |
54f254f9 | 91 | USBPacket packet; |
9822261c HG |
92 | uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ |
93 | uint8_t *buf; | |
f8af1e88 | 94 | UHCIQueue *queue; |
ddf6583f | 95 | QTAILQ_ENTRY(UHCIAsync) next; |
1f250cc7 | 96 | uint32_t td_addr; |
54f254f9 | 97 | uint8_t done; |
f8af1e88 GH |
98 | }; |
99 | ||
100 | struct UHCIQueue { | |
66a08cbe | 101 | uint32_t qh_addr; |
f8af1e88 GH |
102 | uint32_t token; |
103 | UHCIState *uhci; | |
11d15e40 | 104 | USBEndpoint *ep; |
f8af1e88 | 105 | QTAILQ_ENTRY(UHCIQueue) next; |
eae3eb3e | 106 | QTAILQ_HEAD(, UHCIAsync) asyncs; |
f8af1e88 GH |
107 | int8_t valid; |
108 | }; | |
54f254f9 | 109 | |
bb36d470 FB |
110 | typedef struct UHCIPort { |
111 | USBPort port; | |
112 | uint16_t ctrl; | |
bb36d470 FB |
113 | } UHCIPort; |
114 | ||
7b5a44c5 | 115 | struct UHCIState { |
bb36d470 | 116 | PCIDevice dev; |
a03f66e4 | 117 | MemoryRegion io_bar; |
35e4977f | 118 | USBBus bus; /* Note unused when we're a companion controller */ |
bb36d470 FB |
119 | uint16_t cmd; /* cmd register */ |
120 | uint16_t status; | |
121 | uint16_t intr; /* interrupt enable register */ | |
122 | uint16_t frnum; /* frame number */ | |
123 | uint32_t fl_base_addr; /* frame list base address */ | |
124 | uint8_t sof_timing; | |
125 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 126 | int64_t expire_time; |
bb36d470 | 127 | QEMUTimer *frame_timer; |
9a16c595 | 128 | QEMUBH *bh; |
4aed20e2 | 129 | uint32_t frame_bytes; |
40141d12 | 130 | uint32_t frame_bandwidth; |
88793816 | 131 | bool completions_only; |
bb36d470 | 132 | UHCIPort ports[NB_PORTS]; |
4d611c9a PB |
133 | |
134 | /* Interrupts that should be raised at the end of the current frame. */ | |
135 | uint32_t pending_int_mask; | |
54f254f9 AL |
136 | |
137 | /* Active packets */ | |
f8af1e88 | 138 | QTAILQ_HEAD(, UHCIQueue) queues; |
64e58fe5 | 139 | uint8_t num_ports_vmstate; |
35e4977f HG |
140 | |
141 | /* Properties */ | |
142 | char *masterbus; | |
143 | uint32_t firstport; | |
9fdf7027 | 144 | uint32_t maxframes; |
7b5a44c5 | 145 | }; |
bb36d470 FB |
146 | |
147 | typedef struct UHCI_TD { | |
148 | uint32_t link; | |
149 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
150 | uint32_t token; | |
151 | uint32_t buffer; | |
152 | } UHCI_TD; | |
153 | ||
154 | typedef struct UHCI_QH { | |
155 | uint32_t link; | |
156 | uint32_t el_link; | |
157 | } UHCI_QH; | |
158 | ||
40507377 | 159 | static void uhci_async_cancel(UHCIAsync *async); |
11d15e40 | 160 | static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); |
9f0f1a0c | 161 | static void uhci_resume(void *opaque); |
40507377 | 162 | |
49184b62 GA |
163 | #define TYPE_UHCI "pci-uhci-usb" |
164 | #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI) | |
165 | ||
f8af1e88 GH |
166 | static inline int32_t uhci_queue_token(UHCI_TD *td) |
167 | { | |
6fe30910 HG |
168 | if ((td->token & (0xf << 15)) == 0) { |
169 | /* ctrl ep, cover ep and dev, not pid! */ | |
170 | return td->token & 0x7ff00; | |
171 | } else { | |
172 | /* covers ep, dev, pid -> identifies the endpoint */ | |
173 | return td->token & 0x7ffff; | |
174 | } | |
f8af1e88 GH |
175 | } |
176 | ||
66a08cbe HG |
177 | static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, |
178 | USBEndpoint *ep) | |
f8af1e88 | 179 | { |
f8af1e88 GH |
180 | UHCIQueue *queue; |
181 | ||
f8af1e88 GH |
182 | queue = g_new0(UHCIQueue, 1); |
183 | queue->uhci = s; | |
66a08cbe HG |
184 | queue->qh_addr = qh_addr; |
185 | queue->token = uhci_queue_token(td); | |
11d15e40 | 186 | queue->ep = ep; |
f8af1e88 GH |
187 | QTAILQ_INIT(&queue->asyncs); |
188 | QTAILQ_INSERT_HEAD(&s->queues, queue, next); | |
475443cf | 189 | queue->valid = QH_VALID; |
50dcc0f8 | 190 | trace_usb_uhci_queue_add(queue->token); |
f8af1e88 GH |
191 | return queue; |
192 | } | |
193 | ||
66a08cbe | 194 | static void uhci_queue_free(UHCIQueue *queue, const char *reason) |
f8af1e88 GH |
195 | { |
196 | UHCIState *s = queue->uhci; | |
40507377 HG |
197 | UHCIAsync *async; |
198 | ||
199 | while (!QTAILQ_EMPTY(&queue->asyncs)) { | |
200 | async = QTAILQ_FIRST(&queue->asyncs); | |
201 | uhci_async_cancel(async); | |
202 | } | |
f79738b0 | 203 | usb_device_ep_stopped(queue->ep->dev, queue->ep); |
f8af1e88 | 204 | |
66a08cbe | 205 | trace_usb_uhci_queue_del(queue->token, reason); |
f8af1e88 GH |
206 | QTAILQ_REMOVE(&s->queues, queue, next); |
207 | g_free(queue); | |
208 | } | |
209 | ||
66a08cbe HG |
210 | static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) |
211 | { | |
212 | uint32_t token = uhci_queue_token(td); | |
213 | UHCIQueue *queue; | |
214 | ||
215 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
216 | if (queue->token == token) { | |
217 | return queue; | |
218 | } | |
219 | } | |
220 | return NULL; | |
221 | } | |
222 | ||
223 | static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, | |
224 | uint32_t td_addr, bool queuing) | |
225 | { | |
226 | UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); | |
c348e481 | 227 | uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; |
66a08cbe HG |
228 | |
229 | return queue->qh_addr == qh_addr && | |
230 | queue->token == uhci_queue_token(td) && | |
c348e481 | 231 | queue_token_addr == queue->ep->dev->addr && |
66a08cbe HG |
232 | (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || |
233 | first->td_addr == td_addr); | |
234 | } | |
235 | ||
1f250cc7 | 236 | static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) |
54f254f9 | 237 | { |
326700e3 | 238 | UHCIAsync *async = g_new0(UHCIAsync, 1); |
487414f1 | 239 | |
f8af1e88 | 240 | async->queue = queue; |
1f250cc7 | 241 | async->td_addr = td_addr; |
4f4321c1 | 242 | usb_packet_init(&async->packet); |
1f250cc7 | 243 | trace_usb_uhci_packet_add(async->queue->token, async->td_addr); |
54f254f9 AL |
244 | |
245 | return async; | |
246 | } | |
247 | ||
f8af1e88 | 248 | static void uhci_async_free(UHCIAsync *async) |
54f254f9 | 249 | { |
1f250cc7 | 250 | trace_usb_uhci_packet_del(async->queue->token, async->td_addr); |
4f4321c1 | 251 | usb_packet_cleanup(&async->packet); |
9822261c HG |
252 | if (async->buf != async->static_buf) { |
253 | g_free(async->buf); | |
254 | } | |
7267c094 | 255 | g_free(async); |
54f254f9 AL |
256 | } |
257 | ||
f8af1e88 | 258 | static void uhci_async_link(UHCIAsync *async) |
54f254f9 | 259 | { |
f8af1e88 GH |
260 | UHCIQueue *queue = async->queue; |
261 | QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); | |
1f250cc7 | 262 | trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); |
54f254f9 AL |
263 | } |
264 | ||
f8af1e88 | 265 | static void uhci_async_unlink(UHCIAsync *async) |
54f254f9 | 266 | { |
f8af1e88 GH |
267 | UHCIQueue *queue = async->queue; |
268 | QTAILQ_REMOVE(&queue->asyncs, async, next); | |
1f250cc7 | 269 | trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); |
54f254f9 AL |
270 | } |
271 | ||
f8af1e88 | 272 | static void uhci_async_cancel(UHCIAsync *async) |
54f254f9 | 273 | { |
2f2ee268 | 274 | uhci_async_unlink(async); |
1f250cc7 HG |
275 | trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, |
276 | async->done); | |
54f254f9 AL |
277 | if (!async->done) |
278 | usb_cancel_packet(&async->packet); | |
f8af1e88 | 279 | uhci_async_free(async); |
54f254f9 AL |
280 | } |
281 | ||
282 | /* | |
283 | * Mark all outstanding async packets as invalid. | |
284 | * This is used for canceling them when TDs are removed by the HCD. | |
285 | */ | |
f8af1e88 | 286 | static void uhci_async_validate_begin(UHCIState *s) |
54f254f9 | 287 | { |
f8af1e88 | 288 | UHCIQueue *queue; |
54f254f9 | 289 | |
f8af1e88 GH |
290 | QTAILQ_FOREACH(queue, &s->queues, next) { |
291 | queue->valid--; | |
54f254f9 | 292 | } |
54f254f9 AL |
293 | } |
294 | ||
295 | /* | |
296 | * Cancel async packets that are no longer valid | |
297 | */ | |
298 | static void uhci_async_validate_end(UHCIState *s) | |
299 | { | |
f8af1e88 | 300 | UHCIQueue *queue, *n; |
54f254f9 | 301 | |
f8af1e88 | 302 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
40507377 | 303 | if (!queue->valid) { |
66a08cbe | 304 | uhci_queue_free(queue, "validate-end"); |
f8af1e88 | 305 | } |
54f254f9 AL |
306 | } |
307 | } | |
308 | ||
07771f6f GH |
309 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
310 | { | |
5ad23e87 | 311 | UHCIQueue *queue, *n; |
07771f6f | 312 | |
5ad23e87 HG |
313 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
314 | if (queue->ep->dev == dev) { | |
315 | uhci_queue_free(queue, "cancel-device"); | |
07771f6f | 316 | } |
07771f6f GH |
317 | } |
318 | } | |
319 | ||
54f254f9 AL |
320 | static void uhci_async_cancel_all(UHCIState *s) |
321 | { | |
77fa9aee | 322 | UHCIQueue *queue, *nq; |
54f254f9 | 323 | |
77fa9aee | 324 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { |
66a08cbe | 325 | uhci_queue_free(queue, "cancel-all"); |
54f254f9 | 326 | } |
54f254f9 AL |
327 | } |
328 | ||
8c75a899 | 329 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) |
54f254f9 | 330 | { |
f8af1e88 | 331 | UHCIQueue *queue; |
ddf6583f | 332 | UHCIAsync *async; |
e8ee3c72 | 333 | |
f8af1e88 | 334 | QTAILQ_FOREACH(queue, &s->queues, next) { |
8c75a899 HG |
335 | QTAILQ_FOREACH(async, &queue->asyncs, next) { |
336 | if (async->td_addr == td_addr) { | |
337 | return async; | |
338 | } | |
f8af1e88 GH |
339 | } |
340 | } | |
f8af1e88 | 341 | return NULL; |
54f254f9 AL |
342 | } |
343 | ||
bb36d470 FB |
344 | static void uhci_update_irq(UHCIState *s) |
345 | { | |
346 | int level; | |
347 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
348 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
349 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
350 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
351 | (s->status & UHCI_STS_HSERR) || | |
352 | (s->status & UHCI_STS_HCPERR)) { | |
353 | level = 1; | |
354 | } else { | |
355 | level = 0; | |
356 | } | |
9e64f8a3 | 357 | pci_set_irq(&s->dev, level); |
bb36d470 FB |
358 | } |
359 | ||
537e572a | 360 | static void uhci_reset(DeviceState *dev) |
bb36d470 | 361 | { |
537e572a | 362 | PCIDevice *d = PCI_DEVICE(dev); |
49184b62 | 363 | UHCIState *s = UHCI(d); |
bb36d470 FB |
364 | uint8_t *pci_conf; |
365 | int i; | |
366 | UHCIPort *port; | |
367 | ||
50dcc0f8 | 368 | trace_usb_uhci_reset(); |
6f382b5e | 369 | |
bb36d470 FB |
370 | pci_conf = s->dev.config; |
371 | ||
372 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
373 | pci_conf[0x6b] = 0x00; | |
374 | s->cmd = 0; | |
ca5a21c4 | 375 | s->status = UHCI_STS_HCHALTED; |
bb36d470 FB |
376 | s->status2 = 0; |
377 | s->intr = 0; | |
378 | s->fl_base_addr = 0; | |
379 | s->sof_timing = 64; | |
54f254f9 | 380 | |
bb36d470 FB |
381 | for(i = 0; i < NB_PORTS; i++) { |
382 | port = &s->ports[i]; | |
383 | port->ctrl = 0x0080; | |
891fb2cd | 384 | if (port->port.dev && port->port.dev->attached) { |
d28f4e2d | 385 | usb_port_reset(&port->port); |
618c169b | 386 | } |
bb36d470 | 387 | } |
54f254f9 AL |
388 | |
389 | uhci_async_cancel_all(s); | |
9a16c595 | 390 | qemu_bh_cancel(s->bh); |
aba1f242 | 391 | uhci_update_irq(s); |
bb36d470 FB |
392 | } |
393 | ||
817afc61 JQ |
394 | static const VMStateDescription vmstate_uhci_port = { |
395 | .name = "uhci port", | |
396 | .version_id = 1, | |
397 | .minimum_version_id = 1, | |
6e3d652a | 398 | .fields = (VMStateField[]) { |
817afc61 JQ |
399 | VMSTATE_UINT16(ctrl, UHCIPort), |
400 | VMSTATE_END_OF_LIST() | |
401 | } | |
402 | }; | |
403 | ||
75f151cd GH |
404 | static int uhci_post_load(void *opaque, int version_id) |
405 | { | |
406 | UHCIState *s = opaque; | |
407 | ||
408 | if (version_id < 2) { | |
bc72ad67 | 409 | s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 410 | (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); |
75f151cd GH |
411 | } |
412 | return 0; | |
413 | } | |
414 | ||
817afc61 JQ |
415 | static const VMStateDescription vmstate_uhci = { |
416 | .name = "uhci", | |
ecfdc15f | 417 | .version_id = 3, |
817afc61 | 418 | .minimum_version_id = 1, |
75f151cd | 419 | .post_load = uhci_post_load, |
6e3d652a | 420 | .fields = (VMStateField[]) { |
817afc61 | 421 | VMSTATE_PCI_DEVICE(dev, UHCIState), |
d2164ad3 | 422 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), |
817afc61 JQ |
423 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, |
424 | vmstate_uhci_port, UHCIPort), | |
425 | VMSTATE_UINT16(cmd, UHCIState), | |
426 | VMSTATE_UINT16(status, UHCIState), | |
427 | VMSTATE_UINT16(intr, UHCIState), | |
428 | VMSTATE_UINT16(frnum, UHCIState), | |
429 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
430 | VMSTATE_UINT8(sof_timing, UHCIState), | |
431 | VMSTATE_UINT8(status2, UHCIState), | |
e720677e | 432 | VMSTATE_TIMER_PTR(frame_timer, UHCIState), |
6881dd5f | 433 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
ecfdc15f | 434 | VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), |
817afc61 JQ |
435 | VMSTATE_END_OF_LIST() |
436 | } | |
437 | }; | |
b9dc033c | 438 | |
89eb147c GH |
439 | static void uhci_port_write(void *opaque, hwaddr addr, |
440 | uint64_t val, unsigned size) | |
bb36d470 FB |
441 | { |
442 | UHCIState *s = opaque; | |
3b46e624 | 443 | |
50dcc0f8 | 444 | trace_usb_uhci_mmio_writew(addr, val); |
54f254f9 | 445 | |
bb36d470 FB |
446 | switch(addr) { |
447 | case 0x00: | |
448 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
449 | /* start frame processing */ | |
50dcc0f8 | 450 | trace_usb_uhci_schedule_start(); |
bc72ad67 | 451 | s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 452 | (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); |
bc72ad67 | 453 | timer_mod(s->frame_timer, s->expire_time); |
52328140 | 454 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 455 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 456 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
457 | } |
458 | if (val & UHCI_CMD_GRESET) { | |
459 | UHCIPort *port; | |
bb36d470 FB |
460 | int i; |
461 | ||
462 | /* send reset on the USB bus */ | |
463 | for(i = 0; i < NB_PORTS; i++) { | |
464 | port = &s->ports[i]; | |
d28f4e2d | 465 | usb_device_reset(port->port.dev); |
bb36d470 | 466 | } |
537e572a | 467 | uhci_reset(DEVICE(s)); |
bb36d470 FB |
468 | return; |
469 | } | |
5e9ab4c4 | 470 | if (val & UHCI_CMD_HCRESET) { |
537e572a | 471 | uhci_reset(DEVICE(s)); |
bb36d470 FB |
472 | return; |
473 | } | |
474 | s->cmd = val; | |
9f0f1a0c GH |
475 | if (val & UHCI_CMD_EGSM) { |
476 | if ((s->ports[0].ctrl & UHCI_PORT_RD) || | |
477 | (s->ports[1].ctrl & UHCI_PORT_RD)) { | |
478 | uhci_resume(s); | |
479 | } | |
480 | } | |
bb36d470 FB |
481 | break; |
482 | case 0x02: | |
483 | s->status &= ~val; | |
484 | /* XXX: the chip spec is not coherent, so we add a hidden | |
485 | register to distinguish between IOC and SPD */ | |
486 | if (val & UHCI_STS_USBINT) | |
487 | s->status2 = 0; | |
488 | uhci_update_irq(s); | |
489 | break; | |
490 | case 0x04: | |
491 | s->intr = val; | |
492 | uhci_update_irq(s); | |
493 | break; | |
494 | case 0x06: | |
495 | if (s->status & UHCI_STS_HCHALTED) | |
496 | s->frnum = val & 0x7ff; | |
497 | break; | |
89eb147c GH |
498 | case 0x08: |
499 | s->fl_base_addr &= 0xffff0000; | |
500 | s->fl_base_addr |= val & ~0xfff; | |
501 | break; | |
502 | case 0x0a: | |
503 | s->fl_base_addr &= 0x0000ffff; | |
504 | s->fl_base_addr |= (val << 16); | |
505 | break; | |
506 | case 0x0c: | |
507 | s->sof_timing = val & 0xff; | |
508 | break; | |
bb36d470 FB |
509 | case 0x10 ... 0x1f: |
510 | { | |
511 | UHCIPort *port; | |
512 | USBDevice *dev; | |
513 | int n; | |
514 | ||
515 | n = (addr >> 1) & 7; | |
516 | if (n >= NB_PORTS) | |
517 | return; | |
518 | port = &s->ports[n]; | |
a594cfbf | 519 | dev = port->port.dev; |
891fb2cd | 520 | if (dev && dev->attached) { |
bb36d470 | 521 | /* port reset */ |
5fafdf24 | 522 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 523 | !(port->ctrl & UHCI_PORT_RESET) ) { |
d28f4e2d | 524 | usb_device_reset(dev); |
bb36d470 FB |
525 | } |
526 | } | |
9159f679 | 527 | port->ctrl &= UHCI_PORT_READ_ONLY; |
1cbdde90 HG |
528 | /* enabled may only be set if a device is connected */ |
529 | if (!(port->ctrl & UHCI_PORT_CCS)) { | |
530 | val &= ~UHCI_PORT_EN; | |
531 | } | |
9159f679 | 532 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
bb36d470 | 533 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 534 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
535 | } |
536 | break; | |
537 | } | |
538 | } | |
539 | ||
89eb147c | 540 | static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) |
bb36d470 FB |
541 | { |
542 | UHCIState *s = opaque; | |
543 | uint32_t val; | |
544 | ||
bb36d470 FB |
545 | switch(addr) { |
546 | case 0x00: | |
547 | val = s->cmd; | |
548 | break; | |
549 | case 0x02: | |
550 | val = s->status; | |
551 | break; | |
552 | case 0x04: | |
553 | val = s->intr; | |
554 | break; | |
555 | case 0x06: | |
556 | val = s->frnum; | |
557 | break; | |
89eb147c GH |
558 | case 0x08: |
559 | val = s->fl_base_addr & 0xffff; | |
560 | break; | |
561 | case 0x0a: | |
562 | val = (s->fl_base_addr >> 16) & 0xffff; | |
563 | break; | |
564 | case 0x0c: | |
565 | val = s->sof_timing; | |
566 | break; | |
bb36d470 FB |
567 | case 0x10 ... 0x1f: |
568 | { | |
569 | UHCIPort *port; | |
570 | int n; | |
571 | n = (addr >> 1) & 7; | |
5fafdf24 | 572 | if (n >= NB_PORTS) |
bb36d470 FB |
573 | goto read_default; |
574 | port = &s->ports[n]; | |
575 | val = port->ctrl; | |
576 | } | |
577 | break; | |
578 | default: | |
579 | read_default: | |
580 | val = 0xff7f; /* disabled port */ | |
581 | break; | |
582 | } | |
54f254f9 | 583 | |
50dcc0f8 | 584 | trace_usb_uhci_mmio_readw(addr, val); |
54f254f9 | 585 | |
bb36d470 FB |
586 | return val; |
587 | } | |
588 | ||
96217e31 TS |
589 | /* signal resume if controller suspended */ |
590 | static void uhci_resume (void *opaque) | |
591 | { | |
592 | UHCIState *s = (UHCIState *)opaque; | |
593 | ||
594 | if (!s) | |
595 | return; | |
596 | ||
597 | if (s->cmd & UHCI_CMD_EGSM) { | |
598 | s->cmd |= UHCI_CMD_FGR; | |
599 | s->status |= UHCI_STS_RD; | |
600 | uhci_update_irq(s); | |
601 | } | |
602 | } | |
603 | ||
618c169b | 604 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
605 | { |
606 | UHCIState *s = port1->opaque; | |
607 | UHCIPort *port = &s->ports[port1->index]; | |
608 | ||
618c169b GH |
609 | /* set connect status */ |
610 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 611 | |
618c169b GH |
612 | /* update speed */ |
613 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
614 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 615 | } else { |
618c169b GH |
616 | port->ctrl &= ~UHCI_PORT_LSDA; |
617 | } | |
96217e31 | 618 | |
618c169b GH |
619 | uhci_resume(s); |
620 | } | |
96217e31 | 621 | |
618c169b GH |
622 | static void uhci_detach(USBPort *port1) |
623 | { | |
624 | UHCIState *s = port1->opaque; | |
625 | UHCIPort *port = &s->ports[port1->index]; | |
626 | ||
4706ab6c HG |
627 | uhci_async_cancel_device(s, port1->dev); |
628 | ||
618c169b GH |
629 | /* set connect status */ |
630 | if (port->ctrl & UHCI_PORT_CCS) { | |
631 | port->ctrl &= ~UHCI_PORT_CCS; | |
632 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 633 | } |
618c169b GH |
634 | /* disable port */ |
635 | if (port->ctrl & UHCI_PORT_EN) { | |
636 | port->ctrl &= ~UHCI_PORT_EN; | |
637 | port->ctrl |= UHCI_PORT_ENC; | |
638 | } | |
639 | ||
640 | uhci_resume(s); | |
bb36d470 FB |
641 | } |
642 | ||
4706ab6c HG |
643 | static void uhci_child_detach(USBPort *port1, USBDevice *child) |
644 | { | |
645 | UHCIState *s = port1->opaque; | |
646 | ||
647 | uhci_async_cancel_device(s, child); | |
648 | } | |
649 | ||
d47e59b8 | 650 | static void uhci_wakeup(USBPort *port1) |
9159f679 | 651 | { |
d47e59b8 HG |
652 | UHCIState *s = port1->opaque; |
653 | UHCIPort *port = &s->ports[port1->index]; | |
9159f679 GH |
654 | |
655 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
656 | port->ctrl |= UHCI_PORT_RD; | |
657 | uhci_resume(s); | |
658 | } | |
659 | } | |
660 | ||
461700c1 | 661 | static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) |
bb36d470 | 662 | { |
461700c1 GH |
663 | USBDevice *dev; |
664 | int i; | |
54f254f9 | 665 | |
461700c1 | 666 | for (i = 0; i < NB_PORTS; i++) { |
54f254f9 | 667 | UHCIPort *port = &s->ports[i]; |
461700c1 GH |
668 | if (!(port->ctrl & UHCI_PORT_EN)) { |
669 | continue; | |
670 | } | |
671 | dev = usb_find_device(&port->port, addr); | |
672 | if (dev != NULL) { | |
673 | return dev; | |
891fb2cd | 674 | } |
bb36d470 | 675 | } |
461700c1 | 676 | return NULL; |
bb36d470 FB |
677 | } |
678 | ||
963a68b5 HG |
679 | static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) |
680 | { | |
681 | pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); | |
682 | le32_to_cpus(&td->link); | |
683 | le32_to_cpus(&td->ctrl); | |
684 | le32_to_cpus(&td->token); | |
685 | le32_to_cpus(&td->buffer); | |
686 | } | |
687 | ||
faccca00 HG |
688 | static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, |
689 | int status, uint32_t *int_mask) | |
690 | { | |
691 | uint32_t queue_token = uhci_queue_token(td); | |
692 | int ret; | |
693 | ||
694 | switch (status) { | |
695 | case USB_RET_NAK: | |
696 | td->ctrl |= TD_CTRL_NAK; | |
697 | return TD_RESULT_NEXT_QH; | |
698 | ||
699 | case USB_RET_STALL: | |
700 | td->ctrl |= TD_CTRL_STALL; | |
701 | trace_usb_uhci_packet_complete_stall(queue_token, td_addr); | |
702 | ret = TD_RESULT_NEXT_QH; | |
703 | break; | |
704 | ||
705 | case USB_RET_BABBLE: | |
706 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
707 | /* frame interrupted */ | |
708 | trace_usb_uhci_packet_complete_babble(queue_token, td_addr); | |
709 | ret = TD_RESULT_STOP_FRAME; | |
710 | break; | |
711 | ||
712 | case USB_RET_IOERROR: | |
713 | case USB_RET_NODEV: | |
714 | default: | |
715 | td->ctrl |= TD_CTRL_TIMEOUT; | |
716 | td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); | |
717 | trace_usb_uhci_packet_complete_error(queue_token, td_addr); | |
718 | ret = TD_RESULT_NEXT_QH; | |
719 | break; | |
720 | } | |
721 | ||
722 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
723 | s->status |= UHCI_STS_USBERR; | |
724 | if (td->ctrl & TD_CTRL_IOC) { | |
725 | *int_mask |= 0x01; | |
726 | } | |
727 | uhci_update_irq(s); | |
728 | return ret; | |
729 | } | |
730 | ||
54f254f9 | 731 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 732 | { |
9a77a0f5 | 733 | int len = 0, max_len; |
bb36d470 | 734 | uint8_t pid; |
bb36d470 | 735 | |
54f254f9 AL |
736 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
737 | pid = td->token & 0xff; | |
738 | ||
54f254f9 AL |
739 | if (td->ctrl & TD_CTRL_IOS) |
740 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 741 | |
9a77a0f5 HG |
742 | if (async->packet.status != USB_RET_SUCCESS) { |
743 | return uhci_handle_td_error(s, td, async->td_addr, | |
744 | async->packet.status, int_mask); | |
faccca00 | 745 | } |
b9dc033c | 746 | |
9a77a0f5 | 747 | len = async->packet.actual_length; |
54f254f9 AL |
748 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
749 | ||
750 | /* The NAK bit may have been set by a previous frame, so clear it | |
751 | here. The docs are somewhat unclear, but win2k relies on this | |
752 | behavior. */ | |
753 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
754 | if (td->ctrl & TD_CTRL_IOC) |
755 | *int_mask |= 0x01; | |
54f254f9 AL |
756 | |
757 | if (pid == USB_TOKEN_IN) { | |
9822261c | 758 | pci_dma_write(&s->dev, td->buffer, async->buf, len); |
54f254f9 | 759 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { |
bb36d470 FB |
760 | *int_mask |= 0x02; |
761 | /* short packet: do not update QH */ | |
50dcc0f8 | 762 | trace_usb_uhci_packet_complete_shortxfer(async->queue->token, |
1f250cc7 | 763 | async->td_addr); |
60e1b2a6 | 764 | return TD_RESULT_NEXT_QH; |
bb36d470 | 765 | } |
54f254f9 AL |
766 | } |
767 | ||
768 | /* success */ | |
1f250cc7 HG |
769 | trace_usb_uhci_packet_complete_success(async->queue->token, |
770 | async->td_addr); | |
60e1b2a6 | 771 | return TD_RESULT_COMPLETE; |
bb36d470 FB |
772 | } |
773 | ||
66a08cbe | 774 | static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, |
a4f30cd7 | 775 | UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) |
54f254f9 | 776 | { |
9a77a0f5 | 777 | int ret, max_len; |
6ba43f1f | 778 | bool spd; |
a4f30cd7 | 779 | bool queuing = (q != NULL); |
11d15e40 | 780 | uint8_t pid = td->token & 0xff; |
5f77e06b GA |
781 | UHCIAsync *async; |
782 | ||
5f77e06b | 783 | async = uhci_async_find_td(s, td_addr); |
8c75a899 HG |
784 | if (async) { |
785 | if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { | |
786 | assert(q == NULL || q == async->queue); | |
787 | q = async->queue; | |
788 | } else { | |
789 | uhci_queue_free(async->queue, "guest re-used pending td"); | |
790 | async = NULL; | |
791 | } | |
792 | } | |
54f254f9 | 793 | |
66a08cbe HG |
794 | if (q == NULL) { |
795 | q = uhci_queue_find(s, td); | |
796 | if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { | |
797 | uhci_queue_free(q, "guest re-used qh"); | |
798 | q = NULL; | |
799 | } | |
800 | } | |
801 | ||
3905097e | 802 | if (q) { |
475443cf | 803 | q->valid = QH_VALID; |
3905097e HG |
804 | } |
805 | ||
54f254f9 | 806 | /* Is active ? */ |
883bca77 | 807 | if (!(td->ctrl & TD_CTRL_ACTIVE)) { |
420ca987 HG |
808 | if (async) { |
809 | /* Guest marked a pending td non-active, cancel the queue */ | |
810 | uhci_queue_free(async->queue, "pending td non-active"); | |
811 | } | |
883bca77 HG |
812 | /* |
813 | * ehci11d spec page 22: "Even if the Active bit in the TD is already | |
814 | * cleared when the TD is fetched ... an IOC interrupt is generated" | |
815 | */ | |
816 | if (td->ctrl & TD_CTRL_IOC) { | |
817 | *int_mask |= 0x01; | |
818 | } | |
60e1b2a6 | 819 | return TD_RESULT_NEXT_QH; |
883bca77 | 820 | } |
54f254f9 | 821 | |
f419a626 GH |
822 | switch (pid) { |
823 | case USB_TOKEN_OUT: | |
824 | case USB_TOKEN_SETUP: | |
825 | case USB_TOKEN_IN: | |
826 | break; | |
827 | default: | |
828 | /* invalid pid : frame interrupted */ | |
829 | s->status |= UHCI_STS_HCPERR; | |
830 | s->cmd &= ~UHCI_CMD_RS; | |
831 | uhci_update_irq(s); | |
832 | return TD_RESULT_STOP_FRAME; | |
833 | } | |
834 | ||
54f254f9 | 835 | if (async) { |
ee008ba6 GH |
836 | if (queuing) { |
837 | /* we are busy filling the queue, we are not prepared | |
838 | to consume completed packages then, just leave them | |
839 | in async state */ | |
840 | return TD_RESULT_ASYNC_CONT; | |
841 | } | |
8928c9c4 HG |
842 | if (!async->done) { |
843 | UHCI_TD last_td; | |
eae3eb3e | 844 | UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); |
8928c9c4 HG |
845 | /* |
846 | * While we are waiting for the current td to complete, the guest | |
847 | * may have added more tds to the queue. Note we re-read the td | |
848 | * rather then caching it, as we want to see guest made changes! | |
849 | */ | |
850 | uhci_read_td(s, &last_td, last->td_addr); | |
851 | uhci_queue_fill(async->queue, &last_td); | |
54f254f9 | 852 | |
8928c9c4 HG |
853 | return TD_RESULT_ASYNC_CONT; |
854 | } | |
f8af1e88 | 855 | uhci_async_unlink(async); |
54f254f9 AL |
856 | goto done; |
857 | } | |
858 | ||
88793816 HG |
859 | if (s->completions_only) { |
860 | return TD_RESULT_ASYNC_CONT; | |
861 | } | |
862 | ||
54f254f9 | 863 | /* Allocate new packet */ |
a4f30cd7 | 864 | if (q == NULL) { |
ff668537 LM |
865 | USBDevice *dev; |
866 | USBEndpoint *ep; | |
7f102ebe | 867 | |
ff668537 LM |
868 | dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
869 | if (dev == NULL) { | |
7f102ebe HG |
870 | return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, |
871 | int_mask); | |
872 | } | |
ff668537 | 873 | ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); |
66a08cbe | 874 | q = uhci_queue_new(s, qh_addr, td, ep); |
a4f30cd7 HG |
875 | } |
876 | async = uhci_async_alloc(q, td_addr); | |
54f254f9 | 877 | |
54f254f9 | 878 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
6ba43f1f | 879 | spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); |
8550a02d | 880 | usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, |
a6fb2ddb | 881 | (td->ctrl & TD_CTRL_IOC) != 0); |
9822261c HG |
882 | if (max_len <= sizeof(async->static_buf)) { |
883 | async->buf = async->static_buf; | |
884 | } else { | |
885 | async->buf = g_malloc(max_len); | |
886 | } | |
887 | usb_packet_addbuf(&async->packet, async->buf, max_len); | |
54f254f9 AL |
888 | |
889 | switch(pid) { | |
890 | case USB_TOKEN_OUT: | |
891 | case USB_TOKEN_SETUP: | |
9822261c | 892 | pci_dma_read(&s->dev, td->buffer, async->buf, max_len); |
9a77a0f5 HG |
893 | usb_handle_packet(q->ep->dev, &async->packet); |
894 | if (async->packet.status == USB_RET_SUCCESS) { | |
895 | async->packet.actual_length = max_len; | |
896 | } | |
54f254f9 AL |
897 | break; |
898 | ||
899 | case USB_TOKEN_IN: | |
9a77a0f5 | 900 | usb_handle_packet(q->ep->dev, &async->packet); |
54f254f9 AL |
901 | break; |
902 | ||
903 | default: | |
5f77e06b | 904 | abort(); /* Never to execute */ |
54f254f9 | 905 | } |
9a77a0f5 HG |
906 | |
907 | if (async->packet.status == USB_RET_ASYNC) { | |
f8af1e88 | 908 | uhci_async_link(async); |
a4f30cd7 | 909 | if (!queuing) { |
11d15e40 | 910 | uhci_queue_fill(q, td); |
a4f30cd7 | 911 | } |
4efe4ef3 | 912 | return TD_RESULT_ASYNC_START; |
54f254f9 AL |
913 | } |
914 | ||
54f254f9 | 915 | done: |
9a77a0f5 | 916 | ret = uhci_complete_td(s, td, async, int_mask); |
f8af1e88 | 917 | uhci_async_free(async); |
9a77a0f5 | 918 | return ret; |
54f254f9 AL |
919 | } |
920 | ||
d47e59b8 | 921 | static void uhci_async_complete(USBPort *port, USBPacket *packet) |
4d611c9a | 922 | { |
7b5a44c5 | 923 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
f8af1e88 | 924 | UHCIState *s = async->queue->uhci; |
54f254f9 | 925 | |
9a77a0f5 | 926 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
0cae7b1a HG |
927 | uhci_async_cancel(async); |
928 | return; | |
929 | } | |
930 | ||
5b352ed5 | 931 | async->done = 1; |
88793816 HG |
932 | /* Force processing of this packet *now*, needed for migration */ |
933 | s->completions_only = true; | |
934 | qemu_bh_schedule(s->bh); | |
54f254f9 AL |
935 | } |
936 | ||
937 | static int is_valid(uint32_t link) | |
938 | { | |
939 | return (link & 1) == 0; | |
940 | } | |
941 | ||
942 | static int is_qh(uint32_t link) | |
943 | { | |
944 | return (link & 2) != 0; | |
945 | } | |
946 | ||
947 | static int depth_first(uint32_t link) | |
948 | { | |
949 | return (link & 4) != 0; | |
950 | } | |
951 | ||
952 | /* QH DB used for detecting QH loops */ | |
953 | #define UHCI_MAX_QUEUES 128 | |
954 | typedef struct { | |
955 | uint32_t addr[UHCI_MAX_QUEUES]; | |
956 | int count; | |
957 | } QhDb; | |
958 | ||
959 | static void qhdb_reset(QhDb *db) | |
960 | { | |
961 | db->count = 0; | |
962 | } | |
963 | ||
964 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
965 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
966 | { | |
967 | int i; | |
968 | for (i = 0; i < db->count; i++) | |
969 | if (db->addr[i] == addr) | |
970 | return 1; | |
971 | ||
972 | if (db->count >= UHCI_MAX_QUEUES) | |
973 | return 1; | |
974 | ||
975 | db->addr[db->count++] = addr; | |
976 | return 0; | |
977 | } | |
978 | ||
11d15e40 | 979 | static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) |
5a248289 GH |
980 | { |
981 | uint32_t int_mask = 0; | |
982 | uint32_t plink = td->link; | |
5a248289 GH |
983 | UHCI_TD ptd; |
984 | int ret; | |
985 | ||
6ba43f1f | 986 | while (is_valid(plink)) { |
a4f30cd7 | 987 | uhci_read_td(q->uhci, &ptd, plink); |
5a248289 GH |
988 | if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { |
989 | break; | |
990 | } | |
a4f30cd7 | 991 | if (uhci_queue_token(&ptd) != q->token) { |
5a248289 GH |
992 | break; |
993 | } | |
50dcc0f8 | 994 | trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); |
66a08cbe | 995 | ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); |
52b0fecd GH |
996 | if (ret == TD_RESULT_ASYNC_CONT) { |
997 | break; | |
998 | } | |
4efe4ef3 | 999 | assert(ret == TD_RESULT_ASYNC_START); |
5a248289 GH |
1000 | assert(int_mask == 0); |
1001 | plink = ptd.link; | |
1002 | } | |
11d15e40 | 1003 | usb_device_flush_ep_queue(q->ep->dev, q->ep); |
5a248289 GH |
1004 | } |
1005 | ||
54f254f9 AL |
1006 | static void uhci_process_frame(UHCIState *s) |
1007 | { | |
1008 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
4aed20e2 | 1009 | uint32_t curr_qh, td_count = 0; |
54f254f9 | 1010 | int cnt, ret; |
4d611c9a | 1011 | UHCI_TD td; |
54f254f9 AL |
1012 | UHCI_QH qh; |
1013 | QhDb qhdb; | |
4d611c9a | 1014 | |
54f254f9 AL |
1015 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
1016 | ||
9fe2fd67 | 1017 | pci_dma_read(&s->dev, frame_addr, &link, 4); |
54f254f9 | 1018 | le32_to_cpus(&link); |
b9dc033c | 1019 | |
54f254f9 AL |
1020 | int_mask = 0; |
1021 | curr_qh = 0; | |
1022 | ||
1023 | qhdb_reset(&qhdb); | |
1024 | ||
1025 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
88793816 | 1026 | if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { |
4aed20e2 GH |
1027 | /* We've reached the usb 1.1 bandwidth, which is |
1028 | 1280 bytes/frame, stop processing */ | |
1029 | trace_usb_uhci_frame_stop_bandwidth(); | |
1030 | break; | |
1031 | } | |
54f254f9 AL |
1032 | if (is_qh(link)) { |
1033 | /* QH */ | |
50dcc0f8 | 1034 | trace_usb_uhci_qh_load(link & ~0xf); |
54f254f9 AL |
1035 | |
1036 | if (qhdb_insert(&qhdb, link)) { | |
1037 | /* | |
1038 | * We're going in circles. Which is not a bug because | |
3200d108 GH |
1039 | * HCD is allowed to do that as part of the BW management. |
1040 | * | |
4aed20e2 GH |
1041 | * Stop processing here if no transaction has been done |
1042 | * since we've been here last time. | |
54f254f9 | 1043 | */ |
3200d108 | 1044 | if (td_count == 0) { |
50dcc0f8 | 1045 | trace_usb_uhci_frame_loop_stop_idle(); |
3200d108 | 1046 | break; |
3200d108 | 1047 | } else { |
50dcc0f8 | 1048 | trace_usb_uhci_frame_loop_continue(); |
3200d108 GH |
1049 | td_count = 0; |
1050 | qhdb_reset(&qhdb); | |
1051 | qhdb_insert(&qhdb, link); | |
1052 | } | |
54f254f9 AL |
1053 | } |
1054 | ||
9fe2fd67 | 1055 | pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
54f254f9 AL |
1056 | le32_to_cpus(&qh.link); |
1057 | le32_to_cpus(&qh.el_link); | |
1058 | ||
54f254f9 AL |
1059 | if (!is_valid(qh.el_link)) { |
1060 | /* QH w/o elements */ | |
1061 | curr_qh = 0; | |
1062 | link = qh.link; | |
1063 | } else { | |
1064 | /* QH with elements */ | |
72e21db7 PB |
1065 | curr_qh = link; |
1066 | link = qh.el_link; | |
54f254f9 AL |
1067 | } |
1068 | continue; | |
1069 | } | |
1070 | ||
1071 | /* TD */ | |
963a68b5 | 1072 | uhci_read_td(s, &td, link); |
50dcc0f8 | 1073 | trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); |
54f254f9 AL |
1074 | |
1075 | old_td_ctrl = td.ctrl; | |
66a08cbe | 1076 | ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); |
b9dc033c | 1077 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 1078 | /* update the status bits of the TD */ |
b9dc033c | 1079 | val = cpu_to_le32(td.ctrl); |
9fe2fd67 | 1080 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
b9dc033c | 1081 | } |
54f254f9 | 1082 | |
971a5a40 | 1083 | switch (ret) { |
60e1b2a6 | 1084 | case TD_RESULT_STOP_FRAME: /* interrupted frame */ |
971a5a40 | 1085 | goto out; |
b9dc033c | 1086 | |
60e1b2a6 | 1087 | case TD_RESULT_NEXT_QH: |
4efe4ef3 | 1088 | case TD_RESULT_ASYNC_CONT: |
50dcc0f8 | 1089 | trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); |
54f254f9 AL |
1090 | link = curr_qh ? qh.link : td.link; |
1091 | continue; | |
54f254f9 | 1092 | |
4efe4ef3 | 1093 | case TD_RESULT_ASYNC_START: |
50dcc0f8 | 1094 | trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); |
971a5a40 GH |
1095 | link = curr_qh ? qh.link : td.link; |
1096 | continue; | |
54f254f9 | 1097 | |
60e1b2a6 | 1098 | case TD_RESULT_COMPLETE: |
50dcc0f8 | 1099 | trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); |
971a5a40 GH |
1100 | link = td.link; |
1101 | td_count++; | |
4aed20e2 | 1102 | s->frame_bytes += (td.ctrl & 0x7ff) + 1; |
54f254f9 | 1103 | |
971a5a40 GH |
1104 | if (curr_qh) { |
1105 | /* update QH element link */ | |
1106 | qh.el_link = link; | |
1107 | val = cpu_to_le32(qh.el_link); | |
1108 | pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); | |
54f254f9 | 1109 | |
971a5a40 GH |
1110 | if (!depth_first(link)) { |
1111 | /* done with this QH */ | |
971a5a40 GH |
1112 | curr_qh = 0; |
1113 | link = qh.link; | |
1114 | } | |
54f254f9 | 1115 | } |
971a5a40 GH |
1116 | break; |
1117 | ||
1118 | default: | |
1119 | assert(!"unknown return code"); | |
4d611c9a | 1120 | } |
54f254f9 AL |
1121 | |
1122 | /* go to the next entry */ | |
4d611c9a | 1123 | } |
54f254f9 | 1124 | |
971a5a40 | 1125 | out: |
8e65b7c0 | 1126 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1127 | } |
1128 | ||
9a16c595 GH |
1129 | static void uhci_bh(void *opaque) |
1130 | { | |
1131 | UHCIState *s = opaque; | |
1132 | uhci_process_frame(s); | |
1133 | } | |
1134 | ||
bb36d470 FB |
1135 | static void uhci_frame_timer(void *opaque) |
1136 | { | |
1137 | UHCIState *s = opaque; | |
f8f48b69 HG |
1138 | uint64_t t_now, t_last_run; |
1139 | int i, frames; | |
73bcb24d | 1140 | const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; |
8e65b7c0 | 1141 | |
88793816 | 1142 | s->completions_only = false; |
9a16c595 | 1143 | qemu_bh_cancel(s->bh); |
bb36d470 FB |
1144 | |
1145 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1146 | /* Full stop */ |
50dcc0f8 | 1147 | trace_usb_uhci_schedule_stop(); |
bc72ad67 | 1148 | timer_del(s->frame_timer); |
d9a528db | 1149 | uhci_async_cancel_all(s); |
52328140 FB |
1150 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1151 | s->status |= UHCI_STS_HCHALTED; | |
bb36d470 FB |
1152 | return; |
1153 | } | |
54f254f9 | 1154 | |
f8f48b69 HG |
1155 | /* We still store expire_time in our state, for migration */ |
1156 | t_last_run = s->expire_time - frame_t; | |
bc72ad67 | 1157 | t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
54f254f9 | 1158 | |
f8f48b69 HG |
1159 | /* Process up to MAX_FRAMES_PER_TICK frames */ |
1160 | frames = (t_now - t_last_run) / frame_t; | |
9fdf7027 HG |
1161 | if (frames > s->maxframes) { |
1162 | int skipped = frames - s->maxframes; | |
1163 | s->expire_time += skipped * frame_t; | |
1164 | s->frnum = (s->frnum + skipped) & 0x7ff; | |
1165 | frames -= skipped; | |
1166 | } | |
f8f48b69 HG |
1167 | if (frames > MAX_FRAMES_PER_TICK) { |
1168 | frames = MAX_FRAMES_PER_TICK; | |
1169 | } | |
b9dc033c | 1170 | |
f8f48b69 HG |
1171 | for (i = 0; i < frames; i++) { |
1172 | s->frame_bytes = 0; | |
1173 | trace_usb_uhci_frame_start(s->frnum); | |
1174 | uhci_async_validate_begin(s); | |
1175 | uhci_process_frame(s); | |
1176 | uhci_async_validate_end(s); | |
1177 | /* The spec says frnum is the frame currently being processed, and | |
1178 | * the guest must look at frnum - 1 on interrupt, so inc frnum now */ | |
1179 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1180 | s->expire_time += frame_t; | |
1181 | } | |
719c130d | 1182 | |
f8f48b69 | 1183 | /* Complete the previous frame(s) */ |
719c130d HG |
1184 | if (s->pending_int_mask) { |
1185 | s->status2 |= s->pending_int_mask; | |
1186 | s->status |= UHCI_STS_USBINT; | |
1187 | uhci_update_irq(s); | |
1188 | } | |
1189 | s->pending_int_mask = 0; | |
1190 | ||
bc72ad67 | 1191 | timer_mod(s->frame_timer, t_now + frame_t); |
bb36d470 FB |
1192 | } |
1193 | ||
a03f66e4 | 1194 | static const MemoryRegionOps uhci_ioport_ops = { |
89eb147c GH |
1195 | .read = uhci_port_read, |
1196 | .write = uhci_port_write, | |
1197 | .valid.min_access_size = 1, | |
1198 | .valid.max_access_size = 4, | |
1199 | .impl.min_access_size = 2, | |
1200 | .impl.max_access_size = 2, | |
1201 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a03f66e4 | 1202 | }; |
bb36d470 | 1203 | |
0d86d2be GH |
1204 | static USBPortOps uhci_port_ops = { |
1205 | .attach = uhci_attach, | |
618c169b | 1206 | .detach = uhci_detach, |
4706ab6c | 1207 | .child_detach = uhci_child_detach, |
9159f679 | 1208 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1209 | .complete = uhci_async_complete, |
0d86d2be GH |
1210 | }; |
1211 | ||
07771f6f | 1212 | static USBBusOps uhci_bus_ops = { |
07771f6f GH |
1213 | }; |
1214 | ||
63216dc7 | 1215 | static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) |
bb36d470 | 1216 | { |
f4bbaaf5 | 1217 | Error *err = NULL; |
973002c1 | 1218 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
8f3f90b0 | 1219 | UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); |
49184b62 | 1220 | UHCIState *s = UHCI(dev); |
6cf9b6f1 | 1221 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1222 | int i; |
1223 | ||
db579e9e | 1224 | pci_conf[PCI_CLASS_PROG] = 0x00; |
db579e9e | 1225 | /* TODO: reset value should be 0. */ |
e59d33a7 | 1226 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1227 | |
9e64f8a3 | 1228 | pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); |
973002c1 | 1229 | |
35e4977f HG |
1230 | if (s->masterbus) { |
1231 | USBPort *ports[NB_PORTS]; | |
1232 | for(i = 0; i < NB_PORTS; i++) { | |
1233 | ports[i] = &s->ports[i].port; | |
1234 | } | |
f4bbaaf5 MA |
1235 | usb_register_companion(s->masterbus, ports, NB_PORTS, |
1236 | s->firstport, s, &uhci_port_ops, | |
1237 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, | |
1238 | &err); | |
1239 | if (err) { | |
63216dc7 MA |
1240 | error_propagate(errp, err); |
1241 | return; | |
35e4977f HG |
1242 | } |
1243 | } else { | |
c889b3a5 | 1244 | usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); |
35e4977f HG |
1245 | for (i = 0; i < NB_PORTS; i++) { |
1246 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1247 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1248 | } | |
bb36d470 | 1249 | } |
9a16c595 | 1250 | s->bh = qemu_bh_new(uhci_bh, s); |
bc72ad67 | 1251 | s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); |
64e58fe5 | 1252 | s->num_ports_vmstate = NB_PORTS; |
f8af1e88 | 1253 | QTAILQ_INIT(&s->queues); |
bb36d470 | 1254 | |
22fc860b PB |
1255 | memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, |
1256 | "uhci", 0x20); | |
1257 | ||
38ca0f6d PB |
1258 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1259 | to rely on this. */ | |
e824b2cc | 1260 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
bb36d470 | 1261 | } |
afcc3cdf | 1262 | |
63216dc7 | 1263 | static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) |
30235a54 | 1264 | { |
49184b62 | 1265 | UHCIState *s = UHCI(dev); |
30235a54 HC |
1266 | uint8_t *pci_conf = s->dev.config; |
1267 | ||
30235a54 HC |
1268 | /* USB misc control 1/2 */ |
1269 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1270 | /* PM capability */ | |
1271 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1272 | /* USB legacy support */ | |
1273 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1274 | ||
63216dc7 | 1275 | usb_uhci_common_realize(dev, errp); |
30235a54 HC |
1276 | } |
1277 | ||
3a3464b0 GA |
1278 | static void usb_uhci_exit(PCIDevice *dev) |
1279 | { | |
49184b62 | 1280 | UHCIState *s = UHCI(dev); |
3a3464b0 | 1281 | |
d733f74c GA |
1282 | trace_usb_uhci_exit(); |
1283 | ||
3a3464b0 GA |
1284 | if (s->frame_timer) { |
1285 | timer_del(s->frame_timer); | |
1286 | timer_free(s->frame_timer); | |
1287 | s->frame_timer = NULL; | |
1288 | } | |
1289 | ||
1290 | if (s->bh) { | |
1291 | qemu_bh_delete(s->bh); | |
1292 | } | |
1293 | ||
1294 | uhci_async_cancel_all(s); | |
1295 | ||
1296 | if (!s->masterbus) { | |
1297 | usb_bus_release(&s->bus); | |
1298 | } | |
1299 | } | |
1300 | ||
638ca939 | 1301 | static Property uhci_properties_companion[] = { |
1b5a7570 GH |
1302 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), |
1303 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
40141d12 | 1304 | DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), |
9fdf7027 | 1305 | DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), |
1b5a7570 GH |
1306 | DEFINE_PROP_END_OF_LIST(), |
1307 | }; | |
638ca939 GH |
1308 | static Property uhci_properties_standalone[] = { |
1309 | DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), | |
1310 | DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), | |
1311 | DEFINE_PROP_END_OF_LIST(), | |
1312 | }; | |
1b5a7570 | 1313 | |
2c2e8525 | 1314 | static void uhci_class_init(ObjectClass *klass, void *data) |
40021f08 | 1315 | { |
39bffca2 | 1316 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 1317 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
49184b62 GA |
1318 | |
1319 | k->class_id = PCI_CLASS_SERIAL_USB; | |
1320 | dc->vmsd = &vmstate_uhci; | |
1321 | dc->reset = uhci_reset; | |
1322 | set_bit(DEVICE_CATEGORY_USB, dc->categories); | |
1323 | } | |
1324 | ||
1325 | static const TypeInfo uhci_pci_type_info = { | |
1326 | .name = TYPE_UHCI, | |
1327 | .parent = TYPE_PCI_DEVICE, | |
1328 | .instance_size = sizeof(UHCIState), | |
1329 | .class_size = sizeof(UHCIPCIDeviceClass), | |
1330 | .abstract = true, | |
1331 | .class_init = uhci_class_init, | |
fd3b02c8 EH |
1332 | .interfaces = (InterfaceInfo[]) { |
1333 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1334 | { }, | |
1335 | }, | |
49184b62 GA |
1336 | }; |
1337 | ||
1338 | static void uhci_data_class_init(ObjectClass *klass, void *data) | |
1339 | { | |
1340 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1341 | DeviceClass *dc = DEVICE_CLASS(klass); | |
8f3f90b0 | 1342 | UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); |
2c2e8525 GH |
1343 | UHCIInfo *info = data; |
1344 | ||
63216dc7 | 1345 | k->realize = info->realize ? info->realize : usb_uhci_common_realize; |
3a3464b0 | 1346 | k->exit = info->unplug ? usb_uhci_exit : NULL; |
2c2e8525 GH |
1347 | k->vendor_id = info->vendor_id; |
1348 | k->device_id = info->device_id; | |
1349 | k->revision = info->revision; | |
638ca939 GH |
1350 | if (!info->unplug) { |
1351 | /* uhci controllers in companion setups can't be hotplugged */ | |
1352 | dc->hotpluggable = false; | |
4f67d30b | 1353 | device_class_set_props(dc, uhci_properties_companion); |
638ca939 | 1354 | } else { |
4f67d30b | 1355 | device_class_set_props(dc, uhci_properties_standalone); |
638ca939 | 1356 | } |
8f3f90b0 | 1357 | u->info = *info; |
40021f08 AL |
1358 | } |
1359 | ||
2c2e8525 GH |
1360 | static UHCIInfo uhci_info[] = { |
1361 | { | |
1362 | .name = "piix3-usb-uhci", | |
1363 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1364 | .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, | |
1365 | .revision = 0x01, | |
8f3f90b0 | 1366 | .irq_pin = 3, |
2c2e8525 GH |
1367 | .unplug = true, |
1368 | },{ | |
1369 | .name = "piix4-usb-uhci", | |
1370 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1371 | .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, | |
1372 | .revision = 0x01, | |
8f3f90b0 | 1373 | .irq_pin = 3, |
2c2e8525 GH |
1374 | .unplug = true, |
1375 | },{ | |
1376 | .name = "vt82c686b-usb-uhci", | |
1377 | .vendor_id = PCI_VENDOR_ID_VIA, | |
1378 | .device_id = PCI_DEVICE_ID_VIA_UHCI, | |
1379 | .revision = 0x01, | |
8f3f90b0 | 1380 | .irq_pin = 3, |
63216dc7 | 1381 | .realize = usb_uhci_vt82c686b_realize, |
2c2e8525 GH |
1382 | .unplug = true, |
1383 | },{ | |
74625ea2 | 1384 | .name = "ich9-usb-uhci1", /* 00:1d.0 */ |
2c2e8525 GH |
1385 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1386 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, | |
1387 | .revision = 0x03, | |
8f3f90b0 | 1388 | .irq_pin = 0, |
2c2e8525 GH |
1389 | .unplug = false, |
1390 | },{ | |
74625ea2 | 1391 | .name = "ich9-usb-uhci2", /* 00:1d.1 */ |
2c2e8525 GH |
1392 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1393 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, | |
1394 | .revision = 0x03, | |
8f3f90b0 | 1395 | .irq_pin = 1, |
2c2e8525 GH |
1396 | .unplug = false, |
1397 | },{ | |
74625ea2 | 1398 | .name = "ich9-usb-uhci3", /* 00:1d.2 */ |
2c2e8525 GH |
1399 | .vendor_id = PCI_VENDOR_ID_INTEL, |
1400 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, | |
1401 | .revision = 0x03, | |
8f3f90b0 | 1402 | .irq_pin = 2, |
2c2e8525 | 1403 | .unplug = false, |
74625ea2 GH |
1404 | },{ |
1405 | .name = "ich9-usb-uhci4", /* 00:1a.0 */ | |
1406 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1407 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, | |
1408 | .revision = 0x03, | |
1409 | .irq_pin = 0, | |
1410 | .unplug = false, | |
1411 | },{ | |
1412 | .name = "ich9-usb-uhci5", /* 00:1a.1 */ | |
1413 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1414 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, | |
1415 | .revision = 0x03, | |
1416 | .irq_pin = 1, | |
1417 | .unplug = false, | |
1418 | },{ | |
1419 | .name = "ich9-usb-uhci6", /* 00:1a.2 */ | |
1420 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1421 | .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, | |
1422 | .revision = 0x03, | |
1423 | .irq_pin = 2, | |
1424 | .unplug = false, | |
2c2e8525 | 1425 | } |
6cf9b6f1 | 1426 | }; |
afcc3cdf | 1427 | |
83f7d43a | 1428 | static void uhci_register_types(void) |
6cf9b6f1 | 1429 | { |
2c2e8525 | 1430 | TypeInfo uhci_type_info = { |
49184b62 GA |
1431 | .parent = TYPE_UHCI, |
1432 | .class_init = uhci_data_class_init, | |
2c2e8525 GH |
1433 | }; |
1434 | int i; | |
1435 | ||
49184b62 GA |
1436 | type_register_static(&uhci_pci_type_info); |
1437 | ||
2c2e8525 GH |
1438 | for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { |
1439 | uhci_type_info.name = uhci_info[i].name; | |
1440 | uhci_type_info.class_data = uhci_info + i; | |
1441 | type_register(&uhci_type_info); | |
1442 | } | |
6cf9b6f1 | 1443 | } |
83f7d43a AF |
1444 | |
1445 | type_init(uhci_register_types) |