]> git.ipfire.org Git - thirdparty/qemu.git/blame - hw/virtio/virtio-pci.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
virtio: Add shared memory capability
[thirdparty/qemu.git] / hw / virtio / virtio-pci.c
CommitLineData
53c25cea
PB		 1/*
2 * Virtio PCI Bindings
3 *
4 * Copyright IBM, Corp. 2007
5 * Copyright (c) 2009 CodeSourcery
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 * Paul Brook <paul@codesourcery.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
6b620ca3
PB		 14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
53c25cea
PB		 16 */
17
9b8bfe21 18#include "qemu/osdep.h"
53c25cea 19
062c08d1 20#include "exec/memop.h"
cbbe4f50 21#include "standard-headers/linux/virtio_pci.h"
22733245 22#include "standard-headers/linux/virtio_ids.h"
1436f32a 23#include "hw/boards.h"
0d09e41a 24#include "hw/virtio/virtio.h"
ca77ee28 25#include "migration/qemu-file-types.h"
83c9f4ca 26#include "hw/pci/pci.h"
b0e5196a 27#include "hw/pci/pci_bus.h"
a27bd6c7 28#include "hw/qdev-properties.h"
da34e65c 29#include "qapi/error.h"
1de7afc9 30#include "qemu/error-report.h"
a8218588 31#include "qemu/log.h"
0b8fa32f 32#include "qemu/module.h"
83c9f4ca
PB		 33#include "hw/pci/msi.h"
34#include "hw/pci/msix.h"
35#include "hw/loader.h"
9c17d615 36#include "sysemu/kvm.h"
e1b1f534 37#include "hw/virtio/virtio-pci.h"
1de7afc9 38#include "qemu/range.h"
0d09e41a 39#include "hw/virtio/virtio-bus.h"
24a6e7f4 40#include "qapi/visitor.h"
3909c079 41#include "sysemu/replay.h"
31cc62bb 42#include "trace.h"
53c25cea 43
cbbe4f50 44#define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev))
aba800a3 45
c17bef33
MT		 46#undef VIRTIO_PCI_CONFIG
47
aba800a3
MT		 48/* The remaining space is defined by each driver as the per-driver
49 * configuration space */
cbbe4f50 50#define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev))
53c25cea 51
ac7af112
AF		 52static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
53 VirtIOPCIProxy *dev);
75fd6f13 54static void virtio_pci_reset(DeviceState *qdev);
d51fcfac 55
53c25cea 56/* virtio device */
d2a0ccc6
MT		 57/* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */
58static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d)
59{
60 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
61}
53c25cea 62
d2a0ccc6
MT		 63/* DeviceState to VirtIOPCIProxy. Note: used on datapath,
64 * be careful and test performance if you change this.
65 */
66static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d)
53c25cea 67{
d2a0ccc6
MT		 68 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
69}
70
71static void virtio_pci_notify(DeviceState *d, uint16_t vector)
72{
73 VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d);
a3fc66d9 74
15377f6e
AO		 75 if (msix_enabled(&proxy->pci_dev)) {
76 if (vector != VIRTIO_NO_VECTOR) {
77 msix_notify(&proxy->pci_dev, vector);
78 }
79 } else {
a3fc66d9 80 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
d73415a3 81 pci_set_irq(&proxy->pci_dev, qatomic_read(&vdev->isr) & 1);
a3fc66d9 82 }
53c25cea
PB		 83}
84
d2a0ccc6 85static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
ff24bd58 86{
d2a0ccc6 87 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 88 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
89
ff24bd58
MT		 90 pci_device_save(&proxy->pci_dev, f);
91 msix_save(&proxy->pci_dev, f);
92 if (msix_present(&proxy->pci_dev))
a3fc66d9 93 qemu_put_be16(f, vdev->config_vector);
ff24bd58
MT		 94}
95
b81b948e
DDAG		 96static const VMStateDescription vmstate_virtio_pci_modern_queue_state = {
97 .name = "virtio_pci/modern_queue_state",
98 .version_id = 1,
99 .minimum_version_id = 1,
100 .fields = (VMStateField[]) {
101 VMSTATE_UINT16(num, VirtIOPCIQueue),
102 VMSTATE_UNUSED(1), /* enabled was stored as be16 */
103 VMSTATE_BOOL(enabled, VirtIOPCIQueue),
104 VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2),
105 VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2),
106 VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2),
107 VMSTATE_END_OF_LIST()
a6df8adf 108 }
a6df8adf
JW		 109};
110
111static bool virtio_pci_modern_state_needed(void *opaque)
112{
113 VirtIOPCIProxy *proxy = opaque;
114
9a4c0e22 115 return virtio_pci_modern(proxy);
a6df8adf
JW		 116}
117
b81b948e 118static const VMStateDescription vmstate_virtio_pci_modern_state_sub = {
a6df8adf
JW		 119 .name = "virtio_pci/modern_state",
120 .version_id = 1,
121 .minimum_version_id = 1,
122 .needed = &virtio_pci_modern_state_needed,
123 .fields = (VMStateField[]) {
b81b948e
DDAG		 124 VMSTATE_UINT32(dfselect, VirtIOPCIProxy),
125 VMSTATE_UINT32(gfselect, VirtIOPCIProxy),
126 VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2),
127 VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0,
128 vmstate_virtio_pci_modern_queue_state,
129 VirtIOPCIQueue),
a6df8adf
JW		 130 VMSTATE_END_OF_LIST()
131 }
132};
133
134static const VMStateDescription vmstate_virtio_pci = {
135 .name = "virtio_pci",
136 .version_id = 1,
137 .minimum_version_id = 1,
a6df8adf
JW		 138 .fields = (VMStateField[]) {
139 VMSTATE_END_OF_LIST()
140 },
141 .subsections = (const VMStateDescription*[]) {
b81b948e 142 &vmstate_virtio_pci_modern_state_sub,
a6df8adf
JW		 143 NULL
144 }
145};
146
b81b948e
DDAG		 147static bool virtio_pci_has_extra_state(DeviceState *d)
148{
149 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
150
151 return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
152}
153
a6df8adf
JW		 154static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
155{
156 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
157
158 vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL);
159}
160
161static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f)
162{
163 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
164
165 return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1);
166}
167
d2a0ccc6 168static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 169{
d2a0ccc6 170 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 171 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
172
ff24bd58 173 if (msix_present(&proxy->pci_dev))
a3fc66d9 174 qemu_put_be16(f, virtio_queue_vector(vdev, n));
ff24bd58
MT		 175}
176
d2a0ccc6 177static int virtio_pci_load_config(DeviceState *d, QEMUFile *f)
ff24bd58 178{
d2a0ccc6 179 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 180 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
15377f6e 181 uint16_t vector;
a3fc66d9 182
ff24bd58
MT		 183 int ret;
184 ret = pci_device_load(&proxy->pci_dev, f);
e6da7680 185 if (ret) {
ff24bd58 186 return ret;
e6da7680 187 }
3cac001e 188 msix_unuse_all_vectors(&proxy->pci_dev);
ff24bd58 189 msix_load(&proxy->pci_dev, f);
e6da7680 190 if (msix_present(&proxy->pci_dev)) {
15377f6e
AO		 191 qemu_get_be16s(f, &vector);
192
193 if (vector != VIRTIO_NO_VECTOR && vector >= proxy->nvectors) {
194 return -EINVAL;
195 }
e6da7680 196 } else {
15377f6e 197 vector = VIRTIO_NO_VECTOR;
e6da7680 198 }
15377f6e
AO		 199 vdev->config_vector = vector;
200 if (vector != VIRTIO_NO_VECTOR) {
201 msix_vector_use(&proxy->pci_dev, vector);
e6da7680 202 }
ff24bd58
MT		 203 return 0;
204}
205
d2a0ccc6 206static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 207{
d2a0ccc6 208 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 209 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
210
ff24bd58 211 uint16_t vector;
e6da7680
MT		 212 if (msix_present(&proxy->pci_dev)) {
213 qemu_get_be16s(f, &vector);
15377f6e
AO		 214 if (vector != VIRTIO_NO_VECTOR && vector >= proxy->nvectors) {
215 return -EINVAL;
216 }
e6da7680
MT		 217 } else {
218 vector = VIRTIO_NO_VECTOR;
219 }
a3fc66d9 220 virtio_queue_set_vector(vdev, n, vector);
e6da7680 221 if (vector != VIRTIO_NO_VECTOR) {
15377f6e 222 msix_vector_use(&proxy->pci_dev, vector);
e6da7680 223 }
a6df8adf 224
ff24bd58
MT		 225 return 0;
226}
227
22733245
LM		 228typedef struct VirtIOPCIIDInfo {
229 /* virtio id */
230 uint16_t vdev_id;
231 /* pci device id for the transitional device */
232 uint16_t trans_devid;
233 uint16_t class_id;
234} VirtIOPCIIDInfo;
235
236static const VirtIOPCIIDInfo virtio_pci_id_info[] = {
237 {
238 .vdev_id = VIRTIO_ID_CRYPTO,
239 .class_id = PCI_CLASS_OTHERS,
240 }, {
241 .vdev_id = VIRTIO_ID_FS,
242 .class_id = PCI_CLASS_STORAGE_OTHER,
243 }, {
244 .vdev_id = VIRTIO_ID_NET,
245 .trans_devid = PCI_DEVICE_ID_VIRTIO_NET,
246 .class_id = PCI_CLASS_NETWORK_ETHERNET,
247 }, {
248 .vdev_id = VIRTIO_ID_BLOCK,
249 .trans_devid = PCI_DEVICE_ID_VIRTIO_BLOCK,
250 .class_id = PCI_CLASS_STORAGE_SCSI,
251 }, {
252 .vdev_id = VIRTIO_ID_CONSOLE,
253 .trans_devid = PCI_DEVICE_ID_VIRTIO_CONSOLE,
254 .class_id = PCI_CLASS_COMMUNICATION_OTHER,
255 }, {
256 .vdev_id = VIRTIO_ID_SCSI,
257 .trans_devid = PCI_DEVICE_ID_VIRTIO_SCSI,
258 .class_id = PCI_CLASS_STORAGE_SCSI
259 }, {
260 .vdev_id = VIRTIO_ID_9P,
261 .trans_devid = PCI_DEVICE_ID_VIRTIO_9P,
262 .class_id = PCI_BASE_CLASS_NETWORK,
263 }, {
264 .vdev_id = VIRTIO_ID_BALLOON,
265 .trans_devid = PCI_DEVICE_ID_VIRTIO_BALLOON,
266 .class_id = PCI_CLASS_OTHERS,
267 }, {
268 .vdev_id = VIRTIO_ID_RNG,
269 .trans_devid = PCI_DEVICE_ID_VIRTIO_RNG,
270 .class_id = PCI_CLASS_OTHERS,
271 },
272};
273
274static const VirtIOPCIIDInfo *virtio_pci_get_id_info(uint16_t vdev_id)
275{
276 const VirtIOPCIIDInfo *info = NULL;
277 int i;
278
279 for (i = 0; i < ARRAY_SIZE(virtio_pci_id_info); i++) {
280 if (virtio_pci_id_info[i].vdev_id == vdev_id) {
281 info = &virtio_pci_id_info[i];
282 break;
283 }
284 }
285
286 if (!info) {
287 /* The device id is invalid or not added to the id_info yet. */
288 error_report("Invalid virtio device(id %u)", vdev_id);
289 abort();
290 }
291
292 return info;
293}
294
295/*
296 * Get the Transitional Device ID for the specific device, return
297 * zero if the device is non-transitional.
298 */
299uint16_t virtio_pci_get_trans_devid(uint16_t device_id)
300{
301 return virtio_pci_get_id_info(device_id)->trans_devid;
302}
303
304/*
305 * Get the Class ID for the specific device.
306 */
307uint16_t virtio_pci_get_class_id(uint16_t device_id)
308{
309 return virtio_pci_get_id_info(device_id)->class_id;
310}
311
8e93cef1 312static bool virtio_pci_ioeventfd_enabled(DeviceState *d)
9f06e71a
CH		 313{
314 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
315
8e93cef1 316 return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0;
9f06e71a
CH		 317}
318
975acc0a
JW		 319#define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000
320
d9997d89
MA		 321static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy)
322{
323 return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ?
324 QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4;
325}
326
9f06e71a
CH		 327static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
328 int n, bool assign)
25db9ebe 329{
9f06e71a 330 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 331 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
332 VirtQueue *vq = virtio_get_queue(vdev, n);
9a4c0e22
MA		 333 bool legacy = virtio_pci_legacy(proxy);
334 bool modern = virtio_pci_modern(proxy);
bc85ccfd 335 bool fast_mmio = kvm_ioeventfd_any_length_enabled();
9824d2a3 336 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
588255ad 337 MemoryRegion *modern_mr = &proxy->notify.mr;
9824d2a3 338 MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr;
975acc0a 339 MemoryRegion *legacy_mr = &proxy->bar;
d9997d89 340 hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) *
975acc0a
JW		 341 virtio_get_queue_index(vq);
342 hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY;
da146d0a 343
25db9ebe 344 if (assign) {
975acc0a 345 if (modern) {
bc85ccfd
JW		 346 if (fast_mmio) {
347 memory_region_add_eventfd(modern_mr, modern_addr, 0,
348 false, n, notifier);
349 } else {
350 memory_region_add_eventfd(modern_mr, modern_addr, 2,
351 false, n, notifier);
352 }
9824d2a3
JW		 353 if (modern_pio) {
354 memory_region_add_eventfd(modern_notify_mr, 0, 2,
355 true, n, notifier);
356 }
975acc0a
JW		 357 }
358 if (legacy) {
359 memory_region_add_eventfd(legacy_mr, legacy_addr, 2,
360 true, n, notifier);
361 }
25db9ebe 362 } else {
975acc0a 363 if (modern) {
bc85ccfd
JW		 364 if (fast_mmio) {
365 memory_region_del_eventfd(modern_mr, modern_addr, 0,
366 false, n, notifier);
367 } else {
368 memory_region_del_eventfd(modern_mr, modern_addr, 2,
369 false, n, notifier);
370 }
9824d2a3
JW		 371 if (modern_pio) {
372 memory_region_del_eventfd(modern_notify_mr, 0, 2,
373 true, n, notifier);
374 }
975acc0a
JW		 375 }
376 if (legacy) {
377 memory_region_del_eventfd(legacy_mr, legacy_addr, 2,
378 true, n, notifier);
379 }
25db9ebe 380 }
9f06e71a 381 return 0;
25db9ebe
SH		 382}
383
b36e3914 384static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 385{
9f06e71a 386 virtio_bus_start_ioeventfd(&proxy->bus);
25db9ebe
SH		 387}
388
b36e3914 389static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 390{
9f06e71a 391 virtio_bus_stop_ioeventfd(&proxy->bus);
25db9ebe
SH		 392}
393
53c25cea
PB		 394static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
395{
396 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 397 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
15377f6e 398 uint16_t vector;
a8170e5e 399 hwaddr pa;
53c25cea 400
53c25cea
PB		 401 switch (addr) {
402 case VIRTIO_PCI_GUEST_FEATURES:
181103cd
FK		 403 /* Guest does not negotiate properly? We have to assume nothing. */
404 if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
405 val = virtio_bus_get_vdev_bad_features(&proxy->bus);
406 }
ad0c9332 407 virtio_set_features(vdev, val);
53c25cea
PB		 408 break;
409 case VIRTIO_PCI_QUEUE_PFN:
a8170e5e 410 pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
1b8e9b27 411 if (pa == 0) {
75fd6f13 412 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 413 }
7055e687
MT		 414 else
415 virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
53c25cea
PB		 416 break;
417 case VIRTIO_PCI_QUEUE_SEL:
87b3bd1c 418 if (val < VIRTIO_QUEUE_MAX)
53c25cea
PB		 419 vdev->queue_sel = val;
420 break;
421 case VIRTIO_PCI_QUEUE_NOTIFY:
87b3bd1c 422 if (val < VIRTIO_QUEUE_MAX) {
7157e2e2
SH		 423 virtio_queue_notify(vdev, val);
424 }
53c25cea
PB		 425 break;
426 case VIRTIO_PCI_STATUS:
25db9ebe
SH		 427 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
428 virtio_pci_stop_ioeventfd(proxy);
429 }
430
3e607cb5 431 virtio_set_status(vdev, val & 0xFF);
25db9ebe
SH		 432
433 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
434 virtio_pci_start_ioeventfd(proxy);
435 }
436
1b8e9b27 437 if (vdev->status == 0) {
75fd6f13 438 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 439 }
c81131db 440
e43c0b2e
MT		 441 /* Linux before 2.6.34 drives the device without enabling
442 the PCI device bus master bit. Enable it automatically
443 for the guest. This is a PCI spec violation but so is
444 initiating DMA with bus master bit clear. */
445 if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) {
446 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
447 proxy->pci_dev.config[PCI_COMMAND] |
448 PCI_COMMAND_MASTER, 1);
449 }
53c25cea 450 break;
aba800a3 451 case VIRTIO_MSI_CONFIG_VECTOR:
15377f6e
AO		 452 if (vdev->config_vector != VIRTIO_NO_VECTOR) {
453 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
454 }
aba800a3 455 /* Make it possible for guest to discover an error took place. */
15377f6e
AO		 456 if (val < proxy->nvectors) {
457 msix_vector_use(&proxy->pci_dev, val);
458 } else {
aba800a3 459 val = VIRTIO_NO_VECTOR;
15377f6e 460 }
aba800a3
MT		 461 vdev->config_vector = val;
462 break;
463 case VIRTIO_MSI_QUEUE_VECTOR:
15377f6e
AO		 464 vector = virtio_queue_vector(vdev, vdev->queue_sel);
465 if (vector != VIRTIO_NO_VECTOR) {
466 msix_vector_unuse(&proxy->pci_dev, vector);
467 }
aba800a3 468 /* Make it possible for guest to discover an error took place. */
15377f6e
AO		 469 if (val < proxy->nvectors) {
470 msix_vector_use(&proxy->pci_dev, val);
471 } else {
aba800a3 472 val = VIRTIO_NO_VECTOR;
15377f6e 473 }
aba800a3
MT		 474 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
475 break;
476 default:
a8218588
PMD		 477 qemu_log_mask(LOG_GUEST_ERROR,
478 "%s: unexpected address 0x%x value 0x%x\n",
479 __func__, addr, val);
aba800a3 480 break;
53c25cea
PB		 481 }
482}
483
aba800a3 484static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
53c25cea 485{
a3fc66d9 486 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
53c25cea
PB		 487 uint32_t ret = 0xFFFFFFFF;
488
53c25cea
PB		 489 switch (addr) {
490 case VIRTIO_PCI_HOST_FEATURES:
6b8f1020 491 ret = vdev->host_features;
53c25cea
PB		 492 break;
493 case VIRTIO_PCI_GUEST_FEATURES:
704a76fc 494 ret = vdev->guest_features;
53c25cea
PB		 495 break;
496 case VIRTIO_PCI_QUEUE_PFN:
497 ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
498 >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
499 break;
500 case VIRTIO_PCI_QUEUE_NUM:
501 ret = virtio_queue_get_num(vdev, vdev->queue_sel);
502 break;
503 case VIRTIO_PCI_QUEUE_SEL:
504 ret = vdev->queue_sel;
505 break;
506 case VIRTIO_PCI_STATUS:
507 ret = vdev->status;
508 break;
509 case VIRTIO_PCI_ISR:
510 /* reading from the ISR also clears it. */
d73415a3 511 ret = qatomic_xchg(&vdev->isr, 0);
9e64f8a3 512 pci_irq_deassert(&proxy->pci_dev);
53c25cea 513 break;
aba800a3
MT		 514 case VIRTIO_MSI_CONFIG_VECTOR:
515 ret = vdev->config_vector;
516 break;
517 case VIRTIO_MSI_QUEUE_VECTOR:
518 ret = virtio_queue_vector(vdev, vdev->queue_sel);
519 break;
53c25cea
PB		 520 default:
521 break;
522 }
523
524 return ret;
525}
526
df6db5b3
AG		 527static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr,
528 unsigned size)
53c25cea
PB		 529{
530 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 531 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
cbbe4f50 532 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
df6db5b3 533 uint64_t val = 0;
bf697371
AM		 534
535 if (vdev == NULL) {
536 return UINT64_MAX;
537 }
538
aba800a3 539 if (addr < config) {
df6db5b3 540 return virtio_ioport_read(proxy, addr);
aba800a3
MT		 541 }
542 addr -= config;
53c25cea 543
df6db5b3
AG		 544 switch (size) {
545 case 1:
a3fc66d9 546 val = virtio_config_readb(vdev, addr);
df6db5b3
AG		 547 break;
548 case 2:
a3fc66d9 549 val = virtio_config_readw(vdev, addr);
616a6552 550 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 551 val = bswap16(val);
552 }
df6db5b3
AG		 553 break;
554 case 4:
a3fc66d9 555 val = virtio_config_readl(vdev, addr);
616a6552 556 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 557 val = bswap32(val);
558 }
df6db5b3 559 break;
82afa586 560 }
df6db5b3 561 return val;
53c25cea
PB		 562}
563
df6db5b3
AG		 564static void virtio_pci_config_write(void *opaque, hwaddr addr,
565 uint64_t val, unsigned size)
53c25cea
PB		 566{
567 VirtIOPCIProxy *proxy = opaque;
cbbe4f50 568 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
a3fc66d9 569 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
bf697371
AM		 570
571 if (vdev == NULL) {
572 return;
573 }
574
aba800a3
MT		 575 if (addr < config) {
576 virtio_ioport_write(proxy, addr, val);
577 return;
578 }
579 addr -= config;
df6db5b3
AG		 580 /*
581 * Virtio-PCI is odd. Ioports are LE but config space is target native
582 * endian.
583 */
584 switch (size) {
585 case 1:
a3fc66d9 586 virtio_config_writeb(vdev, addr, val);
df6db5b3
AG		 587 break;
588 case 2:
616a6552 589 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 590 val = bswap16(val);
591 }
a3fc66d9 592 virtio_config_writew(vdev, addr, val);
df6db5b3
AG		 593 break;
594 case 4:
616a6552 595 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 596 val = bswap32(val);
597 }
a3fc66d9 598 virtio_config_writel(vdev, addr, val);
df6db5b3 599 break;
82afa586 600 }
53c25cea
PB		 601}
602
da146d0a 603static const MemoryRegionOps virtio_pci_config_ops = {
df6db5b3
AG		 604 .read = virtio_pci_config_read,
605 .write = virtio_pci_config_write,
606 .impl = {
607 .min_access_size = 1,
608 .max_access_size = 4,
609 },
8e4a424b 610 .endianness = DEVICE_LITTLE_ENDIAN,
da146d0a 611};
aba800a3 612
a93c8d82
AK		 613static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy,
614 hwaddr *off, int len)
615{
616 int i;
617 VirtIOPCIRegion *reg;
618
619 for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) {
620 reg = &proxy->regs[i];
621 if (*off >= reg->offset &&
622 *off + len <= reg->offset + reg->size) {
623 *off -= reg->offset;
624 return &reg->mr;
625 }
626 }
627
628 return NULL;
629}
630
1e40356c
MT		 631/* Below are generic functions to do memcpy from/to an address space,
632 * without byteswaps, with input validation.
633 *
634 * As regular address_space_* APIs all do some kind of byteswap at least for
635 * some host/target combinations, we are forced to explicitly convert to a
636 * known-endianness integer value.
637 * It doesn't really matter which endian format to go through, so the code
638 * below selects the endian that causes the least amount of work on the given
639 * host.
640 *
641 * Note: host pointer must be aligned.
642 */
643static
a93c8d82 644void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
1e40356c
MT		 645 const uint8_t *buf, int len)
646{
a93c8d82
AK		 647 uint64_t val;
648 MemoryRegion *mr;
1e40356c
MT		 649
650 /* address_space_* APIs assume an aligned address.
651 * As address is under guest control, handle illegal values.
652 */
653 addr &= ~(len - 1);
654
a93c8d82
AK		 655 mr = virtio_address_space_lookup(proxy, &addr, len);
656 if (!mr) {
657 return;
658 }
659
1e40356c
MT		 660 /* Make sure caller aligned buf properly */
661 assert(!(((uintptr_t)buf) & (len - 1)));
662
663 switch (len) {
664 case 1:
665 val = pci_get_byte(buf);
1e40356c
MT		 666 break;
667 case 2:
9bf825bf 668 val = pci_get_word(buf);
1e40356c
MT		 669 break;
670 case 4:
9bf825bf 671 val = pci_get_long(buf);
1e40356c
MT		 672 break;
673 default:
674 /* As length is under guest control, handle illegal values. */
a93c8d82 675 return;
1e40356c 676 }
d5d680ca 677 memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
062c08d1 678 MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 679}
680
681static void
a93c8d82
AK		 682virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
683 uint8_t *buf, int len)
1e40356c 684{
a93c8d82
AK		 685 uint64_t val;
686 MemoryRegion *mr;
1e40356c
MT		 687
688 /* address_space_* APIs assume an aligned address.
689 * As address is under guest control, handle illegal values.
690 */
691 addr &= ~(len - 1);
692
a93c8d82
AK		 693 mr = virtio_address_space_lookup(proxy, &addr, len);
694 if (!mr) {
695 return;
696 }
697
1e40356c
MT		 698 /* Make sure caller aligned buf properly */
699 assert(!(((uintptr_t)buf) & (len - 1)));
700
d5d680ca 701 memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
062c08d1 702 MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 703 switch (len) {
704 case 1:
1e40356c
MT		 705 pci_set_byte(buf, val);
706 break;
707 case 2:
9bf825bf 708 pci_set_word(buf, val);
1e40356c
MT		 709 break;
710 case 4:
9bf825bf 711 pci_set_long(buf, val);
1e40356c
MT		 712 break;
713 default:
714 /* As length is under guest control, handle illegal values. */
715 break;
716 }
717}
718
206e91d1
VP		 719static void virtio_pci_ats_ctrl_trigger(PCIDevice *pci_dev, bool enable)
720{
721 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
722 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
723 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
724
725 vdev->device_iotlb_enabled = enable;
726
727 if (k->toggle_device_iotlb) {
728 k->toggle_device_iotlb(vdev);
729 }
730}
731
732static void pcie_ats_config_write(PCIDevice *dev, uint32_t address,
733 uint32_t val, int len)
734{
735 uint32_t off;
736 uint16_t ats_cap = dev->exp.ats_cap;
737
738 if (!ats_cap || address < ats_cap) {
739 return;
740 }
741 off = address - ats_cap;
742 if (off >= PCI_EXT_CAP_ATS_SIZEOF) {
743 return;
744 }
745
746 if (range_covers_byte(off, len, PCI_ATS_CTRL + 1)) {
747 virtio_pci_ats_ctrl_trigger(dev, !!(val & PCI_ATS_CTRL_ENABLE));
748 }
749}
750
aba800a3
MT		 751static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
752 uint32_t val, int len)
753{
3f262b26 754 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
a3fc66d9 755 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
ada434cd 756 struct virtio_pci_cfg_cap *cfg;
ed757e14 757
1129714f
MT		 758 pci_default_write_config(pci_dev, address, val, len);
759
eb1556c4
JS		 760 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
761 pcie_cap_flr_write_config(pci_dev, address, val, len);
762 }
763
206e91d1
VP		 764 if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
765 pcie_ats_config_write(pci_dev, address, val, len);
766 }
767
9d7bd082
MR		 768 if (range_covers_byte(address, len, PCI_COMMAND)) {
769 if (!(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
770 virtio_set_disabled(vdev, true);
771 virtio_pci_stop_ioeventfd(proxy);
772 virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
773 } else {
774 virtio_set_disabled(vdev, false);
775 }
ed757e14 776 }
ada434cd
MT		 777
778 if (proxy->config_cap &&
779 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
780 pci_cfg_data),
781 sizeof cfg->pci_cfg_data)) {
782 uint32_t off;
5ae80e62 783 uint32_t caplen;
ada434cd
MT		 784
785 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
786 off = le32_to_cpu(cfg->cap.offset);
5ae80e62 787 caplen = le32_to_cpu(cfg->cap.length);
ada434cd 788
5ae80e62
TH		 789 if (caplen == 1 || caplen == 2 || caplen == 4) {
790 assert(caplen <= sizeof cfg->pci_cfg_data);
791 virtio_address_space_write(proxy, off, cfg->pci_cfg_data, caplen);
ada434cd
MT		 792 }
793 }
794}
795
796static uint32_t virtio_read_config(PCIDevice *pci_dev,
797 uint32_t address, int len)
798{
3f262b26 799 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
ada434cd
MT		 800 struct virtio_pci_cfg_cap *cfg;
801
802 if (proxy->config_cap &&
803 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
804 pci_cfg_data),
805 sizeof cfg->pci_cfg_data)) {
806 uint32_t off;
5ae80e62 807 uint32_t caplen;
ada434cd
MT		 808
809 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
810 off = le32_to_cpu(cfg->cap.offset);
5ae80e62 811 caplen = le32_to_cpu(cfg->cap.length);
ada434cd 812
5ae80e62
TH		 813 if (caplen == 1 || caplen == 2 || caplen == 4) {
814 assert(caplen <= sizeof cfg->pci_cfg_data);
815 virtio_address_space_read(proxy, off, cfg->pci_cfg_data, caplen);
ada434cd
MT		 816 }
817 }
818
819 return pci_default_read_config(pci_dev, address, len);
53c25cea
PB		 820}
821
7d37d351 822static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
d1f6af6a 823 unsigned int vector)
7d37d351 824{
7d37d351 825 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 826 int ret;
7d37d351
JK		 827
828 if (irqfd->users == 0) {
def4c557
LM		 829 KVMRouteChange c = kvm_irqchip_begin_route_changes(kvm_state);
830 ret = kvm_irqchip_add_msi_route(&c, vector, &proxy->pci_dev);
7d37d351
JK		 831 if (ret < 0) {
832 return ret;
833 }
def4c557 834 kvm_irqchip_commit_route_changes(&c);
7d37d351
JK		 835 irqfd->virq = ret;
836 }
837 irqfd->users++;
7d37d351
JK		 838 return 0;
839}
840
841static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy,
7d37d351 842 unsigned int vector)
774345f9
MT		 843{
844 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
845 if (--irqfd->users == 0) {
846 kvm_irqchip_release_virq(kvm_state, irqfd->virq);
847 }
848}
849
f1d0f15a 850static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy,
2e07f69d 851 EventNotifier *n,
f1d0f15a
MT		 852 unsigned int vector)
853{
854 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
9be38598 855 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);
f1d0f15a
MT		 856}
857
858static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy,
2e07f69d 859 EventNotifier *n ,
f1d0f15a 860 unsigned int vector)
7d37d351 861{
7d37d351 862 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 863 int ret;
7d37d351 864
1c9b71a7 865 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq);
7d37d351 866 assert(ret == 0);
f1d0f15a 867}
2e07f69d
CL		 868static int virtio_pci_get_notifier(VirtIOPCIProxy *proxy, int queue_no,
869 EventNotifier **n, unsigned int *vector)
870{
871 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
872 VirtQueue *vq;
873
874 if (queue_no == VIRTIO_CONFIG_IRQ_IDX) {
16805428
CL		 875 *n = virtio_config_get_guest_notifier(vdev);
876 *vector = vdev->config_vector;
2e07f69d
CL		 877 } else {
878 if (!virtio_queue_get_num(vdev, queue_no)) {
879 return -1;
880 }
881 *vector = virtio_queue_vector(vdev, queue_no);
882 vq = virtio_get_queue(vdev, queue_no);
883 *n = virtio_queue_get_guest_notifier(vq);
884 }
885 return 0;
886}
7d37d351 887
ee3b8dc6 888static int kvm_virtio_pci_vector_use_one(VirtIOPCIProxy *proxy, int queue_no)
774345f9 889{
ee3b8dc6
CL		 890 unsigned int vector;
891 int ret;
892 EventNotifier *n;
774345f9 893 PCIDevice *dev = &proxy->pci_dev;
a3fc66d9 894 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 895 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
ee3b8dc6
CL		 896
897 ret = virtio_pci_get_notifier(proxy, queue_no, &n, &vector);
898 if (ret < 0) {
899 return ret;
900 }
901 if (vector >= msix_nr_vectors_allocated(dev)) {
902 return 0;
903 }
904 ret = kvm_virtio_pci_vq_vector_use(proxy, vector);
905 if (ret < 0) {
906 goto undo;
907 }
908 /*
909 * If guest supports masking, set up irqfd now.
910 * Otherwise, delay until unmasked in the frontend.
911 */
912 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
913 ret = kvm_virtio_pci_irqfd_use(proxy, n, vector);
774345f9 914 if (ret < 0) {
ee3b8dc6 915 kvm_virtio_pci_vq_vector_release(proxy, vector);
774345f9 916 goto undo;
7d37d351 917 }
7d37d351 918 }
316011b8 919
ee3b8dc6 920 return 0;
38ce4051 921undo:
ee3b8dc6
CL		 922
923 vector = virtio_queue_vector(vdev, queue_no);
924 if (vector >= msix_nr_vectors_allocated(dev)) {
925 return ret;
926 }
927 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
928 ret = virtio_pci_get_notifier(proxy, queue_no, &n, &vector);
929 if (ret < 0) {
930 return ret;
931 }
932 kvm_virtio_pci_irqfd_release(proxy, n, vector);
933 }
934 return ret;
935}
16805428 936static int kvm_virtio_pci_vector_vq_use(VirtIOPCIProxy *proxy, int nvqs)
ee3b8dc6
CL		 937{
938 int queue_no;
939 int ret = 0;
940 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
941
942 for (queue_no = 0; queue_no < nvqs; queue_no++) {
943 if (!virtio_queue_get_num(vdev, queue_no)) {
944 return -1;
f1d0f15a 945 }
ee3b8dc6 946 ret = kvm_virtio_pci_vector_use_one(proxy, queue_no);
774345f9
MT		 947 }
948 return ret;
7d37d351
JK		 949}
950
16805428
CL		 951static int kvm_virtio_pci_vector_config_use(VirtIOPCIProxy *proxy)
952{
953 return kvm_virtio_pci_vector_use_one(proxy, VIRTIO_CONFIG_IRQ_IDX);
954}
ee3b8dc6
CL		 955
956static void kvm_virtio_pci_vector_release_one(VirtIOPCIProxy *proxy,
957 int queue_no)
774345f9 958{
a3fc66d9 959 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
774345f9 960 unsigned int vector;
2e07f69d 961 EventNotifier *n;
ee3b8dc6
CL		 962 int ret;
963 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
964 PCIDevice *dev = &proxy->pci_dev;
965
966 ret = virtio_pci_get_notifier(proxy, queue_no, &n, &vector);
967 if (ret < 0) {
968 return;
969 }
970 if (vector >= msix_nr_vectors_allocated(dev)) {
971 return;
972 }
973 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
974 kvm_virtio_pci_irqfd_release(proxy, n, vector);
975 }
976 kvm_virtio_pci_vq_vector_release(proxy, vector);
977}
978
16805428 979static void kvm_virtio_pci_vector_vq_release(VirtIOPCIProxy *proxy, int nvqs)
ee3b8dc6
CL		 980{
981 int queue_no;
982 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
983
774345f9
MT		 984 for (queue_no = 0; queue_no < nvqs; queue_no++) {
985 if (!virtio_queue_get_num(vdev, queue_no)) {
986 break;
987 }
ee3b8dc6 988 kvm_virtio_pci_vector_release_one(proxy, queue_no);
774345f9
MT		 989 }
990}
991
16805428
CL		 992static void kvm_virtio_pci_vector_config_release(VirtIOPCIProxy *proxy)
993{
994 kvm_virtio_pci_vector_release_one(proxy, VIRTIO_CONFIG_IRQ_IDX);
995}
996
2e07f69d 997static int virtio_pci_one_vector_unmask(VirtIOPCIProxy *proxy,
a38b2c49
MT		 998 unsigned int queue_no,
999 unsigned int vector,
2e07f69d
CL		 1000 MSIMessage msg,
1001 EventNotifier *n)
774345f9 1002{
a3fc66d9
PB		 1003 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1004 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
a38b2c49 1005 VirtIOIRQFD *irqfd;
53510bfc 1006 int ret = 0;
774345f9 1007
a38b2c49
MT		 1008 if (proxy->vector_irqfd) {
1009 irqfd = &proxy->vector_irqfd[vector];
1010 if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) {
dc9f06ca
PF		 1011 ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg,
1012 &proxy->pci_dev);
a38b2c49
MT		 1013 if (ret < 0) {
1014 return ret;
1015 }
3f1fea0f 1016 kvm_irqchip_commit_routes(kvm_state);
774345f9
MT		 1017 }
1018 }
1019
f1d0f15a
MT		 1020 /* If guest supports masking, irqfd is already setup, unmask it.
1021 * Otherwise, set it up now.
1022 */
5669655a 1023 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 1024 k->guest_notifier_mask(vdev, queue_no, false);
f1d0f15a 1025 /* Test after unmasking to avoid losing events. */
181103cd 1026 if (k->guest_notifier_pending &&
a3fc66d9 1027 k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 1028 event_notifier_set(n);
1029 }
1030 } else {
2e07f69d 1031 ret = kvm_virtio_pci_irqfd_use(proxy, n, vector);
7d37d351 1032 }
774345f9 1033 return ret;
7d37d351
JK		 1034}
1035
2e07f69d 1036static void virtio_pci_one_vector_mask(VirtIOPCIProxy *proxy,
7d37d351 1037 unsigned int queue_no,
2e07f69d
CL		 1038 unsigned int vector,
1039 EventNotifier *n)
7d37d351 1040{
a3fc66d9
PB		 1041 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1042 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
181103cd 1043
f1d0f15a
MT		 1044 /* If guest supports masking, keep irqfd but mask it.
1045 * Otherwise, clean it up now.
1046 */
5669655a 1047 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 1048 k->guest_notifier_mask(vdev, queue_no, true);
f1d0f15a 1049 } else {
2e07f69d 1050 kvm_virtio_pci_irqfd_release(proxy, n, vector);
f1d0f15a 1051 }
7d37d351
JK		 1052}
1053
a38b2c49
MT		 1054static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector,
1055 MSIMessage msg)
7d37d351
JK		 1056{
1057 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 1058 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75 1059 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
2e07f69d 1060 EventNotifier *n;
851c2a75 1061 int ret, index, unmasked = 0;
7d37d351 1062
851c2a75
JW		 1063 while (vq) {
1064 index = virtio_get_queue_index(vq);
1065 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 1066 break;
1067 }
6652d081 1068 if (index < proxy->nvqs_with_notifiers) {
2e07f69d
CL		 1069 n = virtio_queue_get_guest_notifier(vq);
1070 ret = virtio_pci_one_vector_unmask(proxy, index, vector, msg, n);
6652d081
JW		 1071 if (ret < 0) {
1072 goto undo;
1073 }
1074 ++unmasked;
7d37d351 1075 }
851c2a75 1076 vq = virtio_vector_next_queue(vq);
7d37d351 1077 }
16805428
CL		 1078 /* unmask config intr */
1079 if (vector == vdev->config_vector) {
1080 n = virtio_config_get_guest_notifier(vdev);
1081 ret = virtio_pci_one_vector_unmask(proxy, VIRTIO_CONFIG_IRQ_IDX, vector,
1082 msg, n);
1083 if (ret < 0) {
1084 goto undo_config;
1085 }
1086 }
7d37d351 1087 return 0;
16805428
CL		 1088undo_config:
1089 n = virtio_config_get_guest_notifier(vdev);
1090 virtio_pci_one_vector_mask(proxy, VIRTIO_CONFIG_IRQ_IDX, vector, n);
7d37d351 1091undo:
851c2a75 1092 vq = virtio_vector_first_queue(vdev, vector);
6652d081 1093 while (vq && unmasked >= 0) {
851c2a75 1094 index = virtio_get_queue_index(vq);
6652d081 1095 if (index < proxy->nvqs_with_notifiers) {
2e07f69d
CL		 1096 n = virtio_queue_get_guest_notifier(vq);
1097 virtio_pci_one_vector_mask(proxy, index, vector, n);
6652d081
JW		 1098 --unmasked;
1099 }
851c2a75 1100 vq = virtio_vector_next_queue(vq);
7d37d351
JK		 1101 }
1102 return ret;
1103}
1104
a38b2c49 1105static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector)
7d37d351
JK		 1106{
1107 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 1108 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75 1109 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
2e07f69d 1110 EventNotifier *n;
851c2a75 1111 int index;
7d37d351 1112
851c2a75
JW		 1113 while (vq) {
1114 index = virtio_get_queue_index(vq);
2e07f69d 1115 n = virtio_queue_get_guest_notifier(vq);
851c2a75 1116 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 1117 break;
1118 }
6652d081 1119 if (index < proxy->nvqs_with_notifiers) {
2e07f69d 1120 virtio_pci_one_vector_mask(proxy, index, vector, n);
6652d081 1121 }
851c2a75 1122 vq = virtio_vector_next_queue(vq);
7d37d351 1123 }
16805428
CL		 1124
1125 if (vector == vdev->config_vector) {
1126 n = virtio_config_get_guest_notifier(vdev);
1127 virtio_pci_one_vector_mask(proxy, VIRTIO_CONFIG_IRQ_IDX, vector, n);
1128 }
7d37d351
JK		 1129}
1130
a38b2c49
MT		 1131static void virtio_pci_vector_poll(PCIDevice *dev,
1132 unsigned int vector_start,
1133 unsigned int vector_end)
89d62be9
MT		 1134{
1135 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 1136 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 1137 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
89d62be9
MT		 1138 int queue_no;
1139 unsigned int vector;
1140 EventNotifier *notifier;
2e07f69d 1141 int ret;
89d62be9 1142
2d620f59 1143 for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) {
2e07f69d
CL		 1144 ret = virtio_pci_get_notifier(proxy, queue_no, &notifier, &vector);
1145 if (ret < 0) {
89d62be9
MT		 1146 break;
1147 }
89d62be9
MT		 1148 if (vector < vector_start || vector >= vector_end ||
1149 !msix_is_masked(dev, vector)) {
1150 continue;
1151 }
181103cd
FK		 1152 if (k->guest_notifier_pending) {
1153 if (k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 1154 msix_set_pending(dev, vector);
1155 }
1156 } else if (event_notifier_test_and_clear(notifier)) {
89d62be9
MT		 1157 msix_set_pending(dev, vector);
1158 }
1159 }
16805428
CL		 1160 /* poll the config intr */
1161 ret = virtio_pci_get_notifier(proxy, VIRTIO_CONFIG_IRQ_IDX, &notifier,
1162 &vector);
1163 if (ret < 0) {
1164 return;
1165 }
1166 if (vector < vector_start || vector >= vector_end ||
1167 !msix_is_masked(dev, vector)) {
1168 return;
1169 }
1170 if (k->guest_notifier_pending) {
1171 if (k->guest_notifier_pending(vdev, VIRTIO_CONFIG_IRQ_IDX)) {
1172 msix_set_pending(dev, vector);
1173 }
1174 } else if (event_notifier_test_and_clear(notifier)) {
1175 msix_set_pending(dev, vector);
1176 }
1177}
1178
1179void virtio_pci_set_guest_notifier_fd_handler(VirtIODevice *vdev, VirtQueue *vq,
1180 int n, bool assign,
1181 bool with_irqfd)
1182{
1183 if (n == VIRTIO_CONFIG_IRQ_IDX) {
1184 virtio_config_set_guest_notifier_fd_handler(vdev, assign, with_irqfd);
1185 } else {
1186 virtio_queue_set_guest_notifier_fd_handler(vq, assign, with_irqfd);
1187 }
89d62be9
MT		 1188}
1189
1190static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign,
1191 bool with_irqfd)
ade80dc8 1192{
d2a0ccc6 1193 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 1194 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1195 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
16805428
CL		 1196 VirtQueue *vq = NULL;
1197 EventNotifier *notifier = NULL;
1198
1199 if (n == VIRTIO_CONFIG_IRQ_IDX) {
1200 notifier = virtio_config_get_guest_notifier(vdev);
1201 } else {
1202 vq = virtio_get_queue(vdev, n);
1203 notifier = virtio_queue_get_guest_notifier(vq);
1204 }
ade80dc8
MT		 1205
1206 if (assign) {
1207 int r = event_notifier_init(notifier, 0);
1208 if (r < 0) {
1209 return r;
1210 }
16805428 1211 virtio_pci_set_guest_notifier_fd_handler(vdev, vq, n, true, with_irqfd);
ade80dc8 1212 } else {
16805428
CL		 1213 virtio_pci_set_guest_notifier_fd_handler(vdev, vq, n, false,
1214 with_irqfd);
ade80dc8
MT		 1215 event_notifier_cleanup(notifier);
1216 }
1217
5669655a
VK		 1218 if (!msix_enabled(&proxy->pci_dev) &&
1219 vdev->use_guest_notifier_mask &&
1220 vdc->guest_notifier_mask) {
a3fc66d9 1221 vdc->guest_notifier_mask(vdev, n, !assign);
62c96360
MT		 1222 }
1223
ade80dc8
MT		 1224 return 0;
1225}
1226
d2a0ccc6 1227static bool virtio_pci_query_guest_notifiers(DeviceState *d)
5430a28f 1228{
d2a0ccc6 1229 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
5430a28f
MT		 1230 return msix_enabled(&proxy->pci_dev);
1231}
1232
2d620f59 1233static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
54dd9321 1234{
d2a0ccc6 1235 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 1236 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 1237 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
54dd9321 1238 int r, n;
89d62be9
MT		 1239 bool with_irqfd = msix_enabled(&proxy->pci_dev) &&
1240 kvm_msi_via_irqfd_enabled();
54dd9321 1241
87b3bd1c 1242 nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
2d620f59 1243
5a9d5f09
AB		 1244 /*
1245 * When deassigning, pass a consistent nvqs value to avoid leaking
1246 * notifiers. But first check we've actually been configured, exit
1247 * early if we haven't.
2d620f59 1248 */
5a9d5f09
AB		 1249 if (!assign && !proxy->nvqs_with_notifiers) {
1250 return 0;
1251 }
2d620f59
MT		 1252 assert(assign || nvqs == proxy->nvqs_with_notifiers);
1253
1254 proxy->nvqs_with_notifiers = nvqs;
1255
7d37d351 1256 /* Must unset vector notifier while guest notifier is still assigned */
16805428
CL		 1257 if ((proxy->vector_irqfd ||
1258 (vdev->use_guest_notifier_mask && k->guest_notifier_mask)) &&
1259 !assign) {
7d37d351 1260 msix_unset_vector_notifiers(&proxy->pci_dev);
a38b2c49 1261 if (proxy->vector_irqfd) {
16805428
CL		 1262 kvm_virtio_pci_vector_vq_release(proxy, nvqs);
1263 kvm_virtio_pci_vector_config_release(proxy);
a38b2c49
MT		 1264 g_free(proxy->vector_irqfd);
1265 proxy->vector_irqfd = NULL;
1266 }
7d37d351
JK		 1267 }
1268
2d620f59 1269 for (n = 0; n < nvqs; n++) {
54dd9321
MT		 1270 if (!virtio_queue_get_num(vdev, n)) {
1271 break;
1272 }
1273
23fe2b3f 1274 r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd);
54dd9321
MT		 1275 if (r < 0) {
1276 goto assign_error;
1277 }
1278 }
16805428
CL		 1279 r = virtio_pci_set_guest_notifier(d, VIRTIO_CONFIG_IRQ_IDX, assign,
1280 with_irqfd);
1281 if (r < 0) {
1282 goto config_assign_error;
1283 }
7d37d351 1284 /* Must set vector notifier after guest notifier has been assigned */
16805428
CL		 1285 if ((with_irqfd ||
1286 (vdev->use_guest_notifier_mask && k->guest_notifier_mask)) &&
1287 assign) {
a38b2c49
MT		 1288 if (with_irqfd) {
1289 proxy->vector_irqfd =
1290 g_malloc0(sizeof(*proxy->vector_irqfd) *
1291 msix_nr_vectors_allocated(&proxy->pci_dev));
16805428
CL		 1292 r = kvm_virtio_pci_vector_vq_use(proxy, nvqs);
1293 if (r < 0) {
1294 goto config_assign_error;
1295 }
1296 r = kvm_virtio_pci_vector_config_use(proxy);
a38b2c49 1297 if (r < 0) {
16805428 1298 goto config_error;
a38b2c49 1299 }
774345f9 1300 }
16805428
CL		 1301
1302 r = msix_set_vector_notifiers(&proxy->pci_dev, virtio_pci_vector_unmask,
a38b2c49
MT		 1303 virtio_pci_vector_mask,
1304 virtio_pci_vector_poll);
7d37d351 1305 if (r < 0) {
774345f9 1306 goto notifiers_error;
7d37d351
JK		 1307 }
1308 }
1309
54dd9321
MT		 1310 return 0;
1311
774345f9 1312notifiers_error:
a38b2c49
MT		 1313 if (with_irqfd) {
1314 assert(assign);
16805428 1315 kvm_virtio_pci_vector_vq_release(proxy, nvqs);
a38b2c49 1316 }
16805428
CL		 1317config_error:
1318 if (with_irqfd) {
1319 kvm_virtio_pci_vector_config_release(proxy);
1320 }
1321config_assign_error:
1322 virtio_pci_set_guest_notifier(d, VIRTIO_CONFIG_IRQ_IDX, !assign,
1323 with_irqfd);
54dd9321
MT		 1324assign_error:
1325 /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */
7d37d351 1326 assert(assign);
54dd9321 1327 while (--n >= 0) {
89d62be9 1328 virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd);
54dd9321 1329 }
4396d4bd 1330 g_free(proxy->vector_irqfd);
1331 proxy->vector_irqfd = NULL;
54dd9321
MT		 1332 return r;
1333}
1334
6f80e617
TB		 1335static int virtio_pci_set_host_notifier_mr(DeviceState *d, int n,
1336 MemoryRegion *mr, bool assign)
1337{
1338 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
1339 int offset;
1340
1341 if (n >= VIRTIO_QUEUE_MAX || !virtio_pci_modern(proxy) ||
1342 virtio_pci_queue_mem_mult(proxy) != memory_region_size(mr)) {
1343 return -1;
1344 }
1345
1346 if (assign) {
1347 offset = virtio_pci_queue_mem_mult(proxy) * n;
1348 memory_region_add_subregion_overlap(&proxy->notify.mr, offset, mr, 1);
1349 } else {
1350 memory_region_del_subregion(&proxy->notify.mr, mr);
1351 }
1352
1353 return 0;
1354}
1355
d2a0ccc6 1356static void virtio_pci_vmstate_change(DeviceState *d, bool running)
25db9ebe 1357{
d2a0ccc6 1358 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 1359 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
25db9ebe
SH		 1360
1361 if (running) {
68a27b20
MT		 1362 /* Old QEMU versions did not set bus master enable on status write.
1363 * Detect DRIVER set and enable it.
1364 */
1365 if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) &&
1366 (vdev->status & VIRTIO_CONFIG_S_DRIVER) &&
45363e46 1367 !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
68a27b20
MT		 1368 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
1369 proxy->pci_dev.config[PCI_COMMAND] |
1370 PCI_COMMAND_MASTER, 1);
89c473fd 1371 }
25db9ebe 1372 virtio_pci_start_ioeventfd(proxy);
ade80dc8 1373 } else {
25db9ebe 1374 virtio_pci_stop_ioeventfd(proxy);
ade80dc8 1375 }
ade80dc8
MT		 1376}
1377
085bccb7
FK		 1378/*
1379 * virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
1380 */
1381
e0d686bf
JW		 1382static int virtio_pci_query_nvectors(DeviceState *d)
1383{
1384 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1385
1386 return proxy->nvectors;
1387}
1388
8607f5c3
JW		 1389static AddressSpace *virtio_pci_get_dma_as(DeviceState *d)
1390{
1391 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1392 PCIDevice *dev = &proxy->pci_dev;
1393
f0edf239 1394 return pci_get_address_space(dev);
8607f5c3
JW		 1395}
1396
3d1e5d86
JW		 1397static bool virtio_pci_iommu_enabled(DeviceState *d)
1398{
1399 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1400 PCIDevice *dev = &proxy->pci_dev;
1401 AddressSpace *dma_as = pci_device_iommu_address_space(dev);
1402
1403 if (dma_as == &address_space_memory) {
1404 return false;
1405 }
1406
1407 return true;
1408}
1409
f19bcdfe
JW		 1410static bool virtio_pci_queue_enabled(DeviceState *d, int n)
1411{
1412 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1413 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1414
1415 if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
a48aaf88 1416 return proxy->vqs[n].enabled;
f19bcdfe
JW		 1417 }
1418
0c9753eb 1419 return virtio_queue_enabled_legacy(vdev, n);
f19bcdfe
JW		 1420}
1421
ada434cd 1422static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
dfb8e184
MT		 1423 struct virtio_pci_cap *cap)
1424{
1425 PCIDevice *dev = &proxy->pci_dev;
1426 int offset;
1427
9a7c2a59
MZ		 1428 offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
1429 cap->cap_len, &error_abort);
dfb8e184
MT		 1430
1431 assert(cap->cap_len >= sizeof *cap);
1432 memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
1433 cap->cap_len - PCI_CAP_FLAGS);
ada434cd
MT		 1434
1435 return offset;
dfb8e184
MT		 1436}
1437
605a16a7
DDAG		 1438int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy,
1439 uint8_t bar, uint64_t offset, uint64_t length,
1440 uint8_t id)
1441{
1442 struct virtio_pci_cap64 cap = {
1443 .cap.cap_len = sizeof cap,
1444 .cap.cfg_type = VIRTIO_PCI_CAP_SHARED_MEMORY_CFG,
1445 };
1446
1447 cap.cap.bar = bar;
1448 cap.cap.length = cpu_to_le32(length);
1449 cap.length_hi = cpu_to_le32(length >> 32);
1450 cap.cap.offset = cpu_to_le32(offset);
1451 cap.offset_hi = cpu_to_le32(offset >> 32);
1452 cap.cap.id = id;
1453 return virtio_pci_add_mem_cap(proxy, &cap.cap);
1454}
1455
dfb8e184
MT		 1456static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
1457 unsigned size)
1458{
1459 VirtIOPCIProxy *proxy = opaque;
1460 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1461 uint32_t val = 0;
1462 int i;
1463
80ebfd69
AM		 1464 if (vdev == NULL) {
1465 return UINT64_MAX;
1466 }
1467
dfb8e184
MT		 1468 switch (addr) {
1469 case VIRTIO_PCI_COMMON_DFSELECT:
1470 val = proxy->dfselect;
1471 break;
1472 case VIRTIO_PCI_COMMON_DF:
1473 if (proxy->dfselect <= 1) {
9b706dbb
MT		 1474 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
1475
1476 val = (vdev->host_features & ~vdc->legacy_features) >>
5f456073 1477 (32 * proxy->dfselect);
dfb8e184
MT		 1478 }
1479 break;
1480 case VIRTIO_PCI_COMMON_GFSELECT:
1481 val = proxy->gfselect;
1482 break;
1483 case VIRTIO_PCI_COMMON_GF:
3750dabc 1484 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1485 val = proxy->guest_features[proxy->gfselect];
1486 }
1487 break;
1488 case VIRTIO_PCI_COMMON_MSIX:
1489 val = vdev->config_vector;
1490 break;
1491 case VIRTIO_PCI_COMMON_NUMQ:
1492 for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) {
1493 if (virtio_queue_get_num(vdev, i)) {
1494 val = i + 1;
1495 }
1496 }
1497 break;
1498 case VIRTIO_PCI_COMMON_STATUS:
1499 val = vdev->status;
1500 break;
1501 case VIRTIO_PCI_COMMON_CFGGENERATION:
b8f05908 1502 val = vdev->generation;
dfb8e184
MT		 1503 break;
1504 case VIRTIO_PCI_COMMON_Q_SELECT:
1505 val = vdev->queue_sel;
1506 break;
1507 case VIRTIO_PCI_COMMON_Q_SIZE:
1508 val = virtio_queue_get_num(vdev, vdev->queue_sel);
1509 break;
1510 case VIRTIO_PCI_COMMON_Q_MSIX:
1511 val = virtio_queue_vector(vdev, vdev->queue_sel);
1512 break;
1513 case VIRTIO_PCI_COMMON_Q_ENABLE:
1514 val = proxy->vqs[vdev->queue_sel].enabled;
1515 break;
1516 case VIRTIO_PCI_COMMON_Q_NOFF:
1517 /* Simply map queues in order */
1518 val = vdev->queue_sel;
1519 break;
1520 case VIRTIO_PCI_COMMON_Q_DESCLO:
1521 val = proxy->vqs[vdev->queue_sel].desc[0];
1522 break;
1523 case VIRTIO_PCI_COMMON_Q_DESCHI:
1524 val = proxy->vqs[vdev->queue_sel].desc[1];
1525 break;
1526 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1527 val = proxy->vqs[vdev->queue_sel].avail[0];
1528 break;
1529 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1530 val = proxy->vqs[vdev->queue_sel].avail[1];
1531 break;
1532 case VIRTIO_PCI_COMMON_Q_USEDLO:
1533 val = proxy->vqs[vdev->queue_sel].used[0];
1534 break;
1535 case VIRTIO_PCI_COMMON_Q_USEDHI:
1536 val = proxy->vqs[vdev->queue_sel].used[1];
1537 break;
805d782d
XZ		 1538 case VIRTIO_PCI_COMMON_Q_RESET:
1539 val = proxy->vqs[vdev->queue_sel].reset;
1540 break;
dfb8e184
MT		 1541 default:
1542 val = 0;
1543 }
1544
1545 return val;
1546}
1547
1548static void virtio_pci_common_write(void *opaque, hwaddr addr,
1549 uint64_t val, unsigned size)
1550{
1551 VirtIOPCIProxy *proxy = opaque;
1552 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
15377f6e 1553 uint16_t vector;
dfb8e184 1554
80ebfd69
AM		 1555 if (vdev == NULL) {
1556 return;
1557 }
1558
dfb8e184
MT		 1559 switch (addr) {
1560 case VIRTIO_PCI_COMMON_DFSELECT:
1561 proxy->dfselect = val;
1562 break;
1563 case VIRTIO_PCI_COMMON_GFSELECT:
1564 proxy->gfselect = val;
1565 break;
1566 case VIRTIO_PCI_COMMON_GF:
3750dabc 1567 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1568 proxy->guest_features[proxy->gfselect] = val;
1569 virtio_set_features(vdev,
1570 (((uint64_t)proxy->guest_features[1]) << 32) |
1571 proxy->guest_features[0]);
1572 }
1573 break;
1574 case VIRTIO_PCI_COMMON_MSIX:
15377f6e
AO		 1575 if (vdev->config_vector != VIRTIO_NO_VECTOR) {
1576 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
1577 }
dfb8e184 1578 /* Make it possible for guest to discover an error took place. */
15377f6e
AO		 1579 if (val < proxy->nvectors) {
1580 msix_vector_use(&proxy->pci_dev, val);
1581 } else {
dfb8e184
MT		 1582 val = VIRTIO_NO_VECTOR;
1583 }
1584 vdev->config_vector = val;
1585 break;
1586 case VIRTIO_PCI_COMMON_STATUS:
1587 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
1588 virtio_pci_stop_ioeventfd(proxy);
1589 }
1590
1591 virtio_set_status(vdev, val & 0xFF);
1592
1593 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
1594 virtio_pci_start_ioeventfd(proxy);
1595 }
1596
1597 if (vdev->status == 0) {
75fd6f13 1598 virtio_pci_reset(DEVICE(proxy));
dfb8e184
MT		 1599 }
1600
1601 break;
1602 case VIRTIO_PCI_COMMON_Q_SELECT:
1603 if (val < VIRTIO_QUEUE_MAX) {
1604 vdev->queue_sel = val;
1605 }
1606 break;
1607 case VIRTIO_PCI_COMMON_Q_SIZE:
1608 proxy->vqs[vdev->queue_sel].num = val;
d0c5f643
MT		 1609 virtio_queue_set_num(vdev, vdev->queue_sel,
1610 proxy->vqs[vdev->queue_sel].num);
f0d634ea 1611 virtio_init_region_cache(vdev, vdev->queue_sel);
dfb8e184
MT		 1612 break;
1613 case VIRTIO_PCI_COMMON_Q_MSIX:
15377f6e
AO		 1614 vector = virtio_queue_vector(vdev, vdev->queue_sel);
1615 if (vector != VIRTIO_NO_VECTOR) {
1616 msix_vector_unuse(&proxy->pci_dev, vector);
1617 }
dfb8e184 1618 /* Make it possible for guest to discover an error took place. */
15377f6e
AO		 1619 if (val < proxy->nvectors) {
1620 msix_vector_use(&proxy->pci_dev, val);
1621 } else {
dfb8e184
MT		 1622 val = VIRTIO_NO_VECTOR;
1623 }
1624 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
1625 break;
1626 case VIRTIO_PCI_COMMON_Q_ENABLE:
10d35e58
JW		 1627 if (val == 1) {
1628 virtio_queue_set_num(vdev, vdev->queue_sel,
1629 proxy->vqs[vdev->queue_sel].num);
1630 virtio_queue_set_rings(vdev, vdev->queue_sel,
dfb8e184
MT		 1631 ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
1632 proxy->vqs[vdev->queue_sel].desc[0],
1633 ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
1634 proxy->vqs[vdev->queue_sel].avail[0],
1635 ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
1636 proxy->vqs[vdev->queue_sel].used[0]);
10d35e58 1637 proxy->vqs[vdev->queue_sel].enabled = 1;
805d782d 1638 proxy->vqs[vdev->queue_sel].reset = 0;
d1060e3d 1639 virtio_queue_enable(vdev, vdev->queue_sel);
10d35e58
JW		 1640 } else {
1641 virtio_error(vdev, "wrong value for queue_enable %"PRIx64, val);
1642 }
dfb8e184
MT		 1643 break;
1644 case VIRTIO_PCI_COMMON_Q_DESCLO:
1645 proxy->vqs[vdev->queue_sel].desc[0] = val;
1646 break;
1647 case VIRTIO_PCI_COMMON_Q_DESCHI:
1648 proxy->vqs[vdev->queue_sel].desc[1] = val;
1649 break;
1650 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1651 proxy->vqs[vdev->queue_sel].avail[0] = val;
1652 break;
1653 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1654 proxy->vqs[vdev->queue_sel].avail[1] = val;
1655 break;
1656 case VIRTIO_PCI_COMMON_Q_USEDLO:
1657 proxy->vqs[vdev->queue_sel].used[0] = val;
1658 break;
1659 case VIRTIO_PCI_COMMON_Q_USEDHI:
1660 proxy->vqs[vdev->queue_sel].used[1] = val;
1661 break;
805d782d
XZ		 1662 case VIRTIO_PCI_COMMON_Q_RESET:
1663 if (val == 1) {
1664 proxy->vqs[vdev->queue_sel].reset = 1;
1665
1666 virtio_queue_reset(vdev, vdev->queue_sel);
1667
1668 proxy->vqs[vdev->queue_sel].reset = 0;
1669 proxy->vqs[vdev->queue_sel].enabled = 0;
1670 }
1671 break;
dfb8e184
MT		 1672 default:
1673 break;
1674 }
1675}
1676
1677
1678static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr,
1679 unsigned size)
1680{
df07a8f8
AM		 1681 VirtIOPCIProxy *proxy = opaque;
1682 if (virtio_bus_get_device(&proxy->bus) == NULL) {
1683 return UINT64_MAX;
1684 }
1685
dfb8e184
MT		 1686 return 0;
1687}
1688
1689static void virtio_pci_notify_write(void *opaque, hwaddr addr,
1690 uint64_t val, unsigned size)
1691{
ccec7e96
AM		 1692 VirtIOPCIProxy *proxy = opaque;
1693 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1694
d9997d89 1695 unsigned queue = addr / virtio_pci_queue_mem_mult(proxy);
dfb8e184 1696
ccec7e96 1697 if (vdev != NULL && queue < VIRTIO_QUEUE_MAX) {
31cc62bb 1698 trace_virtio_pci_notify_write(addr, val, size);
dfb8e184
MT		 1699 virtio_queue_notify(vdev, queue);
1700 }
1701}
1702
9824d2a3
JW		 1703static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr,
1704 uint64_t val, unsigned size)
1705{
ccec7e96
AM		 1706 VirtIOPCIProxy *proxy = opaque;
1707 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1708
9824d2a3
JW		 1709 unsigned queue = val;
1710
ccec7e96 1711 if (vdev != NULL && queue < VIRTIO_QUEUE_MAX) {
31cc62bb 1712 trace_virtio_pci_notify_write_pio(addr, val, size);
9824d2a3
JW		 1713 virtio_queue_notify(vdev, queue);
1714 }
1715}
1716
dfb8e184
MT		 1717static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr,
1718 unsigned size)
1719{
1720 VirtIOPCIProxy *proxy = opaque;
1721 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
c3fd7061
YB		 1722 uint64_t val;
1723
1724 if (vdev == NULL) {
df07a8f8 1725 return UINT64_MAX;
c3fd7061 1726 }
dfb8e184 1727
c3fd7061
YB		 1728 val = qatomic_xchg(&vdev->isr, 0);
1729 pci_irq_deassert(&proxy->pci_dev);
dfb8e184
MT		 1730 return val;
1731}
1732
1733static void virtio_pci_isr_write(void *opaque, hwaddr addr,
1734 uint64_t val, unsigned size)
1735{
1736}
1737
1738static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr,
1739 unsigned size)
1740{
ccec7e96
AM		 1741 VirtIOPCIProxy *proxy = opaque;
1742 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
51e0e42c 1743 uint64_t val;
dfb8e184 1744
ccec7e96 1745 if (vdev == NULL) {
df07a8f8 1746 return UINT64_MAX;
ccec7e96
AM		 1747 }
1748
dfb8e184
MT		 1749 switch (size) {
1750 case 1:
54c720d4 1751 val = virtio_config_modern_readb(vdev, addr);
dfb8e184
MT		 1752 break;
1753 case 2:
54c720d4 1754 val = virtio_config_modern_readw(vdev, addr);
dfb8e184
MT		 1755 break;
1756 case 4:
54c720d4 1757 val = virtio_config_modern_readl(vdev, addr);
dfb8e184 1758 break;
51e0e42c
YB		 1759 default:
1760 val = 0;
1761 break;
dfb8e184
MT		 1762 }
1763 return val;
1764}
1765
1766static void virtio_pci_device_write(void *opaque, hwaddr addr,
1767 uint64_t val, unsigned size)
1768{
ccec7e96
AM		 1769 VirtIOPCIProxy *proxy = opaque;
1770 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1771
1772 if (vdev == NULL) {
1773 return;
1774 }
1775
dfb8e184
MT		 1776 switch (size) {
1777 case 1:
54c720d4 1778 virtio_config_modern_writeb(vdev, addr, val);
dfb8e184
MT		 1779 break;
1780 case 2:
54c720d4 1781 virtio_config_modern_writew(vdev, addr, val);
dfb8e184
MT		 1782 break;
1783 case 4:
54c720d4 1784 virtio_config_modern_writel(vdev, addr, val);
dfb8e184
MT		 1785 break;
1786 }
1787}
1788
b74259e3
AB		 1789static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy,
1790 const char *vdev_name)
1141ce21
GH		 1791{
1792 static const MemoryRegionOps common_ops = {
1793 .read = virtio_pci_common_read,
1794 .write = virtio_pci_common_write,
1795 .impl = {
1796 .min_access_size = 1,
1797 .max_access_size = 4,
1798 },
1799 .endianness = DEVICE_LITTLE_ENDIAN,
1800 };
1801 static const MemoryRegionOps isr_ops = {
1802 .read = virtio_pci_isr_read,
1803 .write = virtio_pci_isr_write,
1804 .impl = {
1805 .min_access_size = 1,
1806 .max_access_size = 4,
1807 },
1808 .endianness = DEVICE_LITTLE_ENDIAN,
1809 };
1810 static const MemoryRegionOps device_ops = {
1811 .read = virtio_pci_device_read,
1812 .write = virtio_pci_device_write,
1813 .impl = {
1814 .min_access_size = 1,
1815 .max_access_size = 4,
1816 },
1817 .endianness = DEVICE_LITTLE_ENDIAN,
1818 };
1819 static const MemoryRegionOps notify_ops = {
1820 .read = virtio_pci_notify_read,
1821 .write = virtio_pci_notify_write,
1822 .impl = {
1823 .min_access_size = 1,
1824 .max_access_size = 4,
1825 },
1826 .endianness = DEVICE_LITTLE_ENDIAN,
1827 };
9824d2a3
JW		 1828 static const MemoryRegionOps notify_pio_ops = {
1829 .read = virtio_pci_notify_read,
1830 .write = virtio_pci_notify_write_pio,
1831 .impl = {
1832 .min_access_size = 1,
1833 .max_access_size = 4,
1834 },
1835 .endianness = DEVICE_LITTLE_ENDIAN,
1836 };
b74259e3 1837 g_autoptr(GString) name = g_string_new(NULL);
9824d2a3 1838
b74259e3 1839 g_string_printf(name, "virtio-pci-common-%s", vdev_name);
1141ce21
GH		 1840 memory_region_init_io(&proxy->common.mr, OBJECT(proxy),
1841 &common_ops,
1842 proxy,
b74259e3 1843 name->str,
b6ce27a5 1844 proxy->common.size);
a3cc2e81 1845
b74259e3 1846 g_string_printf(name, "virtio-pci-isr-%s", vdev_name);
1141ce21
GH		 1847 memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),
1848 &isr_ops,
1849 proxy,
b74259e3 1850 name->str,
b6ce27a5 1851 proxy->isr.size);
a3cc2e81 1852
b74259e3 1853 g_string_printf(name, "virtio-pci-device-%s", vdev_name);
1141ce21
GH		 1854 memory_region_init_io(&proxy->device.mr, OBJECT(proxy),
1855 &device_ops,
ccec7e96 1856 proxy,
b74259e3 1857 name->str,
b6ce27a5 1858 proxy->device.size);
a3cc2e81 1859
b74259e3 1860 g_string_printf(name, "virtio-pci-notify-%s", vdev_name);
1141ce21
GH		 1861 memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),
1862 &notify_ops,
ccec7e96 1863 proxy,
b74259e3 1864 name->str,
b6ce27a5 1865 proxy->notify.size);
9824d2a3 1866
b74259e3 1867 g_string_printf(name, "virtio-pci-notify-pio-%s", vdev_name);
9824d2a3
JW		 1868 memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy),
1869 &notify_pio_ops,
ccec7e96 1870 proxy,
b74259e3 1871 name->str,
e3aab6c7 1872 proxy->notify_pio.size);
a3cc2e81
GH		 1873}
1874
1875static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy,
54790d71 1876 VirtIOPCIRegion *region,
9824d2a3
JW		 1877 struct virtio_pci_cap *cap,
1878 MemoryRegion *mr,
1879 uint8_t bar)
a3cc2e81 1880{
9824d2a3 1881 memory_region_add_subregion(mr, region->offset, &region->mr);
54790d71 1882
fc004905 1883 cap->cfg_type = region->type;
9824d2a3 1884 cap->bar = bar;
54790d71 1885 cap->offset = cpu_to_le32(region->offset);
b6ce27a5 1886 cap->length = cpu_to_le32(region->size);
54790d71 1887 virtio_pci_add_mem_cap(proxy, cap);
9824d2a3
JW		 1888
1889}
1890
1891static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy,
1892 VirtIOPCIRegion *region,
1893 struct virtio_pci_cap *cap)
1894{
1895 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1896 &proxy->modern_bar, proxy->modern_mem_bar_idx);
1141ce21 1897}
dfb8e184 1898
9824d2a3
JW		 1899static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy,
1900 VirtIOPCIRegion *region,
1901 struct virtio_pci_cap *cap)
1902{
1903 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1904 &proxy->io_bar, proxy->modern_io_bar_idx);
9824d2a3
JW		 1905}
1906
1907static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy,
1908 VirtIOPCIRegion *region)
27462695
MT		 1909{
1910 memory_region_del_subregion(&proxy->modern_bar,
1911 &region->mr);
1912}
1913
9824d2a3
JW		 1914static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy,
1915 VirtIOPCIRegion *region)
1916{
1917 memory_region_del_subregion(&proxy->io_bar,
1918 &region->mr);
1919}
1920
d1b4259f
MC		 1921static void virtio_pci_pre_plugged(DeviceState *d, Error **errp)
1922{
1923 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1924 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1925
1926 if (virtio_pci_modern(proxy)) {
1927 virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1);
1928 }
1929
1930 virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE);
1931}
1932
085bccb7 1933/* This is called by virtio-bus just after the device is plugged. */
e8398045 1934static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
085bccb7
FK		 1935{
1936 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1937 VirtioBusState *bus = &proxy->bus;
9a4c0e22 1938 bool legacy = virtio_pci_legacy(proxy);
d1b4259f 1939 bool modern;
9824d2a3 1940 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
085bccb7
FK		 1941 uint8_t *config;
1942 uint32_t size;
6b8f1020 1943 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
085bccb7 1944
d1b4259f
MC		 1945 /*
1946 * Virtio capabilities present without
1947 * VIRTIO_F_VERSION_1 confuses guests
1948 */
66d1c4c1
MC		 1949 if (!proxy->ignore_backend_features &&
1950 !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
d1b4259f
MC		 1951 virtio_pci_disable_modern(proxy);
1952
1953 if (!legacy) {
1954 error_setg(errp, "Device doesn't support modern mode, and legacy"
1955 " mode is disabled");
1956 error_append_hint(errp, "Set disable-legacy to off\n");
1957
1958 return;
1959 }
1960 }
1961
1962 modern = virtio_pci_modern(proxy);
1963
085bccb7
FK		 1964 config = proxy->pci_dev.config;
1965 if (proxy->class_code) {
1966 pci_config_set_class(config, proxy->class_code);
1967 }
e266d421
GH		 1968
1969 if (legacy) {
9b3a35ec 1970 if (!virtio_legacy_allowed(vdev)) {
d55f5182
SG		 1971 /*
1972 * To avoid migration issues, we allow legacy mode when legacy
1973 * check is disabled in the old machine types (< 5.1).
1974 */
1975 if (virtio_legacy_check_disabled(vdev)) {
1976 warn_report("device is modern-only, but for backward "
1977 "compatibility legacy is allowed");
1978 } else {
1979 error_setg(errp,
1980 "device is modern-only, use disable-legacy=on");
1981 return;
1982 }
9b3a35ec 1983 }
8607f5c3
JW		 1984 if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
1985 error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
2080a29f 1986 " neither legacy nor transitional device");
c1dadb84 1987 return;
8607f5c3 1988 }
f2bc54de
LP		 1989 /*
1990 * Legacy and transitional devices use specific subsystem IDs.
1991 * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
1992 * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
1993 */
e266d421 1994 pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
22733245
LM		 1995 if (proxy->trans_devid) {
1996 pci_config_set_device_id(config, proxy->trans_devid);
1997 }
e266d421
GH		 1998 } else {
1999 /* pure virtio-1.0 */
2000 pci_set_word(config + PCI_VENDOR_ID,
2001 PCI_VENDOR_ID_REDHAT_QUMRANET);
2002 pci_set_word(config + PCI_DEVICE_ID,
0468fe82 2003 PCI_DEVICE_ID_VIRTIO_10_BASE + virtio_bus_get_vdev_id(bus));
e266d421
GH		 2004 pci_config_set_revision(config, 1);
2005 }
085bccb7
FK		 2006 config[PCI_INTERRUPT_PIN] = 1;
2007
dfb8e184 2008
e266d421 2009 if (modern) {
cc52ea90
GH		 2010 struct virtio_pci_cap cap = {
2011 .cap_len = sizeof cap,
dfb8e184
MT		 2012 };
2013 struct virtio_pci_notify_cap notify = {
dfb8e184 2014 .cap.cap_len = sizeof notify,
dfb8e184 2015 .notify_off_multiplier =
d9997d89 2016 cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
dfb8e184 2017 };
ada434cd
MT		 2018 struct virtio_pci_cfg_cap cfg = {
2019 .cap.cap_len = sizeof cfg,
2020 .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
2021 };
9824d2a3
JW		 2022 struct virtio_pci_notify_cap notify_pio = {
2023 .cap.cap_len = sizeof notify,
2024 .notify_off_multiplier = cpu_to_le32(0x0),
2025 };
dfb8e184 2026
9824d2a3 2027 struct virtio_pci_cfg_cap *cfg_mask;
dfb8e184 2028
b74259e3 2029 virtio_pci_modern_regions_init(proxy, vdev->name);
9824d2a3
JW		 2030
2031 virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
2032 virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
2033 virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
2034 virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
2035
2036 if (modern_pio) {
2037 memory_region_init(&proxy->io_bar, OBJECT(proxy),
2038 "virtio-pci-io", 0x4);
2039
7a25126d 2040 pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
9824d2a3
JW		 2041 PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
2042
2043 virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
2044 &notify_pio.cap);
2045 }
ada434cd 2046
7a25126d 2047 pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
4e93a68e
GH		 2048 PCI_BASE_ADDRESS_SPACE_MEMORY |
2049 PCI_BASE_ADDRESS_MEM_PREFETCH |
2050 PCI_BASE_ADDRESS_MEM_TYPE_64,
dfb8e184 2051 &proxy->modern_bar);
ada434cd
MT		 2052
2053 proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
2054 cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
2055 pci_set_byte(&cfg_mask->cap.bar, ~0x0);
2056 pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
2057 pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
2058 pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
dfb8e184
MT		 2059 }
2060
0d583647
RH		 2061 if (proxy->nvectors) {
2062 int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
ee640c62 2063 proxy->msix_bar_idx, NULL);
0d583647 2064 if (err) {
ee640c62 2065 /* Notice when a system that supports MSIx can't initialize it */
0d583647 2066 if (err != -ENOTSUP) {
0765691e
MA		 2067 warn_report("unable to init msix vectors to %" PRIu32,
2068 proxy->nvectors);
0d583647
RH		 2069 }
2070 proxy->nvectors = 0;
2071 }
085bccb7
FK		 2072 }
2073
2074 proxy->pci_dev.config_write = virtio_write_config;
ada434cd 2075 proxy->pci_dev.config_read = virtio_read_config;
085bccb7 2076
e266d421
GH		 2077 if (legacy) {
2078 size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
2079 + virtio_bus_get_vdev_config_len(bus);
1d0148fe 2080 size = pow2ceil(size);
085bccb7 2081
e266d421
GH		 2082 memory_region_init_io(&proxy->bar, OBJECT(proxy),
2083 &virtio_pci_config_ops,
2084 proxy, "virtio-pci", size);
dfb8e184 2085
7a25126d 2086 pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
23c5e397 2087 PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
e266d421 2088 }
085bccb7
FK		 2089}
2090
06a13073
PB		 2091static void virtio_pci_device_unplugged(DeviceState *d)
2092{
06a13073 2093 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
9a4c0e22 2094 bool modern = virtio_pci_modern(proxy);
9824d2a3 2095 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
06a13073
PB		 2096
2097 virtio_pci_stop_ioeventfd(proxy);
27462695
MT		 2098
2099 if (modern) {
9824d2a3
JW		 2100 virtio_pci_modern_mem_region_unmap(proxy, &proxy->common);
2101 virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr);
2102 virtio_pci_modern_mem_region_unmap(proxy, &proxy->device);
2103 virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify);
2104 if (modern_pio) {
2105 virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio);
2106 }
27462695 2107 }
06a13073
PB		 2108}
2109
fc079951 2110static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
085bccb7 2111{
b6ce27a5 2112 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
085bccb7 2113 VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);
fd56e061
DG		 2114 bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
2115 !pci_bus_is_root(pci_get_bus(pci_dev));
fc079951 2116
c324fd0a 2117 if (kvm_enabled() && !kvm_has_many_ioeventfds()) {
ca2b413c
PB		 2118 proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
2119 }
2120
3909c079
PD		 2121 /* fd-based ioevents can't be synchronized in record/replay */
2122 if (replay_mode != REPLAY_MODE_NONE) {
2123 proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
2124 }
2125
b6ce27a5
GH		 2126 /*
2127 * virtio pci bar layout used by default.
2128 * subclasses can re-arrange things if needed.
2129 *
2130 * region 0 -- virtio legacy io bar
2131 * region 1 -- msi-x bar
e6779156 2132 * region 2 -- virtio modern io bar (off by default)
b6ce27a5
GH		 2133 * region 4+5 -- virtio modern memory (64bit) bar
2134 *
2135 */
7a25126d
CF		 2136 proxy->legacy_io_bar_idx = 0;
2137 proxy->msix_bar_idx = 1;
2138 proxy->modern_io_bar_idx = 2;
2139 proxy->modern_mem_bar_idx = 4;
b6ce27a5
GH		 2140
2141 proxy->common.offset = 0x0;
2142 proxy->common.size = 0x1000;
2143 proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;
2144
2145 proxy->isr.offset = 0x1000;
2146 proxy->isr.size = 0x1000;
2147 proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;
2148
2149 proxy->device.offset = 0x2000;
2150 proxy->device.size = 0x1000;
2151 proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;
2152
2153 proxy->notify.offset = 0x3000;
d9997d89 2154 proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;
b6ce27a5
GH		 2155 proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
2156
9824d2a3
JW		 2157 proxy->notify_pio.offset = 0x0;
2158 proxy->notify_pio.size = 0x4;
2159 proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
2160
b6ce27a5
GH		 2161 /* subclasses can enforce modern, so do this unconditionally */
2162 memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",
d9997d89
MA		 2163 /* PCI BAR regions must be powers of 2 */
2164 pow2ceil(proxy->notify.offset + proxy->notify.size));
b6ce27a5 2165
dd56040d
DDAG		 2166 if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {
2167 proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
2168 }
2169
2170 if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {
2171 error_setg(errp, "device cannot work as neither modern nor legacy mode"
2172 " is enabled");
2173 error_append_hint(errp, "Set either disable-modern or disable-legacy"
2174 " to off\n");
2175 return;
3eff3769
GK		 2176 }
2177
9a4c0e22 2178 if (pcie_port && pci_is_express(pci_dev)) {
1811e64c 2179 int pos;
06e97442 2180 uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
1811e64c 2181
1811e64c
MA		 2182 pos = pcie_endpoint_cap_init(pci_dev, 0);
2183 assert(pos > 0);
2184
9a7c2a59
MZ		 2185 pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
2186 PCI_PM_SIZEOF, errp);
2187 if (pos < 0) {
2188 return;
2189 }
2190
27ce0f3a 2191 pci_dev->exp.pm_cap = pos;
1811e64c
MA		 2192
2193 /*
2194 * Indicates that this function complies with revision 1.2 of the
2195 * PCI Power Management Interface Specification.
2196 */
2197 pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
615c4ed2 2198
fdfa3b1d
AM		 2199 if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
2200 pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
2201 PCI_ERR_SIZEOF, NULL);
2202 last_pcie_cap_offset += PCI_ERR_SIZEOF;
2203 }
2204
c2cabb34
MA		 2205 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
2206 /* Init error enabling flags */
2207 pcie_cap_deverr_init(pci_dev);
2208 }
2209
d584f1b9
MA		 2210 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
2211 /* Init Link Control Register */
2212 pcie_cap_lnkctl_init(pci_dev);
2213 }
2214
27ce0f3a
MA		 2215 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
2216 /* Init Power Management Control Register */
2217 pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
2218 PCI_PM_CTRL_STATE_MASK);
2219 }
2220
615c4ed2 2221 if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
d83f46d1
JW		 2222 pcie_ats_init(pci_dev, last_pcie_cap_offset,
2223 proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED);
06e97442 2224 last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
615c4ed2
JW		 2225 }
2226
eb1556c4
JS		 2227 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
2228 /* Set Function Level Reset capability bit */
2229 pcie_cap_flr_init(pci_dev);
2230 }
0560b0e9
SL		 2231 } else {
2232 /*
2233 * make future invocations of pci_is_express() return false
2234 * and pci_config_size() return PCI_CONFIG_SPACE_SIZE.
2235 */
2236 pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
1811e64c
MA		 2237 }
2238
b6ce27a5 2239 virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
fc079951 2240 if (k->realize) {
b6ce27a5 2241 k->realize(proxy, errp);
085bccb7 2242 }
085bccb7
FK		 2243}
2244
2245static void virtio_pci_exit(PCIDevice *pci_dev)
2246{
fdfa3b1d
AM		 2247 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
2248 bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
2249 !pci_bus_is_root(pci_get_bus(pci_dev));
2250
8b81bb3b 2251 msix_uninit_exclusive_bar(pci_dev);
fdfa3b1d
AM		 2252 if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
2253 pci_is_express(pci_dev)) {
2254 pcie_aer_exit(pci_dev);
2255 }
085bccb7
FK		 2256}
2257
59ccd20a 2258static void virtio_pci_reset(DeviceState *qdev)
085bccb7
FK		 2259{
2260 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
2261 VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
393f04d3
JW		 2262 int i;
2263
085bccb7
FK		 2264 virtio_bus_reset(bus);
2265 msix_unuse_all_vectors(&proxy->pci_dev);
393f04d3
JW		 2266
2267 for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
2268 proxy->vqs[i].enabled = 0;
805d782d 2269 proxy->vqs[i].reset = 0;
60a8d802
JW		 2270 proxy->vqs[i].num = 0;
2271 proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0;
2272 proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
2273 proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
393f04d3 2274 }
9afb4177
MT		 2275}
2276
54da4183 2277static void virtio_pci_bus_reset_hold(Object *obj)
9afb4177 2278{
54da4183
PM		 2279 PCIDevice *dev = PCI_DEVICE(obj);
2280 DeviceState *qdev = DEVICE(obj);
9afb4177
MT		 2281
2282 virtio_pci_reset(qdev);
c2cabb34
MA		 2283
2284 if (pci_is_express(dev)) {
2285 pcie_cap_deverr_reset(dev);
d584f1b9 2286 pcie_cap_lnkctl_reset(dev);
27ce0f3a
MA		 2287
2288 pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
c2cabb34 2289 }
085bccb7
FK		 2290}
2291
85d1277e 2292static Property virtio_pci_properties[] = {
68a27b20
MT		 2293 DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
2294 VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
a6df8adf
JW		 2295 DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
2296 VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
9824d2a3
JW		 2297 DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
2298 VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
1811e64c
MA		 2299 DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
2300 VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
d9997d89
MA		 2301 DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
2302 VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
66d1c4c1
MC		 2303 DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
2304 ignore_backend_features, false),
615c4ed2
JW		 2305 DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
2306 VIRTIO_PCI_FLAG_ATS_BIT, false),
d83f46d1
JW		 2307 DEFINE_PROP_BIT("x-ats-page-aligned", VirtIOPCIProxy, flags,
2308 VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, true),
c2cabb34
MA		 2309 DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
2310 VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
d584f1b9
MA		 2311 DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
2312 VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
27ce0f3a
MA		 2313 DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
2314 VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
eb1556c4
JS		 2315 DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
2316 VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
fdfa3b1d
AM		 2317 DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
2318 VIRTIO_PCI_FLAG_AER_BIT, false),
85d1277e
ML		 2319 DEFINE_PROP_END_OF_LIST(),
2320};
2321
0560b0e9
SL		 2322static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
2323{
2324 VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);
2325 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
2326 PCIDevice *pci_dev = &proxy->pci_dev;
2327
2328 if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
9a4c0e22 2329 virtio_pci_modern(proxy)) {
0560b0e9
SL		 2330 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2331 }
2332
2333 vpciklass->parent_dc_realize(qdev, errp);
2334}
2335
085bccb7
FK		 2336static void virtio_pci_class_init(ObjectClass *klass, void *data)
2337{
2338 DeviceClass *dc = DEVICE_CLASS(klass);
2339 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
0560b0e9 2340 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
54da4183 2341 ResettableClass *rc = RESETTABLE_CLASS(klass);
085bccb7 2342
4f67d30b 2343 device_class_set_props(dc, virtio_pci_properties);
fc079951 2344 k->realize = virtio_pci_realize;
085bccb7
FK		 2345 k->exit = virtio_pci_exit;
2346 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2347 k->revision = VIRTIO_PCI_ABI_VERSION;
2348 k->class_id = PCI_CLASS_OTHERS;
bf853881
PMD		 2349 device_class_set_parent_realize(dc, virtio_pci_dc_realize,
2350 &vpciklass->parent_dc_realize);
54da4183 2351 rc->phases.hold = virtio_pci_bus_reset_hold;
085bccb7
FK		 2352}
2353
2354static const TypeInfo virtio_pci_info = {
2355 .name = TYPE_VIRTIO_PCI,
2356 .parent = TYPE_PCI_DEVICE,
2357 .instance_size = sizeof(VirtIOPCIProxy),
2358 .class_init = virtio_pci_class_init,
2359 .class_size = sizeof(VirtioPCIClass),
2360 .abstract = true,
2361};
2362
a4ee4c8b
EH		 2363static Property virtio_pci_generic_properties[] = {
2364 DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy,
2365 ON_OFF_AUTO_AUTO),
2366 DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false),
2367 DEFINE_PROP_END_OF_LIST(),
2368};
2369
2370static void virtio_pci_base_class_init(ObjectClass *klass, void *data)
2371{
2372 const VirtioPCIDeviceTypeInfo *t = data;
2373 if (t->class_init) {
2374 t->class_init(klass, NULL);
2375 }
2376}
2377
2378static void virtio_pci_generic_class_init(ObjectClass *klass, void *data)
2379{
2380 DeviceClass *dc = DEVICE_CLASS(klass);
2381
4f67d30b 2382 device_class_set_props(dc, virtio_pci_generic_properties);
a4ee4c8b
EH		 2383}
2384
a4ee4c8b
EH		 2385static void virtio_pci_transitional_instance_init(Object *obj)
2386{
2387 VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
2388
2389 proxy->disable_legacy = ON_OFF_AUTO_OFF;
2390 proxy->disable_modern = false;
2391}
2392
2393static void virtio_pci_non_transitional_instance_init(Object *obj)
2394{
2395 VirtIOPCIProxy *proxy = VIRTIO_PCI(obj);
2396
2397 proxy->disable_legacy = ON_OFF_AUTO_ON;
2398 proxy->disable_modern = false;
2399}
2400
2401void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t)
2402{
683c1d89 2403 char *base_name = NULL;
a4ee4c8b
EH		 2404 TypeInfo base_type_info = {
2405 .name = t->base_name,
2406 .parent = t->parent ? t->parent : TYPE_VIRTIO_PCI,
2407 .instance_size = t->instance_size,
2408 .instance_init = t->instance_init,
8ea90ee6 2409 .class_size = t->class_size,
a4ee4c8b 2410 .abstract = true,
1e33b513 2411 .interfaces = t->interfaces,
a4ee4c8b
EH		 2412 };
2413 TypeInfo generic_type_info = {
2414 .name = t->generic_name,
2415 .parent = base_type_info.name,
2416 .class_init = virtio_pci_generic_class_init,
2417 .interfaces = (InterfaceInfo[]) {
2418 { INTERFACE_PCIE_DEVICE },
2419 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2420 { }
2421 },
2422 };
2423
2424 if (!base_type_info.name) {
2425 /* No base type -> register a single generic device type */
683c1d89
MAL		 2426 /* use intermediate %s-base-type to add generic device props */
2427 base_name = g_strdup_printf("%s-base-type", t->generic_name);
2428 base_type_info.name = base_name;
2429 base_type_info.class_init = virtio_pci_generic_class_init;
2430
2431 generic_type_info.parent = base_name;
2432 generic_type_info.class_init = virtio_pci_base_class_init;
2433 generic_type_info.class_data = (void *)t;
2434
a4ee4c8b
EH		 2435 assert(!t->non_transitional_name);
2436 assert(!t->transitional_name);
683c1d89
MAL		 2437 } else {
2438 base_type_info.class_init = virtio_pci_base_class_init;
2439 base_type_info.class_data = (void *)t;
a4ee4c8b
EH		 2440 }
2441
2442 type_register(&base_type_info);
2443 if (generic_type_info.name) {
2444 type_register(&generic_type_info);
2445 }
2446
2447 if (t->non_transitional_name) {
2448 const TypeInfo non_transitional_type_info = {
2449 .name = t->non_transitional_name,
2450 .parent = base_type_info.name,
2451 .instance_init = virtio_pci_non_transitional_instance_init,
2452 .interfaces = (InterfaceInfo[]) {
2453 { INTERFACE_PCIE_DEVICE },
2454 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2455 { }
2456 },
2457 };
2458 type_register(&non_transitional_type_info);
2459 }
2460
2461 if (t->transitional_name) {
2462 const TypeInfo transitional_type_info = {
2463 .name = t->transitional_name,
2464 .parent = base_type_info.name,
2465 .instance_init = virtio_pci_transitional_instance_init,
2466 .interfaces = (InterfaceInfo[]) {
2467 /*
2468 * Transitional virtio devices work only as Conventional PCI
2469 * devices because they require PIO ports.
2470 */
2471 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2472 { }
2473 },
2474 };
2475 type_register(&transitional_type_info);
2476 }
683c1d89 2477 g_free(base_name);
a4ee4c8b
EH		 2478}
2479
1436f32a
SH		 2480unsigned virtio_pci_optimal_num_queues(unsigned fixed_queues)
2481{
2482 /*
2483 * 1:1 vq to vCPU mapping is ideal because the same vCPU that submitted
2484 * virtqueue buffers can handle their completion. When a different vCPU
2485 * handles completion it may need to IPI the vCPU that submitted the
2486 * request and this adds overhead.
2487 *
2488 * Virtqueues consume guest RAM and MSI-X vectors. This is wasteful in
2489 * guests with very many vCPUs and a device that is only used by a few
2490 * vCPUs. Unfortunately optimizing that case requires manual pinning inside
2491 * the guest, so those users might as well manually set the number of
2492 * queues. There is no upper limit that can be applied automatically and
2493 * doing so arbitrarily would result in a sudden performance drop once the
2494 * threshold number of vCPUs is exceeded.
2495 */
2496 unsigned num_queues = current_machine->smp.cpus;
2497
2498 /*
2499 * The maximum number of MSI-X vectors is PCI_MSIX_FLAGS_QSIZE + 1, but the
2500 * config change interrupt and the fixed virtqueues must be taken into
2501 * account too.
2502 */
2503 num_queues = MIN(num_queues, PCI_MSIX_FLAGS_QSIZE - fixed_queues);
2504
2505 /*
2506 * There is a limit to how many virtqueues a device can have.
2507 */
2508 return MIN(num_queues, VIRTIO_QUEUE_MAX - fixed_queues);
2509}
2510
0a2acf5e
FK		 2511/* virtio-pci-bus */
2512
ac7af112
AF		 2513static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
2514 VirtIOPCIProxy *dev)
0a2acf5e
FK		 2515{
2516 DeviceState *qdev = DEVICE(dev);
f4dd69aa
FK		 2517 char virtio_bus_name[] = "virtio-bus";
2518
d637e1dc 2519 qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name);
0a2acf5e
FK		 2520}
2521
2522static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
2523{
2524 BusClass *bus_class = BUS_CLASS(klass);
2525 VirtioBusClass *k = VIRTIO_BUS_CLASS(klass);
2526 bus_class->max_dev = 1;
2527 k->notify = virtio_pci_notify;
2528 k->save_config = virtio_pci_save_config;
2529 k->load_config = virtio_pci_load_config;
2530 k->save_queue = virtio_pci_save_queue;
2531 k->load_queue = virtio_pci_load_queue;
a6df8adf
JW		 2532 k->save_extra_state = virtio_pci_save_extra_state;
2533 k->load_extra_state = virtio_pci_load_extra_state;
2534 k->has_extra_state = virtio_pci_has_extra_state;
0a2acf5e 2535 k->query_guest_notifiers = virtio_pci_query_guest_notifiers;
0a2acf5e 2536 k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
6f80e617 2537 k->set_host_notifier_mr = virtio_pci_set_host_notifier_mr;
0a2acf5e 2538 k->vmstate_change = virtio_pci_vmstate_change;
d1b4259f 2539 k->pre_plugged = virtio_pci_pre_plugged;
085bccb7 2540 k->device_plugged = virtio_pci_device_plugged;
06a13073 2541 k->device_unplugged = virtio_pci_device_unplugged;
e0d686bf 2542 k->query_nvectors = virtio_pci_query_nvectors;
8e93cef1 2543 k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled;
9f06e71a 2544 k->ioeventfd_assign = virtio_pci_ioeventfd_assign;
8607f5c3 2545 k->get_dma_as = virtio_pci_get_dma_as;
3d1e5d86 2546 k->iommu_enabled = virtio_pci_iommu_enabled;
f19bcdfe 2547 k->queue_enabled = virtio_pci_queue_enabled;
0a2acf5e
FK		 2548}
2549
2550static const TypeInfo virtio_pci_bus_info = {
2551 .name = TYPE_VIRTIO_PCI_BUS,
2552 .parent = TYPE_VIRTIO_BUS,
2553 .instance_size = sizeof(VirtioPCIBusState),
74ded8b4 2554 .class_size = sizeof(VirtioPCIBusClass),
0a2acf5e
FK		 2555 .class_init = virtio_pci_bus_class_init,
2556};
2557
83f7d43a 2558static void virtio_pci_register_types(void)
53c25cea 2559{
a4ee4c8b
EH		 2560 /* Base types: */
2561 type_register_static(&virtio_pci_bus_info);
2562 type_register_static(&virtio_pci_info);
53c25cea
PB		 2563}
2564
83f7d43a 2565type_init(virtio_pci_register_types)
271458d7 2566
Mirror of https://git.qemu.org/git/qemu.git