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Commit | Line | Data |
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9dd986cc RJ |
1 | /* |
2 | * Virtual hardware watchdog. | |
3 | * | |
4 | * Copyright (C) 2009 Red Hat Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
9dd986cc RJ |
18 | * |
19 | * By Richard W.M. Jones (rjones@redhat.com). | |
20 | */ | |
21 | ||
0430891c | 22 | #include "qemu/osdep.h" |
9dd986cc | 23 | |
0b8fa32f | 24 | #include "qemu/module.h" |
1de7afc9 | 25 | #include "qemu/timer.h" |
0d09e41a | 26 | #include "sysemu/watchdog.h" |
83c9f4ca | 27 | #include "hw/pci/pci.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
db1015e9 | 29 | #include "qom/object.h" |
9dd986cc RJ |
30 | |
31 | /*#define I6300ESB_DEBUG 1*/ | |
32 | ||
33 | #ifdef I6300ESB_DEBUG | |
34 | #define i6300esb_debug(fs,...) \ | |
35 | fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__) | |
36 | #else | |
37 | #define i6300esb_debug(fs,...) | |
38 | #endif | |
39 | ||
9dd986cc RJ |
40 | /* PCI configuration registers */ |
41 | #define ESB_CONFIG_REG 0x60 /* Config register */ | |
42 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ | |
43 | ||
44 | /* Memory mapped registers (offset from base address) */ | |
45 | #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */ | |
46 | #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */ | |
47 | #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */ | |
48 | #define ESB_RELOAD_REG 0x0c /* Reload register */ | |
49 | ||
50 | /* Lock register bits */ | |
51 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ | |
52 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ | |
53 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ | |
54 | ||
55 | /* Config register bits */ | |
56 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ | |
57 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ | |
58 | #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ | |
59 | ||
60 | /* Reload register bits */ | |
61 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ | |
62 | ||
63 | /* Magic constants */ | |
64 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | |
65 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ | |
66 | ||
67 | /* Device state. */ | |
68 | struct I6300State { | |
9d472d51 | 69 | PCIDevice dev; |
d9c6ebd1 | 70 | MemoryRegion io_mem; |
9dd986cc RJ |
71 | |
72 | int reboot_enabled; /* "Reboot" on timer expiry. The real action | |
73 | * performed depends on the -watchdog-action | |
74 | * param passed on QEMU command line. | |
75 | */ | |
76 | int clock_scale; /* Clock scale. */ | |
77 | #define CLOCK_SCALE_1KHZ 0 | |
78 | #define CLOCK_SCALE_1MHZ 1 | |
79 | ||
80 | int int_type; /* Interrupt type generated. */ | |
81 | #define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */ | |
82 | #define INT_TYPE_SMI 2 | |
83 | #define INT_TYPE_DISABLED 3 | |
84 | ||
85 | int free_run; /* If true, reload timer on expiry. */ | |
86 | int locked; /* If true, enabled field cannot be changed. */ | |
87 | int enabled; /* If true, watchdog is enabled. */ | |
88 | ||
89 | QEMUTimer *timer; /* The actual watchdog timer. */ | |
90 | ||
91 | uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */ | |
92 | uint32_t timer2_preload; | |
93 | int stage; /* Stage (1 or 2). */ | |
94 | ||
95 | int unlock_state; /* Guest writes 0x80, 0x86 to unlock the | |
96 | * registers, and we transition through | |
97 | * states 0 -> 1 -> 2 when this happens. | |
98 | */ | |
99 | ||
100 | int previous_reboot_flag; /* If the watchdog caused the previous | |
101 | * reboot, this flag will be set. | |
102 | */ | |
103 | }; | |
104 | ||
105 | typedef struct I6300State I6300State; | |
106 | ||
41fc9050 GA |
107 | #define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb" |
108 | #define WATCHDOG_I6300ESB_DEVICE(obj) \ | |
109 | OBJECT_CHECK(I6300State, (obj), TYPE_WATCHDOG_I6300ESB_DEVICE) | |
110 | ||
9dd986cc RJ |
111 | /* This function is called when the watchdog has either been enabled |
112 | * (hence it starts counting down) or has been keep-alived. | |
113 | */ | |
114 | static void i6300esb_restart_timer(I6300State *d, int stage) | |
115 | { | |
116 | int64_t timeout; | |
117 | ||
118 | if (!d->enabled) | |
119 | return; | |
120 | ||
121 | d->stage = stage; | |
122 | ||
123 | if (d->stage <= 1) | |
124 | timeout = d->timer1_preload; | |
125 | else | |
126 | timeout = d->timer2_preload; | |
127 | ||
128 | if (d->clock_scale == CLOCK_SCALE_1KHZ) | |
129 | timeout <<= 15; | |
130 | else | |
131 | timeout <<= 5; | |
132 | ||
9491e9bc LV |
133 | /* Get the timeout in nanoseconds. */ |
134 | ||
135 | timeout = timeout * 30; /* on a PCI bus, 1 tick is 30 ns*/ | |
9dd986cc RJ |
136 | |
137 | i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout); | |
138 | ||
bc72ad67 | 139 | timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); |
9dd986cc RJ |
140 | } |
141 | ||
142 | /* This is called when the guest disables the watchdog. */ | |
143 | static void i6300esb_disable_timer(I6300State *d) | |
144 | { | |
145 | i6300esb_debug("timer disabled\n"); | |
146 | ||
bc72ad67 | 147 | timer_del(d->timer); |
9dd986cc RJ |
148 | } |
149 | ||
fa82e9c3 | 150 | static void i6300esb_reset(DeviceState *dev) |
9dd986cc | 151 | { |
40021f08 | 152 | PCIDevice *pdev = PCI_DEVICE(dev); |
41fc9050 | 153 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(pdev); |
fa82e9c3 BK |
154 | |
155 | i6300esb_debug("I6300State = %p\n", d); | |
156 | ||
9dd986cc | 157 | i6300esb_disable_timer(d); |
fa82e9c3 | 158 | |
36888c63 RJ |
159 | /* NB: Don't change d->previous_reboot_flag in this function. */ |
160 | ||
fa82e9c3 BK |
161 | d->reboot_enabled = 1; |
162 | d->clock_scale = CLOCK_SCALE_1KHZ; | |
163 | d->int_type = INT_TYPE_IRQ; | |
164 | d->free_run = 0; | |
165 | d->locked = 0; | |
166 | d->enabled = 0; | |
167 | d->timer1_preload = 0xfffff; | |
168 | d->timer2_preload = 0xfffff; | |
169 | d->stage = 1; | |
170 | d->unlock_state = 0; | |
9dd986cc RJ |
171 | } |
172 | ||
173 | /* This function is called when the watchdog expires. Note that | |
174 | * the hardware has two timers, and so expiry happens in two stages. | |
175 | * If d->stage == 1 then we perform the first stage action (usually, | |
176 | * sending an interrupt) and then restart the timer again for the | |
177 | * second stage. If the second stage expires then the watchdog | |
178 | * really has run out. | |
179 | */ | |
180 | static void i6300esb_timer_expired(void *vp) | |
181 | { | |
4f423e81 | 182 | I6300State *d = vp; |
9dd986cc RJ |
183 | |
184 | i6300esb_debug("stage %d\n", d->stage); | |
185 | ||
186 | if (d->stage == 1) { | |
187 | /* What to do at the end of stage 1? */ | |
188 | switch (d->int_type) { | |
189 | case INT_TYPE_IRQ: | |
190 | fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n"); | |
191 | break; | |
192 | case INT_TYPE_SMI: | |
193 | fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n"); | |
194 | break; | |
195 | } | |
196 | ||
197 | /* Start the second stage. */ | |
198 | i6300esb_restart_timer(d, 2); | |
199 | } else { | |
200 | /* Second stage expired, reboot for real. */ | |
201 | if (d->reboot_enabled) { | |
202 | d->previous_reboot_flag = 1; | |
203 | watchdog_perform_action(); /* This reboots, exits, etc */ | |
f1114d32 | 204 | i6300esb_reset(DEVICE(d)); |
9dd986cc RJ |
205 | } |
206 | ||
207 | /* In "free running mode" we start stage 1 again. */ | |
208 | if (d->free_run) | |
209 | i6300esb_restart_timer(d, 1); | |
210 | } | |
211 | } | |
212 | ||
213 | static void i6300esb_config_write(PCIDevice *dev, uint32_t addr, | |
214 | uint32_t data, int len) | |
215 | { | |
41fc9050 | 216 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); |
9dd986cc RJ |
217 | int old; |
218 | ||
219 | i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len); | |
220 | ||
221 | if (addr == ESB_CONFIG_REG && len == 2) { | |
222 | d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0; | |
223 | d->clock_scale = | |
224 | (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ; | |
225 | d->int_type = (data & ESB_WDT_INTTYPE); | |
226 | } else if (addr == ESB_LOCK_REG && len == 1) { | |
227 | if (!d->locked) { | |
228 | d->locked = (data & ESB_WDT_LOCK) != 0; | |
229 | d->free_run = (data & ESB_WDT_FUNC) != 0; | |
230 | old = d->enabled; | |
231 | d->enabled = (data & ESB_WDT_ENABLE) != 0; | |
232 | if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ | |
233 | i6300esb_restart_timer(d, 1); | |
234 | else if (!d->enabled) | |
235 | i6300esb_disable_timer(d); | |
236 | } | |
237 | } else { | |
238 | pci_default_write_config(dev, addr, data, len); | |
239 | } | |
240 | } | |
241 | ||
242 | static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len) | |
243 | { | |
41fc9050 | 244 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); |
9dd986cc RJ |
245 | uint32_t data; |
246 | ||
247 | i6300esb_debug ("addr = %x, len = %d\n", addr, len); | |
248 | ||
249 | if (addr == ESB_CONFIG_REG && len == 2) { | |
250 | data = | |
251 | (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) | | |
252 | (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) | | |
253 | d->int_type; | |
254 | return data; | |
255 | } else if (addr == ESB_LOCK_REG && len == 1) { | |
256 | data = | |
257 | (d->free_run ? ESB_WDT_FUNC : 0) | | |
258 | (d->locked ? ESB_WDT_LOCK : 0) | | |
259 | (d->enabled ? ESB_WDT_ENABLE : 0); | |
260 | return data; | |
261 | } else { | |
262 | return pci_default_read_config(dev, addr, len); | |
263 | } | |
264 | } | |
265 | ||
a8170e5e | 266 | static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr) |
9dd986cc RJ |
267 | { |
268 | i6300esb_debug ("addr = %x\n", (int) addr); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
a8170e5e | 273 | static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr) |
9dd986cc RJ |
274 | { |
275 | uint32_t data = 0; | |
4f423e81 | 276 | I6300State *d = vp; |
9dd986cc RJ |
277 | |
278 | i6300esb_debug("addr = %x\n", (int) addr); | |
279 | ||
280 | if (addr == 0xc) { | |
281 | /* The previous reboot flag is really bit 9, but there is | |
282 | * a bug in the Linux driver where it thinks it's bit 12. | |
283 | * Set both. | |
284 | */ | |
285 | data = d->previous_reboot_flag ? 0x1200 : 0; | |
286 | } | |
287 | ||
288 | return data; | |
289 | } | |
290 | ||
a8170e5e | 291 | static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr) |
9dd986cc RJ |
292 | { |
293 | i6300esb_debug("addr = %x\n", (int) addr); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
a8170e5e | 298 | static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val) |
9dd986cc | 299 | { |
4f423e81 | 300 | I6300State *d = vp; |
9dd986cc RJ |
301 | |
302 | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); | |
303 | ||
304 | if (addr == 0xc && val == 0x80) | |
305 | d->unlock_state = 1; | |
306 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
307 | d->unlock_state = 2; | |
308 | } | |
309 | ||
a8170e5e | 310 | static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val) |
9dd986cc | 311 | { |
4f423e81 | 312 | I6300State *d = vp; |
9dd986cc RJ |
313 | |
314 | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); | |
315 | ||
316 | if (addr == 0xc && val == 0x80) | |
317 | d->unlock_state = 1; | |
318 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
319 | d->unlock_state = 2; | |
320 | else { | |
321 | if (d->unlock_state == 2) { | |
322 | if (addr == 0xc) { | |
323 | if ((val & 0x100) != 0) | |
324 | /* This is the "ping" from the userspace watchdog in | |
325 | * the guest ... | |
326 | */ | |
327 | i6300esb_restart_timer(d, 1); | |
328 | ||
329 | /* Setting bit 9 resets the previous reboot flag. | |
330 | * There's a bug in the Linux driver where it sets | |
331 | * bit 12 instead. | |
332 | */ | |
333 | if ((val & 0x200) != 0 || (val & 0x1000) != 0) { | |
334 | d->previous_reboot_flag = 0; | |
335 | } | |
336 | } | |
337 | ||
338 | d->unlock_state = 0; | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
a8170e5e | 343 | static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val) |
9dd986cc | 344 | { |
4f423e81 | 345 | I6300State *d = vp; |
9dd986cc RJ |
346 | |
347 | i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val); | |
348 | ||
349 | if (addr == 0xc && val == 0x80) | |
350 | d->unlock_state = 1; | |
351 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
352 | d->unlock_state = 2; | |
353 | else { | |
354 | if (d->unlock_state == 2) { | |
355 | if (addr == 0) | |
356 | d->timer1_preload = val & 0xfffff; | |
357 | else if (addr == 4) | |
358 | d->timer2_preload = val & 0xfffff; | |
359 | ||
360 | d->unlock_state = 0; | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
a821541e PM |
365 | static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size) |
366 | { | |
367 | switch (size) { | |
368 | case 1: | |
369 | return i6300esb_mem_readb(opaque, addr); | |
370 | case 2: | |
371 | return i6300esb_mem_readw(opaque, addr); | |
372 | case 4: | |
373 | return i6300esb_mem_readl(opaque, addr); | |
374 | default: | |
375 | g_assert_not_reached(); | |
376 | } | |
377 | } | |
378 | ||
379 | static void i6300esb_mem_writefn(void *opaque, hwaddr addr, | |
380 | uint64_t value, unsigned size) | |
381 | { | |
382 | switch (size) { | |
383 | case 1: | |
384 | i6300esb_mem_writeb(opaque, addr, value); | |
385 | break; | |
386 | case 2: | |
387 | i6300esb_mem_writew(opaque, addr, value); | |
388 | break; | |
389 | case 4: | |
390 | i6300esb_mem_writel(opaque, addr, value); | |
391 | break; | |
392 | default: | |
393 | g_assert_not_reached(); | |
394 | } | |
395 | } | |
396 | ||
d9c6ebd1 | 397 | static const MemoryRegionOps i6300esb_ops = { |
a821541e PM |
398 | .read = i6300esb_mem_readfn, |
399 | .write = i6300esb_mem_writefn, | |
400 | .valid.min_access_size = 1, | |
401 | .valid.max_access_size = 4, | |
06b82e2d | 402 | .endianness = DEVICE_LITTLE_ENDIAN, |
d9c6ebd1 AK |
403 | }; |
404 | ||
95c90a0e JQ |
405 | static const VMStateDescription vmstate_i6300esb = { |
406 | .name = "i6300esb_wdt", | |
c1990468 MR |
407 | /* With this VMSD's introduction, version_id/minimum_version_id were |
408 | * erroneously set to sizeof(I6300State), causing a somewhat random | |
409 | * version_id to be set for every build. This eventually broke | |
410 | * migration. | |
411 | * | |
d49805ae JQ |
412 | * To correct this without breaking old->new migration for older |
413 | * versions of QEMU, we've set version_id to a value high enough | |
414 | * to exceed all past values of sizeof(I6300State) across various | |
415 | * build environments, and have reset minimum_version_id to 1, | |
416 | * since this VMSD has never changed and thus can accept all past | |
417 | * versions. | |
c1990468 MR |
418 | * |
419 | * For future changes we can treat these values as we normally would. | |
420 | */ | |
421 | .version_id = 10000, | |
422 | .minimum_version_id = 1, | |
d49805ae | 423 | .fields = (VMStateField[]) { |
95c90a0e JQ |
424 | VMSTATE_PCI_DEVICE(dev, I6300State), |
425 | VMSTATE_INT32(reboot_enabled, I6300State), | |
426 | VMSTATE_INT32(clock_scale, I6300State), | |
427 | VMSTATE_INT32(int_type, I6300State), | |
428 | VMSTATE_INT32(free_run, I6300State), | |
429 | VMSTATE_INT32(locked, I6300State), | |
430 | VMSTATE_INT32(enabled, I6300State), | |
e720677e | 431 | VMSTATE_TIMER_PTR(timer, I6300State), |
95c90a0e JQ |
432 | VMSTATE_UINT32(timer1_preload, I6300State), |
433 | VMSTATE_UINT32(timer2_preload, I6300State), | |
434 | VMSTATE_INT32(stage, I6300State), | |
435 | VMSTATE_INT32(unlock_state, I6300State), | |
436 | VMSTATE_INT32(previous_reboot_flag, I6300State), | |
437 | VMSTATE_END_OF_LIST() | |
438 | } | |
439 | }; | |
9dd986cc | 440 | |
9af21dbe | 441 | static void i6300esb_realize(PCIDevice *dev, Error **errp) |
9dd986cc | 442 | { |
41fc9050 | 443 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); |
9dd986cc | 444 | |
fa82e9c3 BK |
445 | i6300esb_debug("I6300State = %p\n", d); |
446 | ||
bc72ad67 | 447 | d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d); |
36888c63 | 448 | d->previous_reboot_flag = 0; |
9dd986cc | 449 | |
22fc860b PB |
450 | memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d, |
451 | "i6300esb", 0x10); | |
e824b2cc | 452 | pci_register_bar(&d->dev, 0, 0, &d->io_mem); |
9dd986cc RJ |
453 | } |
454 | ||
eb7a20a3 LQ |
455 | static void i6300esb_exit(PCIDevice *dev) |
456 | { | |
457 | I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev); | |
458 | ||
459 | timer_del(d->timer); | |
460 | timer_free(d->timer); | |
461 | } | |
462 | ||
9dd986cc RJ |
463 | static WatchdogTimerModel model = { |
464 | .wdt_name = "i6300esb", | |
465 | .wdt_description = "Intel 6300ESB", | |
9dd986cc RJ |
466 | }; |
467 | ||
40021f08 AL |
468 | static void i6300esb_class_init(ObjectClass *klass, void *data) |
469 | { | |
39bffca2 | 470 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
471 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
472 | ||
473 | k->config_read = i6300esb_config_read; | |
474 | k->config_write = i6300esb_config_write; | |
9af21dbe | 475 | k->realize = i6300esb_realize; |
eb7a20a3 | 476 | k->exit = i6300esb_exit; |
40021f08 AL |
477 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
478 | k->device_id = PCI_DEVICE_ID_INTEL_ESB_9; | |
479 | k->class_id = PCI_CLASS_SYSTEM_OTHER; | |
39bffca2 AL |
480 | dc->reset = i6300esb_reset; |
481 | dc->vmsd = &vmstate_i6300esb; | |
125ee0ed | 482 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
40021f08 AL |
483 | } |
484 | ||
8c43a6f0 | 485 | static const TypeInfo i6300esb_info = { |
41fc9050 | 486 | .name = TYPE_WATCHDOG_I6300ESB_DEVICE, |
39bffca2 AL |
487 | .parent = TYPE_PCI_DEVICE, |
488 | .instance_size = sizeof(I6300State), | |
489 | .class_init = i6300esb_class_init, | |
fd3b02c8 EH |
490 | .interfaces = (InterfaceInfo[]) { |
491 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
492 | { }, | |
493 | }, | |
09aaa160 MA |
494 | }; |
495 | ||
83f7d43a | 496 | static void i6300esb_register_types(void) |
9dd986cc RJ |
497 | { |
498 | watchdog_add_model(&model); | |
39bffca2 | 499 | type_register_static(&i6300esb_info); |
9dd986cc | 500 | } |
09aaa160 | 501 | |
83f7d43a | 502 | type_init(i6300esb_register_types) |