[people/ms/u-boot.git] / include / asm-blackfin / config.h

/*
 * config.h - setup common defines for Blackfin boards based on config.h
 *
 * Copyright (c) 2007-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
#define __ASM_BLACKFIN_CONFIG_POST_H__

/* Sanity check CONFIG_BFIN_CPU */
#ifndef CONFIG_BFIN_CPU
# error CONFIG_BFIN_CPU: your board config needs to define this
#endif

#ifndef CONFIG_BFIN_SCRATCH_REG
# define CONFIG_BFIN_SCRATCH_REG retn
#endif

/* Relocation to SDRAM works on all Blackfin boards */
#define CONFIG_RELOC_FIXUP_WORKS

/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
#endif

/* Set default CONFIG_VCO_HZ if need be */
#if !defined(CONFIG_VCO_HZ)
# if (CONFIG_CLKIN_HALF == 0)
#  define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
# else
#  define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
# endif
#endif

/* Set default CONFIG_CCLK_HZ if need be */
#if !defined(CONFIG_CCLK_HZ)
# if (CONFIG_PLL_BYPASS == 0)
#  define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
# else
#  define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
# endif
#endif

/* Set default CONFIG_SCLK_HZ if need be */
#if !defined(CONFIG_SCLK_HZ)
# if (CONFIG_PLL_BYPASS == 0)
#  define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
# else
#  define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
# endif
#endif

/* Since we use these to program PLL registers directly,
 * make sure the values are sane and won't screw us up.
 */
#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
#endif
#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
#endif
#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
#endif

/* Using L1 scratch pad makes sense for everyone by default. */
#ifndef CONFIG_LINUX_CMDLINE_ADDR
# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
#endif
#ifndef CONFIG_LINUX_CMDLINE_SIZE
# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
#endif

/* Set default SPI flash CS to the one we boot from */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
#endif

/* We need envcrc to embed the env into LDRs */
#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
# define CONFIG_BUILD_ENVCRC
#endif

/* Default/common Blackfin memory layout */
#ifndef CONFIG_SYS_SDRAM_BASE
# define CONFIG_SYS_SDRAM_BASE 0
#endif
#ifndef CONFIG_SYS_MAX_RAM_SIZE
# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
# if CONFIG_SYS_MAX_RAM_SIZE
#  define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
# else
#  define CONFIG_SYS_MONITOR_BASE 0
# endif
#endif
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#endif
#ifndef CONFIG_SYS_GBL_DATA_SIZE
# define CONFIG_SYS_GBL_DATA_SIZE (128)
#endif
#ifndef CONFIG_SYS_GBL_DATA_ADDR
# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
#endif
#ifndef CONFIG_STACKBASE
# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
#endif
#ifndef CONFIG_SYS_MEMTEST_START
# define CONFIG_SYS_MEMTEST_START 0
#endif
#ifndef CONFIG_SYS_MEMTEST_END
# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
#endif

/* Check to make sure everything fits in external RAM */
#if CONFIG_SYS_MAX_RAM_SIZE && \
    ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
# error Memory Map does not fit into configuration
#endif

/* Default/common Blackfin environment settings */
#ifndef CONFIG_LOADADDR
# define CONFIG_LOADADDR 0x1000000
#endif
#ifndef CONFIG_SYS_LOAD_ADDR
# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#endif
#ifndef CONFIG_SYS_BOOTM_LEN
# define CONFIG_SYS_BOOTM_LEN 0x4000000
#endif
#ifndef CONFIG_SYS_PROMPT
# define CONFIG_SYS_PROMPT "bfin> "
#endif
#ifndef CONFIG_SYS_CBSIZE
# define CONFIG_SYS_CBSIZE 1024
#endif
#ifndef CONFIG_SYS_BARGSIZE
# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#endif
#ifndef CONFIG_SYS_PBSIZE
# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#endif
#ifndef CONFIG_SYS_MAXARGS
# define CONFIG_SYS_MAXARGS 16
#endif
#if defined(CONFIG_SYS_HZ)
# if (CONFIG_SYS_HZ != 1000)
#  warning "CONFIG_SYS_HZ must always be 1000"
# endif
# undef CONFIG_SYS_HZ
#endif
#define CONFIG_SYS_HZ 1000
#ifndef CONFIG_SYS_BAUDRATE_TABLE
# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif

#endif
Commit	Line	Data
47d41cc3	1	/*
f348ab85	2	* config.h - setup common defines for Blackfin boards based on config.h
47d41cc3	3	*
f348ab85	4	* Copyright (c) 2007-2009 Analog Devices Inc.
47d41cc3	5	*
f348ab85	6	* Licensed under the GPL-2 or later.
47d41cc3 KG	7	*/
47d41cc3 KG	8
f348ab85 MF	9	#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
	10	#define __ASM_BLACKFIN_CONFIG_POST_H__
	11
	12	/* Sanity check CONFIG_BFIN_CPU */
	13	#ifndef CONFIG_BFIN_CPU
	14	# error CONFIG_BFIN_CPU: your board config needs to define this
	15	#endif
	16
9c46e71a MF	17	#ifndef CONFIG_BFIN_SCRATCH_REG
	18	# define CONFIG_BFIN_SCRATCH_REG retn
	19	#endif
	20
370ec734 MF	21	/* Relocation to SDRAM works on all Blackfin boards */
	22	#define CONFIG_RELOC_FIXUP_WORKS
	23
f348ab85 MF	24	/* Make sure the structure is properly aligned */
	25	#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
	26	# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
	27	#endif
	28
	29	/* Set default CONFIG_VCO_HZ if need be */
	30	#if !defined(CONFIG_VCO_HZ)
	31	# if (CONFIG_CLKIN_HALF == 0)
	32	# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
	33	# else
	34	# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
	35	# endif
	36	#endif
	37
	38	/* Set default CONFIG_CCLK_HZ if need be */
	39	#if !defined(CONFIG_CCLK_HZ)
	40	# if (CONFIG_PLL_BYPASS == 0)
	41	# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
	42	# else
	43	# define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
	44	# endif
	45	#endif
	46
	47	/* Set default CONFIG_SCLK_HZ if need be */
	48	#if !defined(CONFIG_SCLK_HZ)
	49	# if (CONFIG_PLL_BYPASS == 0)
	50	# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
	51	# else
	52	# define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
	53	# endif
	54	#endif
	55
	56	/* Since we use these to program PLL registers directly,
	57	* make sure the values are sane and won't screw us up.
	58	*/
	59	#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
	60	# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
	61	#endif
	62	#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
	63	# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
	64	#endif
	65	#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
	66	# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
	67	#endif
	68
	69	/* Using L1 scratch pad makes sense for everyone by default. */
	70	#ifndef CONFIG_LINUX_CMDLINE_ADDR
	71	# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
	72	#endif
	73	#ifndef CONFIG_LINUX_CMDLINE_SIZE
	74	# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
	75	#endif
	76
	77	/* Set default SPI flash CS to the one we boot from */
	78	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
	79	# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
	80	#endif
	81
76d82187 MF	82	/* We need envcrc to embed the env into LDRs */
	83	#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
	84	# define CONFIG_BUILD_ENVCRC
	85	#endif
	86
f348ab85 MF	87	/* Default/common Blackfin memory layout */
	88	#ifndef CONFIG_SYS_SDRAM_BASE
	89	# define CONFIG_SYS_SDRAM_BASE 0
	90	#endif
	91	#ifndef CONFIG_SYS_MAX_RAM_SIZE
	92	# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
	93	#endif
	94	#ifndef CONFIG_SYS_MONITOR_BASE
7527feef MF	95	# if CONFIG_SYS_MAX_RAM_SIZE
	96	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
	97	# else
	98	# define CONFIG_SYS_MONITOR_BASE 0
	99	# endif
f348ab85 MF	100	#endif
	101	#ifndef CONFIG_SYS_MALLOC_BASE
	102	# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
	103	#endif
	104	#ifndef CONFIG_SYS_GBL_DATA_SIZE
	105	# define CONFIG_SYS_GBL_DATA_SIZE (128)
	106	#endif
	107	#ifndef CONFIG_SYS_GBL_DATA_ADDR
	108	# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
	109	#endif
	110	#ifndef CONFIG_STACKBASE
	111	# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
	112	#endif
	113	#ifndef CONFIG_SYS_MEMTEST_START
	114	# define CONFIG_SYS_MEMTEST_START 0
	115	#endif
	116	#ifndef CONFIG_SYS_MEMTEST_END
	117	# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
	118	#endif
	119
	120	/* Check to make sure everything fits in external RAM */
7527feef MF	121	#if CONFIG_SYS_MAX_RAM_SIZE && \
7527feef MF	122	((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
f348ab85 MF	123	# error Memory Map does not fit into configuration
	124	#endif
	125
	126	/* Default/common Blackfin environment settings */
	127	#ifndef CONFIG_LOADADDR
	128	# define CONFIG_LOADADDR 0x1000000
	129	#endif
	130	#ifndef CONFIG_SYS_LOAD_ADDR
	131	# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	132	#endif
	133	#ifndef CONFIG_SYS_BOOTM_LEN
	134	# define CONFIG_SYS_BOOTM_LEN 0x4000000
	135	#endif
	136	#ifndef CONFIG_SYS_PROMPT
	137	# define CONFIG_SYS_PROMPT "bfin> "
	138	#endif
	139	#ifndef CONFIG_SYS_CBSIZE
69a25ce3	140	# define CONFIG_SYS_CBSIZE 1024
f348ab85 MF	141	#endif
	142	#ifndef CONFIG_SYS_BARGSIZE
	143	# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	144	#endif
	145	#ifndef CONFIG_SYS_PBSIZE
	146	# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	147	#endif
	148	#ifndef CONFIG_SYS_MAXARGS
	149	# define CONFIG_SYS_MAXARGS 16
	150	#endif
	151	#if defined(CONFIG_SYS_HZ)
	152	# if (CONFIG_SYS_HZ != 1000)
	153	# warning "CONFIG_SYS_HZ must always be 1000"
	154	# endif
	155	# undef CONFIG_SYS_HZ
	156	#endif
	157	#define CONFIG_SYS_HZ 1000
	158	#ifndef CONFIG_SYS_BAUDRATE_TABLE
	159	# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	160	#endif
47d41cc3 KG	161
47d41cc3 KG	162	#endif