projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 48dbfeab TL |
1 | /* |
| 2 | * ColdFire Internal Memory Map and Defines | |
| 3 | * | |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | #ifndef __IMMAP_H | |
| 27 | #define __IMMAP_H | |
| c883f6ea | 28 | |
| 4a442d31 TL |
29 | #ifdef CONFIG_M5235 |
| 30 | #include <asm/immap_5235.h> | |
| 31 | #include <asm/m5235.h> | |
| 32 | ||
| 33 | #define CFG_FEC0_IOBASE (MMAP_FEC) | |
| 34 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 35 | ||
| 36 | /* Timer */ | |
| 37 | #ifdef CONFIG_MCFTMR | |
| 38 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 39 | #define CFG_TMR_BASE (MMAP_DTMR3) | |
| 40 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) | |
| 41 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) | |
| 42 | #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) | |
| 43 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| 44 | #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ | |
| 45 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) | |
| 46 | #endif | |
| 47 | ||
| 48 | #ifdef CONFIG_MCFPIT | |
| 49 | #define CFG_UDELAY_BASE (MMAP_PIT0) | |
| 50 | #define CFG_PIT_BASE (MMAP_PIT1) | |
| 51 | #define CFG_PIT_PRESCALE (6) | |
| 52 | #endif | |
| 53 | ||
| 54 | #define CFG_INTR_BASE (MMAP_INTC0) | |
| 55 | #define CFG_NUM_IRQS (128) | |
| 56 | #endif /* CONFIG_M5235 */ | |
| 57 | ||
| 56115665 TL |
58 | #ifdef CONFIG_M5249 |
| 59 | #include <asm/immap_5249.h> | |
| 60 | #include <asm/m5249.h> | |
| 61 | ||
| 62 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 63 | ||
| 64 | #define CFG_INTR_BASE (MMAP_INTC) | |
| 65 | #define CFG_NUM_IRQS (64) | |
| 66 | ||
| 67 | /* Timer */ | |
| 68 | #ifdef CONFIG_MCFTMR | |
| 69 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 70 | #define CFG_TMR_BASE (MMAP_DTMR1) | |
| 71 | #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) | |
| 72 | #define CFG_TMRINTR_NO (31) | |
| 73 | #define CFG_TMRINTR_MASK (0x00000400) | |
| 74 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| a1436a84 | 75 | #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) |
| 56115665 TL |
76 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) |
| 77 | #endif | |
| 78 | #endif /* CONFIG_M5249 */ | |
| 79 | ||
| a1436a84 TL |
80 | #ifdef CONFIG_M5253 |
| 81 | #include <asm/immap_5253.h> | |
| 82 | #include <asm/m5249.h> | |
| 83 | #include <asm/m5253.h> | |
| 84 | ||
| 85 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 86 | ||
| 87 | #define CFG_INTR_BASE (MMAP_INTC) | |
| 88 | #define CFG_NUM_IRQS (64) | |
| 89 | ||
| 90 | /* Timer */ | |
| 91 | #ifdef CONFIG_MCFTMR | |
| 92 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 93 | #define CFG_TMR_BASE (MMAP_DTMR1) | |
| 94 | #define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) | |
| 95 | #define CFG_TMRINTR_NO (27) | |
| 96 | #define CFG_TMRINTR_MASK (0x00000400) | |
| 97 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| 98 | #define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) | |
| 99 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) | |
| 100 | #endif | |
| 101 | #endif /* CONFIG_M5253 */ | |
| 102 | ||
| 56115665 TL |
103 | #ifdef CONFIG_M5271 |
| 104 | #include <asm/immap_5271.h> | |
| 105 | #include <asm/m5271.h> | |
| 106 | ||
| 107 | #define CFG_FEC0_IOBASE (MMAP_FEC) | |
| 108 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 109 | ||
| 110 | /* Timer */ | |
| 111 | #ifdef CONFIG_MCFTMR | |
| 112 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 113 | #define CFG_TMR_BASE (MMAP_DTMR3) | |
| 114 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) | |
| 115 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) | |
| 116 | #define CFG_TMRINTR_MASK (INTC_IPRL_INT22) | |
| 117 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| 118 | #define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ | |
| 119 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) | |
| 120 | #endif | |
| 121 | ||
| 122 | #define CFG_INTR_BASE (MMAP_INTC0) | |
| 123 | #define CFG_NUM_IRQS (128) | |
| 124 | #endif /* CONFIG_M5271 */ | |
| 125 | ||
| 126 | #ifdef CONFIG_M5272 | |
| 127 | #include <asm/immap_5272.h> | |
| 128 | #include <asm/m5272.h> | |
| 129 | ||
| 130 | #define CFG_FEC0_IOBASE (MMAP_FEC) | |
| 131 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 132 | ||
| 133 | #define CFG_INTR_BASE (MMAP_INTC) | |
| 134 | #define CFG_NUM_IRQS (64) | |
| 135 | ||
| 136 | /* Timer */ | |
| 137 | #ifdef CONFIG_MCFTMR | |
| 138 | #define CFG_UDELAY_BASE (MMAP_TMR0) | |
| 139 | #define CFG_TMR_BASE (MMAP_TMR3) | |
| 140 | #define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) | |
| 141 | #define CFG_TMRINTR_NO (INT_TMR3) | |
| 142 | #define CFG_TMRINTR_MASK (INT_ISR_INT24) | |
| 143 | #define CFG_TMRINTR_PEND (0) | |
| 144 | #define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) | |
| 145 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) | |
| 146 | #endif | |
| 147 | #endif /* CONFIG_M5272 */ | |
| 148 | ||
| 149 | #ifdef CONFIG_M5282 | |
| 150 | #include <asm/immap_5282.h> | |
| 151 | #include <asm/m5282.h> | |
| 152 | ||
| 153 | #define CFG_FEC0_IOBASE (MMAP_FEC) | |
| 154 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) | |
| 155 | ||
| 156 | #define CFG_INTR_BASE (MMAP_INTC0) | |
| 157 | #define CFG_NUM_IRQS (128) | |
| 158 | ||
| 159 | /* Timer */ | |
| 160 | #ifdef CONFIG_MCFTMR | |
| 161 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 162 | #define CFG_TMR_BASE (MMAP_DTMR3) | |
| 163 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) | |
| 164 | #define CFG_TMRINTR_NO (INT0_LO_DTMR3) | |
| 165 | #define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) | |
| 166 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| 167 | #define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ | |
| 168 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) | |
| 169 | #endif | |
| 170 | #endif /* CONFIG_M5282 */ | |
| 171 | ||
| aa5f1f9d | 172 | #if defined(CONFIG_M5329) || defined(CONFIG_M5373) |
| 48dbfeab TL |
173 | #include <asm/immap_5329.h> |
| 174 | #include <asm/m5329.h> | |
| 175 | ||
| 176 | #define CFG_FEC0_IOBASE (MMAP_FEC) | |
| 177 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) | |
| 178 | #define CFG_MCFRTC_BASE (MMAP_RTC) | |
| 179 | ||
| 180 | /* Timer */ | |
| 181 | #ifdef CONFIG_MCFTMR | |
| 182 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 183 | #define CFG_TMR_BASE (MMAP_DTMR1) | |
| ab77bc54 | 184 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) |
| 48dbfeab TL |
185 | #define CFG_TMRINTR_NO (INT0_HI_DTMR1) |
| 186 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) | |
| ab77bc54 | 187 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) |
| 48dbfeab | 188 | #define CFG_TMRINTR_PRI (6) |
| 99c03c17 | 189 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 48dbfeab TL |
190 | #endif |
| 191 | ||
| 192 | #ifdef CONFIG_MCFPIT | |
| 193 | #define CFG_UDELAY_BASE (MMAP_PIT0) | |
| 194 | #define CFG_PIT_BASE (MMAP_PIT1) | |
| 195 | #define CFG_PIT_PRESCALE (6) | |
| 196 | #endif | |
| 197 | ||
| 198 | #define CFG_INTR_BASE (MMAP_INTC0) | |
| 199 | #define CFG_NUM_IRQS (128) | |
| aa5f1f9d | 200 | #endif /* CONFIG_M5329 && CONFIG_M5373 */ |
| c883f6ea | 201 | |
| 8ae158cd TL |
202 | #ifdef CONFIG_M54455 |
| 203 | #include <asm/immap_5445x.h> | |
| 204 | #include <asm/m5445x.h> | |
| 205 | ||
| 206 | #define CFG_FEC0_IOBASE (MMAP_FEC0) | |
| 207 | #define CFG_FEC1_IOBASE (MMAP_FEC1) | |
| 208 | ||
| 209 | #define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) | |
| 210 | ||
| 211 | #define CFG_MCFRTC_BASE (MMAP_RTC) | |
| 212 | ||
| 213 | /* Timer */ | |
| 214 | #ifdef CONFIG_MCFTMR | |
| 215 | #define CFG_UDELAY_BASE (MMAP_DTMR0) | |
| 216 | #define CFG_TMR_BASE (MMAP_DTMR1) | |
| 217 | #define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) | |
| 218 | #define CFG_TMRINTR_NO (INT0_HI_DTMR1) | |
| 219 | #define CFG_TMRINTR_MASK (INTC_IPRH_INT33) | |
| 220 | #define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) | |
| 221 | #define CFG_TMRINTR_PRI (6) | |
| 222 | #define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) | |
| 223 | #endif | |
| 224 | ||
| 225 | #ifdef CONFIG_MCFPIT | |
| 226 | #define CFG_UDELAY_BASE (MMAP_PIT0) | |
| 227 | #define CFG_PIT_BASE (MMAP_PIT1) | |
| 228 | #define CFG_PIT_PRESCALE (6) | |
| 229 | #endif | |
| 230 | ||
| 231 | #define CFG_INTR_BASE (MMAP_INTC0) | |
| 232 | #define CFG_NUM_IRQS (128) | |
| 233 | ||
| 234 | #ifdef CONFIG_PCI | |
| 2e72ad06 TL |
235 | #define CFG_PCI_BAR0 (CFG_MBAR) |
| 236 | #define CFG_PCI_BAR5 (CFG_SDRAM_BASE) | |
| 237 | #define CFG_PCI_TBATR0 (CFG_MBAR) | |
| 238 | #define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) | |
| 8ae158cd TL |
239 | #endif |
| 240 | #endif /* CONFIG_M54455 */ | |
| 241 | ||
| 48dbfeab | 242 | #endif /* __IMMAP_H */ |