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4a442d31 TL |
1 | /* |
2 | * MCF5329 Internal Memory Map | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __IMMAP_5235__ | |
27 | #define __IMMAP_5235__ | |
28 | ||
6d0f6bcf JCPV |
29 | #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) |
30 | #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) | |
31 | #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) | |
32 | #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) | |
33 | #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) | |
34 | #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) | |
35 | #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) | |
36 | #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) | |
37 | #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) | |
38 | #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) | |
39 | #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) | |
40 | #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) | |
41 | #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) | |
42 | #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) | |
43 | #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) | |
44 | #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) | |
45 | #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) | |
46 | #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) | |
47 | #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) | |
48 | #define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) | |
49 | #define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) | |
50 | #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) | |
51 | #define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) | |
52 | #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) | |
53 | #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) | |
54 | #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) | |
55 | #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) | |
56 | #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) | |
57 | #define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) | |
58 | #define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) | |
59 | #define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) | |
60 | #define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) | |
61 | #define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) | |
62 | #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) | |
63 | #define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) | |
64 | #define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) | |
4a442d31 TL |
65 | |
66 | /* System Control Module register */ | |
67 | typedef struct scm_ctrl { | |
68 | u32 ipsbar; /* 0x00 - MBAR */ | |
69 | u32 res1; /* 0x04 */ | |
70 | u32 rambar; /* 0x08 - RAMBAR */ | |
71 | u32 res2; /* 0x0C */ | |
72 | u8 crsr; /* 0x10 Core Reset Status Register */ | |
73 | u8 cwcr; /* 0x11 Core Watchdog Control Register */ | |
74 | u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ | |
75 | u8 cwsr; /* 0x13 Core Watchdog Service Register */ | |
76 | u32 dmareqc; /* 0x14 */ | |
77 | u32 res3; /* 0x18 */ | |
78 | u32 mpark; /* 0x1C */ | |
79 | u8 mpr; /* 0x20 */ | |
80 | u8 res4[3]; /* 0x21 - 0x23 */ | |
81 | u8 pacr0; /* 0x24 */ | |
82 | u8 pacr1; /* 0x25 */ | |
83 | u8 pacr2; /* 0x26 */ | |
84 | u8 pacr3; /* 0x27 */ | |
85 | u8 pacr4; /* 0x28 */ | |
86 | u32 res5; /* 0x29 */ | |
87 | u8 pacr5; /* 0x2a */ | |
88 | u8 pacr6; /* 0x2b */ | |
89 | u8 pacr7; /* 0x2c */ | |
90 | u32 res6; /* 0x2d */ | |
91 | u8 pacr8; /* 0x2e */ | |
92 | u32 res7; /* 0x2f */ | |
93 | u8 gpacr; /* 0x30 */ | |
94 | u8 res8[3]; /* 0x31 - 0x33 */ | |
95 | } scm_t; | |
96 | ||
97 | /* SDRAM controller registers */ | |
98 | typedef struct sdram_ctrl { | |
99 | u16 dcr; /* 0x00 Control register */ | |
100 | u16 res1[3]; /* 0x02 - 0x07 */ | |
101 | u32 dacr0; /* 0x08 address and control register 0 */ | |
102 | u32 dmr0; /* 0x0C mask register block 0 */ | |
103 | u32 dacr1; /* 0x10 address and control register 1 */ | |
104 | u32 dmr1; /* 0x14 mask register block 1 */ | |
105 | } sdram_t; | |
106 | ||
107 | /* Flexbus module Chip select registers */ | |
108 | typedef struct fbcs_ctrl { | |
109 | u16 csar0; /* 0x00 Chip-Select Address Register 0 */ | |
110 | u16 res0; | |
111 | u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ | |
112 | u16 res1; /* 0x08 */ | |
113 | u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ | |
114 | ||
115 | u16 csar1; /* 0x0C Chip-Select Address Register 1 */ | |
116 | u16 res2; | |
117 | u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ | |
118 | u16 res3; /* 0x14 */ | |
119 | u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ | |
120 | ||
121 | u16 csar2; /* 0x18 Chip-Select Address Register 2 */ | |
122 | u16 res4; | |
123 | u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ | |
124 | u16 res5; /* 0x20 */ | |
125 | u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ | |
126 | ||
127 | u16 csar3; /* 0x24 Chip-Select Address Register 3 */ | |
128 | u16 res6; | |
129 | u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ | |
130 | u16 res7; /* 0x2C */ | |
131 | u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ | |
132 | ||
133 | u16 csar4; /* 0x30 Chip-Select Address Register 4 */ | |
134 | u16 res8; | |
135 | u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ | |
136 | u16 res9; /* 0x38 */ | |
137 | u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ | |
138 | ||
139 | u16 csar5; /* 0x3C Chip-Select Address Register 5 */ | |
140 | u16 res10; | |
141 | u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ | |
142 | u16 res11; /* 0x44 */ | |
143 | u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ | |
144 | ||
145 | u16 csar6; /* 0x48 Chip-Select Address Register 5 */ | |
146 | u16 res12; | |
147 | u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ | |
148 | u16 res13; /* 0x50 */ | |
149 | u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ | |
150 | ||
151 | u16 csar7; /* 0x54 Chip-Select Address Register 5 */ | |
152 | u16 res14; | |
153 | u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ | |
154 | u16 res15; /* 0x5C */ | |
155 | u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ | |
156 | } fbcs_t; | |
157 | ||
158 | /* QSPI module registers */ | |
159 | typedef struct qspi_ctrl { | |
160 | u16 qmr; /* Mode register */ | |
161 | u16 res1; | |
162 | u16 qdlyr; /* Delay register */ | |
163 | u16 res2; | |
164 | u16 qwr; /* Wrap register */ | |
165 | u16 res3; | |
166 | u16 qir; /* Interrupt register */ | |
167 | u16 res4; | |
168 | u16 qar; /* Address register */ | |
169 | u16 res5; | |
170 | u16 qdr; /* Data register */ | |
171 | u16 res6; | |
172 | } qspi_t; | |
173 | ||
174 | /* Interrupt module registers */ | |
175 | typedef struct int0_ctrl { | |
176 | /* Interrupt Controller 0 */ | |
177 | u32 iprh0; /* 0x00 Pending Register High */ | |
178 | u32 iprl0; /* 0x04 Pending Register Low */ | |
179 | u32 imrh0; /* 0x08 Mask Register High */ | |
180 | u32 imrl0; /* 0x0C Mask Register Low */ | |
181 | u32 frch0; /* 0x10 Force Register High */ | |
182 | u32 frcl0; /* 0x14 Force Register Low */ | |
183 | u8 irlr; /* 0x18 */ | |
184 | u8 iacklpr; /* 0x19 */ | |
185 | u16 res1[19]; /* 0x1a - 0x3c */ | |
186 | u8 icr0[64]; /* 0x40 - 0x7F Control registers */ | |
187 | u32 res3[24]; /* 0x80 - 0xDF */ | |
188 | u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ | |
189 | u8 res4[3]; /* 0xE1 - 0xE3 */ | |
190 | u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ | |
191 | u8 res5[3]; /* 0xE5 - 0xE7 */ | |
192 | u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ | |
193 | u8 res6[3]; /* 0xE9 - 0xEB */ | |
194 | u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ | |
195 | u8 res7[3]; /* 0xED - 0xEF */ | |
196 | u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ | |
197 | u8 res8[3]; /* 0xF1 - 0xF3 */ | |
198 | u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ | |
199 | u8 res9[3]; /* 0xF5 - 0xF7 */ | |
200 | u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ | |
201 | u8 resa[3]; /* 0xF9 - 0xFB */ | |
202 | u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ | |
203 | u8 resb[3]; /* 0xFD - 0xFF */ | |
204 | } int0_t; | |
205 | ||
206 | typedef struct int1_ctrl { | |
207 | /* Interrupt Controller 1 */ | |
208 | u32 iprh1; /* 0x00 Pending Register High */ | |
209 | u32 iprl1; /* 0x04 Pending Register Low */ | |
210 | u32 imrh1; /* 0x08 Mask Register High */ | |
211 | u32 imrl1; /* 0x0C Mask Register Low */ | |
212 | u32 frch1; /* 0x10 Force Register High */ | |
213 | u32 frcl1; /* 0x14 Force Register Low */ | |
214 | u8 irlr; /* 0x18 */ | |
215 | u8 iacklpr; /* 0x19 */ | |
216 | u16 res1[19]; /* 0x1a - 0x3c */ | |
217 | u8 icr1[64]; /* 0x40 - 0x7F */ | |
218 | u32 res4[24]; /* 0x80 - 0xDF */ | |
219 | u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ | |
220 | u8 res5[3]; /* 0xE1 - 0xE3 */ | |
221 | u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ | |
222 | u8 res6[3]; /* 0xE5 - 0xE7 */ | |
223 | u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ | |
224 | u8 res7[3]; /* 0xE9 - 0xEB */ | |
225 | u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ | |
226 | u8 res8[3]; /* 0xED - 0xEF */ | |
227 | u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ | |
228 | u8 res9[3]; /* 0xF1 - 0xF3 */ | |
229 | u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ | |
230 | u8 resa[3]; /* 0xF5 - 0xF7 */ | |
231 | u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ | |
232 | u8 resb[3]; /* 0xF9 - 0xFB */ | |
233 | u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ | |
234 | u8 resc[3]; /* 0xFD - 0xFF */ | |
235 | } int1_t; | |
236 | ||
237 | typedef struct intgack_ctrl1 { | |
238 | /* Global IACK Registers */ | |
239 | u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ | |
240 | u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ | |
241 | } intgack_t; | |
242 | ||
243 | /* GPIO port registers */ | |
244 | typedef struct gpio_ctrl { | |
245 | /* Port Output Data Registers */ | |
246 | u8 podr_addr; /* 0x00 */ | |
247 | u8 podr_datah; /* 0x01 */ | |
248 | u8 podr_datal; /* 0x02 */ | |
249 | u8 podr_busctl; /* 0x03 */ | |
250 | u8 podr_bs; /* 0x04 */ | |
251 | u8 podr_cs; /* 0x05 */ | |
252 | u8 podr_sdram; /* 0x06 */ | |
253 | u8 podr_feci2c; /* 0x07 */ | |
254 | u8 podr_uarth; /* 0x08 */ | |
255 | u8 podr_uartl; /* 0x09 */ | |
256 | u8 podr_qspi; /* 0x0A */ | |
257 | u8 podr_timer; /* 0x0B */ | |
258 | u8 podr_etpu; /* 0x0C */ | |
259 | u8 res1[3]; /* 0x0D - 0x0F */ | |
260 | ||
261 | /* Port Data Direction Registers */ | |
262 | u8 pddr_addr; /* 0x10 */ | |
263 | u8 pddr_datah; /* 0x11 */ | |
264 | u8 pddr_datal; /* 0x12 */ | |
265 | u8 pddr_busctl; /* 0x13 */ | |
266 | u8 pddr_bs; /* 0x14 */ | |
267 | u8 pddr_cs; /* 0x15 */ | |
268 | u8 pddr_sdram; /* 0x16 */ | |
269 | u8 pddr_feci2c; /* 0x17 */ | |
270 | u8 pddr_uarth; /* 0x18 */ | |
271 | u8 pddr_uartl; /* 0x19 */ | |
272 | u8 pddr_qspi; /* 0x1A */ | |
273 | u8 pddr_timer; /* 0x1B */ | |
274 | u8 pddr_etpu; /* 0x1C */ | |
275 | u8 res2[3]; /* 0x1D - 0x1F */ | |
276 | ||
277 | /* Port Data Direction Registers */ | |
278 | u8 ppdsdr_addr; /* 0x20 */ | |
279 | u8 ppdsdr_datah; /* 0x21 */ | |
280 | u8 ppdsdr_datal; /* 0x22 */ | |
281 | u8 ppdsdr_busctl; /* 0x23 */ | |
282 | u8 ppdsdr_bs; /* 0x24 */ | |
283 | u8 ppdsdr_cs; /* 0x25 */ | |
284 | u8 ppdsdr_sdram; /* 0x26 */ | |
285 | u8 ppdsdr_feci2c; /* 0x27 */ | |
286 | u8 ppdsdr_uarth; /* 0x28 */ | |
287 | u8 ppdsdr_uartl; /* 0x29 */ | |
288 | u8 ppdsdr_qspi; /* 0x2A */ | |
289 | u8 ppdsdr_timer; /* 0x2B */ | |
290 | u8 ppdsdr_etpu; /* 0x2C */ | |
291 | u8 res3[3]; /* 0x2D - 0x2F */ | |
292 | ||
293 | /* Port Clear Output Data Registers */ | |
294 | u8 pclrr_addr; /* 0x30 */ | |
295 | u8 pclrr_datah; /* 0x31 */ | |
296 | u8 pclrr_datal; /* 0x32 */ | |
297 | u8 pclrr_busctl; /* 0x33 */ | |
298 | u8 pclrr_bs; /* 0x34 */ | |
299 | u8 pclrr_cs; /* 0x35 */ | |
300 | u8 pclrr_sdram; /* 0x36 */ | |
301 | u8 pclrr_feci2c; /* 0x37 */ | |
302 | u8 pclrr_uarth; /* 0x38 */ | |
303 | u8 pclrr_uartl; /* 0x39 */ | |
304 | u8 pclrr_qspi; /* 0x3A */ | |
305 | u8 pclrr_timer; /* 0x3B */ | |
306 | u8 pclrr_etpu; /* 0x3C */ | |
307 | u8 res4[3]; /* 0x3D - 0x3F */ | |
308 | ||
309 | /* Pin Assignment Registers */ | |
310 | u8 par_ad; /* 0x40 */ | |
311 | u8 res5; /* 0x41 */ | |
312 | u16 par_busctl; /* 0x42 */ | |
313 | u8 par_bs; /* 0x44 */ | |
314 | u8 par_cs; /* 0x45 */ | |
315 | u8 par_sdram; /* 0x46 */ | |
316 | u8 par_feci2c; /* 0x47 */ | |
317 | u16 par_uart; /* 0x48 */ | |
318 | u8 par_qspi; /* 0x4A */ | |
319 | u8 res6; /* 0x4B */ | |
320 | u16 par_timer; /* 0x4C */ | |
321 | u8 par_etpu; /* 0x4E */ | |
322 | u8 res7; /* 0x4F */ | |
323 | ||
324 | /* Drive Strength Control Registers */ | |
325 | u8 dscr_eim; /* 0x50 */ | |
326 | u8 dscr_etpu; /* 0x51 */ | |
327 | u8 dscr_feci2c; /* 0x52 */ | |
328 | u8 dscr_uart; /* 0x53 */ | |
329 | u8 dscr_qspi; /* 0x54 */ | |
330 | u8 dscr_timer; /* 0x55 */ | |
331 | u16 res8; /* 0x56 */ | |
332 | } gpio_t; | |
333 | ||
334 | /*Chip configuration module registers */ | |
335 | typedef struct ccm_ctrl { | |
336 | u8 rcr; /* 0x01 */ | |
337 | u8 rsr; /* 0x02 */ | |
338 | u16 res1; /* 0x03 */ | |
339 | u16 ccr; /* 0x04 Chip configuration register */ | |
340 | u16 lpcr; /* 0x06 Low-power Control register */ | |
341 | u16 rcon; /* 0x08 Rreset configuration register */ | |
342 | u16 cir; /* 0x0a Chip identification register */ | |
343 | } ccm_t; | |
344 | ||
345 | /* Clock Module registers */ | |
346 | typedef struct pll_ctrl { | |
347 | u32 syncr; /* 0x00 synthesizer control register */ | |
348 | u32 synsr; /* 0x04 synthesizer status register */ | |
349 | } pll_t; | |
350 | ||
351 | /* Watchdog registers */ | |
352 | typedef struct wdog_ctrl { | |
353 | u16 cr; /* 0x00 Control register */ | |
354 | u16 mr; /* 0x02 Modulus register */ | |
355 | u16 cntr; /* 0x04 Count register */ | |
356 | u16 sr; /* 0x06 Service register */ | |
357 | } wdog_t; | |
358 | ||
359 | /* FlexCan module registers */ | |
360 | typedef struct can_ctrl { | |
361 | u32 mcr; /* 0x00 Module Configuration register */ | |
362 | u32 ctrl; /* 0x04 Control register */ | |
363 | u32 timer; /* 0x08 Free Running Timer */ | |
364 | u32 res1; /* 0x0C */ | |
365 | u32 rxgmask; /* 0x10 Rx Global Mask */ | |
366 | u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ | |
367 | u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ | |
368 | u32 errcnt; /* 0x1C Error Counter Register */ | |
369 | u32 errstat; /* 0x20 Error and status Register */ | |
370 | u32 res2; /* 0x24 */ | |
371 | u32 imask; /* 0x28 Interrupt Mask Register */ | |
372 | u32 res3; /* 0x2C */ | |
373 | u32 iflag; /* 0x30 Interrupt Flag Register */ | |
374 | u32 res4[19]; /* 0x34 - 0x7F */ | |
375 | u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ | |
376 | } can_t; | |
377 | ||
378 | #endif /* __IMMAP_5235__ */ |