[people/ms/u-boot.git] / include / asm-m68k / immap_5275.h

/*
 * MCF5274/5 Internal Memory Map
 *
 * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
 * Based on work Copyright (c) 2003 Josef Baumgartner
 *                                  <josef.baumgartner@telex.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __IMMAP_5275__
#define __IMMAP_5275__

#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00001000)
#define MMAP_FEC0FIFO	(CONFIG_SYS_MBAR + 0x00001400)
#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00001800)
#define MMAP_FEC1FIFO	(CONFIG_SYS_MBAR + 0x00001C00)
#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x00110000)
#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110004)
#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
#define MMAP_USB	(CONFIG_SYS_MBAR + 0x001C0000)
#define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)

/* System configuration registers
*/
typedef	struct sys_ctrl {
	u32 ipsbar;
	u32 res1;
	u32 rambar;
	u32 res2;
	u8 crsr;
	u8 cwcr;
	u8 lpicr;
	u8 cwsr;
	u8 res3[8];
	u32 mpark;
	u8 mpr;
	u8 res4[3];
	u8 pacr0;
	u8 pacr1;
	u8 pacr2;
	u8 pacr3;
	u8 pacr4;
	u8 res5;
	u8 pacr5;
	u8 pacr6;
	u8 pacr7;
	u8 res6;
	u8 pacr8;
	u8 res7;
	u8 gpacr;
	u8 res8[3];
} sysctrl_t;
/* SDRAM controller registers, offset: 0x040
 */
typedef struct sdram_ctrl {
	u32 sdmr;
	u32 sdcr;
	u32 sdcfg1;
	u32 sdcfg2;
	u32 sdbar0;
	u32 sdbmr0;
	u32 sdbar1;
	u32 sdbmr1;
} sdramctrl_t;

/* Chip select module registers, offset: 0x080
*/
typedef struct	cs_ctlr {
	u16 ar0;
	u16 res1;
	u32 mr0;
	u16 res2;
	u16 cr0;
	u16 ar1;
	u16 res3;
	u32 mr1;
	u16 res4;
	u16 cr1;
	u16 ar2;
	u16 res5;
	u32 mr2;
	u16 res6;
	u16 cr2;
	u16 ar3;
	u16 res7;
	u32 mr3;
	u16 res8;
	u16 cr3;
	u16 ar4;
	u16 res9;
	u32 mr4;
	u16 res10;
	u16 cr4;
	u16 ar5;
	u16 res11;
	u32 mr5;
	u16 res12;
	u16 cr5;
	u16 ar6;
	u16 res13;
	u32 mr6;
	u16 res14;
	u16 cr6;
	u16 ar7;
	u16 res15;
	u32 mr7;
	u16 res16;
	u16 cr7;
} csctrl_t;

/* DMA module registers, offset 0x100
 */
typedef struct	dma_ctrl {
	u32 sar;
	u32 dar;
	u32 dsrbcr;
	u32 dcr;
} dma_t;

/* QSPI module registers, offset 0x340
 */
typedef struct	qspi_ctrl {
	u16 qmr;
	u8 res1[2];
	u16 qdlyr;
	u8 res2[2];
	u16 qwr;
	u8 res3[2];
	u16 qir;
	u8 res4[2];
	u16 qar;
	u8 res5[2];
	u16 qdr;
	u8 res6[2];
} qspi_t;

/* Interrupt module registers, offset 0xc00
*/
typedef struct int_ctrl {
	u32 iprh0;
	u32 iprl0;
	u32 imrh0;
	u32 imrl0;
	u32 frch0;
	u32 frcl0;
	u8 irlr;
	u8 iacklpr;
	u8 res1[0x26];
	u8 icr0[64]; /* No ICR0, done this way for readability */
	u8 res2[0x60];
	u8 swiack0;
	u8 res3[3];
	u8 Lniack0_1;
	u8 res4[3];
	u8 Lniack0_2;
	u8 res5[3];
	u8 Lniack0_3;
	u8 res6[3];
	u8 Lniack0_4;
	u8 res7[3];
	u8 Lniack0_5;
	u8 res8[3];
	u8 Lniack0_6;
	u8 res9[3];
	u8 Lniack0_7;
	u8 res10[3];
} int0_t;

/* GPIO port registers
*/
typedef struct	gpio_ctrl {
	/* Port Output Data Registers */
	u8 podr_res1[4];
	u8 podr_busctl;
	u8 podr_addr;
	u8 podr_res2[2];
	u8 podr_cs;
	u8 podr_res3;
	u8 podr_fec0h;
	u8 podr_fec0l;
	u8 podr_feci2c;
	u8 podr_qspi;
	u8 podr_sdram;
	u8 podr_timerh;
	u8 podr_timerl;
	u8 podr_uartl;
	u8 podr_fec1h;
	u8 podr_fec1l;
	u8 podr_bs;
	u8 podr_res4;
	u8 podr_usbh;
	u8 podr_usbl;
	u8 podr_uarth;
	u8 podr_res5[3];
	/* Port Data Direction Registers */
	u8 pddr_res1[4];
	u8 pddr_busctl;
	u8 pddr_addr;
	u8 pddr_res2[2];
	u8 pddr_cs;
	u8 pddr_res3;
	u8 pddr_fec0h;
	u8 pddr_fec0l;
	u8 pddr_feci2c;
	u8 pddr_qspi;
	u8 pddr_sdram;
	u8 pddr_timerh;
	u8 pddr_timerl;
	u8 pddr_uartl;
	u8 pddr_fec1h;
	u8 pddr_fec1l;
	u8 pddr_bs;
	u8 pddr_res4;
	u8 pddr_usbh;
	u8 pddr_usbl;
	u8 pddr_uarth;
	u8 pddr_res5[3];
	/* Port Pin Data/Set Registers */
	u8 ppdsdr_res1[4];
	u8 ppdsdr_busctl;
	u8 ppdsdr_addr;
	u8 ppdsdr_res2[2];
	u8 ppdsdr_cs;
	u8 ppdsdr_res3;
	u8 ppdsdr_fec0h;
	u8 ppdsdr_fec0l;
	u8 ppdsdr_feci2c;
	u8 ppdsdr_qspi;
	u8 ppdsdr_sdram;
	u8 ppdsdr_timerh;
	u8 ppdsdr_timerl;
	u8 ppdsdr_uartl;
	u8 ppdsdr_fec1h;
	u8 ppdsdr_fec1l;
	u8 ppdsdr_bs;
	u8 ppdsdr_res4;
	u8 ppdsdr_usbh;
	u8 ppdsdr_usbl;
	u8 ppdsdr_uarth;
	u8 ppdsdr_res5[3];
	/* Port Clear Output Data Registers */
	u8 pclrr_res1[4];
	u8 pclrr_busctl;
	u8 pclrr_addr;
	u8 pclrr_res2[2];
	u8 pclrr_cs;
	u8 pclrr_res3;
	u8 pclrr_fec0h;
	u8 pclrr_fec0l;
	u8 pclrr_feci2c;
	u8 pclrr_qspi;
	u8 pclrr_sdram;
	u8 pclrr_timerh;
	u8 pclrr_timerl;
	u8 pclrr_uartl;
	u8 pclrr_fec1h;
	u8 pclrr_fec1l;
	u8 pclrr_bs;
	u8 pclrr_res4;
	u8 pclrr_usbh;
	u8 pclrr_usbl;
	u8 pclrr_uarth;
	u8 pclrr_res5[3];
	/* Pin Assignment Registers */
	u8 par_addr;
	u8 par_cs;
	u16 par_busctl;
	u8 par_res1[2];
	u16 par_usb;
	u8 par_fec0hl;
	u8 par_fec1hl;
	u16 par_timer;
	u16 par_uart;
	u16 par_qspi;
	u16 par_sdram;
	u16 par_feci2c;
	u8 par_bs;
	u8 par_res2[3];
} gpio_t;


/* PWM module registers
 */
typedef struct	pwm_ctrl {
	u8 pwcr0;
	u8 res1[3];
	u8 pwcr1;
	u8 res2[3];
	u8 pwcr2;
	u8 res3[7];
	u8 pwwd0;
	u8 res4[3];
	u8 pwwd1;
	u8 res5[3];
	u8 pwwd2;
	u8 res6[7];
} pwm_t;

/* Watchdog registers
 */
typedef struct wdog_ctrl {
	u16 wcr;
	u16 wmr;
	u16 wcntr;
	u16 wsr;
	u8 res4[114];
} wdog_t;

/* USB module registers
*/
typedef struct usb {
	u16 res1;
	u16 fnr;
	u16 res2;
	u16 fnmr;
	u16 res3;
	u16 rfmr;
	u16 res4;
	u16 rfmmr;
	u8 res5[3];
	u8 far;
	u32 asr;
	u32 drr1;
	u32 drr2;
	u16 res6;
	u16 specr;
	u16 res7;
	u16 ep0sr;
	u32 iep0cfg;
	u32 oep0cfg;
	u32 ep1cfg;
	u32 ep2cfg;
	u32 ep3cfg;
	u32 ep4cfg;
	u32 ep5cfg;
	u32 ep6cfg;
	u32 ep7cfg;
	u32 ep0ctl;
	u16 res8;
	u16 ep1ctl;
	u16 res9;
	u16 ep2ctl;
	u16 res10;
	u16 ep3ctl;
	u16 res11;
	u16 ep4ctl;
	u16 res12;
	u16 ep5ctl;
	u16 res13;
	u16 ep6ctl;
	u16 res14;
	u16 ep7ctl;
	u32 ep0isr;
	u16 res15;
	u16 ep1isr;
	u16 res16;
	u16 ep2isr;
	u16 res17;
	u16 ep3isr;
	u16 res18;
	u16 ep4isr;
	u16 res19;
	u16 ep5isr;
	u16 res20;
	u16 ep6isr;
	u16 res21;
	u16 ep7isr;
	u32 ep0imr;
	u16 res22;
	u16 ep1imr;
	u16 res23;
	u16 ep2imr;
	u16 res24;
	u16 ep3imr;
	u16 res25;
	u16 ep4imr;
	u16 res26;
	u16 ep5imr;
	u16 res27;
	u16 ep6imr;
	u16 res28;
	u16 ep7imr;
	u32 ep0dr;
	u32 ep1dr;
	u32 ep2dr;
	u32 ep3dr;
	u32 ep4dr;
	u32 ep5dr;
	u32 ep6dr;
	u32 ep7dr;
	u16 res29;
	u16 ep0dpr;
	u16 res30;
	u16 ep1dpr;
	u16 res31;
	u16 ep2dpr;
	u16 res32;
	u16 ep3dpr;
	u16 res33;
	u16 ep4dpr;
	u16 res34;
	u16 ep5dpr;
	u16 res35;
	u16 ep6dpr;
	u16 res36;
	u16 ep7dpr;
	u8 res37[788];
	u8 cfgram[1024];
} usb_t;

/* PLL module registers
 */
typedef struct pll_ctrl {
	u32 syncr;
	u32 synsr;
} pll_t;

typedef struct rcm {
	u8 rcr;
	u8 rsr;
} rcm_t;

#endif /* __IMMAP_5275__ */
Commit	Line	Data
f71d9d91 MF	1	/*
	2	* MCF5274/5 Internal Memory Map
	3	*
	4	* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
	5	* Based on work Copyright (c) 2003 Josef Baumgartner
	6	* <josef.baumgartner@telex.de>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __IMMAP_5275__
	28	#define __IMMAP_5275__
	29
6d0f6bcf JCPV	30	#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
	31	#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
	32	#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
	33	#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
	34	#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
	35	#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
	36	#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
	37	#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
	38	#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
	39	#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
	40	#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
	41	#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
	42	#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
	43	#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
	44	#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
	45	#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
	46	#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
	47	#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
	48	#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
	49	#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
	50	#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
	51	#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
	52	#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
	53	#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
	54	#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
	55	#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
	56	#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
	57	#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
	58	#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
	59	#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
	60	#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
	61	#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
	62	#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
	63	#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
	64	#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
	65	#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
	66	#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
	67	#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
f71d9d91 MF	68
	69	/* System configuration registers
	70	*/
	71	typedef struct sys_ctrl {
	72	u32 ipsbar;
	73	u32 res1;
	74	u32 rambar;
	75	u32 res2;
	76	u8 crsr;
	77	u8 cwcr;
	78	u8 lpicr;
	79	u8 cwsr;
	80	u8 res3[8];
	81	u32 mpark;
	82	u8 mpr;
	83	u8 res4[3];
	84	u8 pacr0;
	85	u8 pacr1;
	86	u8 pacr2;
	87	u8 pacr3;
	88	u8 pacr4;
	89	u8 res5;
	90	u8 pacr5;
	91	u8 pacr6;
	92	u8 pacr7;
	93	u8 res6;
	94	u8 pacr8;
	95	u8 res7;
	96	u8 gpacr;
	97	u8 res8[3];
	98	} sysctrl_t;
	99	/* SDRAM controller registers, offset: 0x040
	100	*/
	101	typedef struct sdram_ctrl {
	102	u32 sdmr;
	103	u32 sdcr;
	104	u32 sdcfg1;
	105	u32 sdcfg2;
	106	u32 sdbar0;
	107	u32 sdbmr0;
	108	u32 sdbar1;
	109	u32 sdbmr1;
	110	} sdramctrl_t;
	111
	112	/* Chip select module registers, offset: 0x080
	113	*/
	114	typedef struct cs_ctlr {
	115	u16 ar0;
	116	u16 res1;
	117	u32 mr0;
	118	u16 res2;
	119	u16 cr0;
	120	u16 ar1;
	121	u16 res3;
	122	u32 mr1;
	123	u16 res4;
	124	u16 cr1;
	125	u16 ar2;
	126	u16 res5;
	127	u32 mr2;
	128	u16 res6;
	129	u16 cr2;
	130	u16 ar3;
	131	u16 res7;
132	u32 mr3;
133	u16 res8;
134	u16 cr3;
135	u16 ar4;
136	u16 res9;
137	u32 mr4;
138	u16 res10;
139	u16 cr4;
140	u16 ar5;
141	u16 res11;
142	u32 mr5;
143	u16 res12;
144	u16 cr5;
145	u16 ar6;
146	u16 res13;
147	u32 mr6;
148	u16 res14;
149	u16 cr6;
150	u16 ar7;
151	u16 res15;
152	u32 mr7;
153	u16 res16;
154	u16 cr7;
155	} csctrl_t;
156
157	/* DMA module registers, offset 0x100
158	*/
159	typedef struct dma_ctrl {
160	u32 sar;
161	u32 dar;
162	u32 dsrbcr;
163	u32 dcr;
164	} dma_t;
165
166	/* QSPI module registers, offset 0x340
167	*/
168	typedef struct qspi_ctrl {
169	u16 qmr;
170	u8 res1[2];
171	u16 qdlyr;
172	u8 res2[2];
173	u16 qwr;
174	u8 res3[2];
175	u16 qir;
176	u8 res4[2];
177	u16 qar;
178	u8 res5[2];
179	u16 qdr;
180	u8 res6[2];
181	} qspi_t;
182
183	/* Interrupt module registers, offset 0xc00
184	*/
185	typedef struct int_ctrl {
186	u32 iprh0;
187	u32 iprl0;
188	u32 imrh0;
189	u32 imrl0;
190	u32 frch0;
191	u32 frcl0;
192	u8 irlr;
193	u8 iacklpr;
194	u8 res1[0x26];
195	u8 icr0[64]; /* No ICR0, done this way for readability */
196	u8 res2[0x60];
197	u8 swiack0;
198	u8 res3[3];
199	u8 Lniack0_1;
200	u8 res4[3];
201	u8 Lniack0_2;
202	u8 res5[3];
203	u8 Lniack0_3;
204	u8 res6[3];
205	u8 Lniack0_4;
206	u8 res7[3];
207	u8 Lniack0_5;
208	u8 res8[3];
209	u8 Lniack0_6;
210	u8 res9[3];
211	u8 Lniack0_7;
212	u8 res10[3];
213	} int0_t;
214
215	/* GPIO port registers
216	*/
217	typedef struct gpio_ctrl {
218	/* Port Output Data Registers */
219	u8 podr_res1[4];
220	u8 podr_busctl;
221	u8 podr_addr;
222	u8 podr_res2[2];
223	u8 podr_cs;
224	u8 podr_res3;
225	u8 podr_fec0h;
226	u8 podr_fec0l;
227	u8 podr_feci2c;
228	u8 podr_qspi;
229	u8 podr_sdram;
230	u8 podr_timerh;
231	u8 podr_timerl;
232	u8 podr_uartl;
233	u8 podr_fec1h;
234	u8 podr_fec1l;
235	u8 podr_bs;
236	u8 podr_res4;
237	u8 podr_usbh;
238	u8 podr_usbl;
239	u8 podr_uarth;
240	u8 podr_res5[3];
241	/* Port Data Direction Registers */
242	u8 pddr_res1[4];
243	u8 pddr_busctl;
244	u8 pddr_addr;
245	u8 pddr_res2[2];
246	u8 pddr_cs;
247	u8 pddr_res3;
248	u8 pddr_fec0h;
249	u8 pddr_fec0l;
250	u8 pddr_feci2c;
251	u8 pddr_qspi;
252	u8 pddr_sdram;
253	u8 pddr_timerh;
254	u8 pddr_timerl;
255	u8 pddr_uartl;
256	u8 pddr_fec1h;
257	u8 pddr_fec1l;
258	u8 pddr_bs;
259	u8 pddr_res4;
260	u8 pddr_usbh;
261	u8 pddr_usbl;
262	u8 pddr_uarth;
263	u8 pddr_res5[3];
264	/* Port Pin Data/Set Registers */
265	u8 ppdsdr_res1[4];
266	u8 ppdsdr_busctl;
267	u8 ppdsdr_addr;
268	u8 ppdsdr_res2[2];
269	u8 ppdsdr_cs;
270	u8 ppdsdr_res3;
271	u8 ppdsdr_fec0h;
272	u8 ppdsdr_fec0l;
273	u8 ppdsdr_feci2c;
274	u8 ppdsdr_qspi;
275	u8 ppdsdr_sdram;
276	u8 ppdsdr_timerh;
277	u8 ppdsdr_timerl;
278	u8 ppdsdr_uartl;
279	u8 ppdsdr_fec1h;
280	u8 ppdsdr_fec1l;
281	u8 ppdsdr_bs;
282	u8 ppdsdr_res4;
283	u8 ppdsdr_usbh;
284	u8 ppdsdr_usbl;
285	u8 ppdsdr_uarth;
286	u8 ppdsdr_res5[3];
287	/* Port Clear Output Data Registers */
288	u8 pclrr_res1[4];
289	u8 pclrr_busctl;
290	u8 pclrr_addr;
291	u8 pclrr_res2[2];
292	u8 pclrr_cs;
293	u8 pclrr_res3;
294	u8 pclrr_fec0h;
295	u8 pclrr_fec0l;
296	u8 pclrr_feci2c;
297	u8 pclrr_qspi;
298	u8 pclrr_sdram;
299	u8 pclrr_timerh;
300	u8 pclrr_timerl;
301	u8 pclrr_uartl;
302	u8 pclrr_fec1h;
303	u8 pclrr_fec1l;
304	u8 pclrr_bs;
305	u8 pclrr_res4;
306	u8 pclrr_usbh;
307	u8 pclrr_usbl;
308	u8 pclrr_uarth;
309	u8 pclrr_res5[3];
310	/* Pin Assignment Registers */
311	u8 par_addr;
312	u8 par_cs;
313	u16 par_busctl;
314	u8 par_res1[2];
315	u16 par_usb;
316	u8 par_fec0hl;
317	u8 par_fec1hl;
318	u16 par_timer;
319	u16 par_uart;
320	u16 par_qspi;
321	u16 par_sdram;
322	u16 par_feci2c;
323	u8 par_bs;
324	u8 par_res2[3];
325	} gpio_t;
326
327
328	/* PWM module registers
329	*/
330	typedef struct pwm_ctrl {
331	u8 pwcr0;
332	u8 res1[3];
333	u8 pwcr1;
334	u8 res2[3];
335	u8 pwcr2;
336	u8 res3[7];
337	u8 pwwd0;
338	u8 res4[3];
339	u8 pwwd1;
340	u8 res5[3];
341	u8 pwwd2;
342	u8 res6[7];
343	} pwm_t;
344
345	/* Watchdog registers
346	*/
347	typedef struct wdog_ctrl {
348	u16 wcr;
349	u16 wmr;
350	u16 wcntr;
351	u16 wsr;
352	u8 res4[114];
353	} wdog_t;
354
355	/* USB module registers
356	*/
357	typedef struct usb {
358	u16 res1;
359	u16 fnr;
360	u16 res2;
361	u16 fnmr;
362	u16 res3;
363	u16 rfmr;
364	u16 res4;
365	u16 rfmmr;
366	u8 res5[3];
367	u8 far;
368	u32 asr;
369	u32 drr1;
370	u32 drr2;
371	u16 res6;
372	u16 specr;
373	u16 res7;
374	u16 ep0sr;
375	u32 iep0cfg;
376	u32 oep0cfg;
377	u32 ep1cfg;
378	u32 ep2cfg;
379	u32 ep3cfg;
380	u32 ep4cfg;
381	u32 ep5cfg;
382	u32 ep6cfg;
383	u32 ep7cfg;
384	u32 ep0ctl;
385	u16 res8;
386	u16 ep1ctl;
387	u16 res9;
388	u16 ep2ctl;
389	u16 res10;
390	u16 ep3ctl;
391	u16 res11;
392	u16 ep4ctl;
393	u16 res12;
394	u16 ep5ctl;
395	u16 res13;
396	u16 ep6ctl;
397	u16 res14;
398	u16 ep7ctl;
399	u32 ep0isr;
400	u16 res15;
401	u16 ep1isr;
402	u16 res16;
403	u16 ep2isr;
404	u16 res17;
405	u16 ep3isr;
406	u16 res18;
407	u16 ep4isr;
408	u16 res19;
409	u16 ep5isr;
410	u16 res20;
411	u16 ep6isr;
412	u16 res21;
413	u16 ep7isr;
414	u32 ep0imr;
415	u16 res22;
416	u16 ep1imr;
417	u16 res23;
418	u16 ep2imr;
419	u16 res24;
420	u16 ep3imr;
421	u16 res25;
422	u16 ep4imr;
423	u16 res26;
424	u16 ep5imr;
425	u16 res27;
426	u16 ep6imr;
427	u16 res28;
428	u16 ep7imr;
429	u32 ep0dr;
430	u32 ep1dr;
431	u32 ep2dr;
432	u32 ep3dr;
433	u32 ep4dr;
434	u32 ep5dr;
435	u32 ep6dr;
436	u32 ep7dr;
437	u16 res29;
438	u16 ep0dpr;
439	u16 res30;
440	u16 ep1dpr;
441	u16 res31;
442	u16 ep2dpr;
443	u16 res32;
444	u16 ep3dpr;
445	u16 res33;
446	u16 ep4dpr;
447	u16 res34;
448	u16 ep5dpr;
449	u16 res35;
450	u16 ep6dpr;
451	u16 res36;
452	u16 ep7dpr;
453	u8 res37[788];
454	u8 cfgram[1024];
455	} usb_t;
456
457	/* PLL module registers
458	*/
459	typedef struct pll_ctrl {
460	u32 syncr;
461	u32 synsr;
462	} pll_t;
463
464	typedef struct rcm {
465	u8 rcr;
466	u8 rsr;
467	} rcm_t;
468
469	#endif /* __IMMAP_5275__ */