[people/ms/u-boot.git] / include / asm-m68k / m5271.h

/*
 * mcf5271.h -- Definitions for Motorola Coldfire 5271
 *
 * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
 * Based on mcf5272sim.h of uCLinux distribution:
 *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
 *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef	_MCF5271_H_
#define	_MCF5271_H_

#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
#define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
#define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y

#define MCF_FMPLL_SYNCR				0x120000
#define MCF_FMPLL_SYNSR				0x120004
#define MCF_FMPLL_SYNCR_MFD(x)			((x&0x7)<<24)
#define MCF_FMPLL_SYNCR_RFD(x)			((x&0x7)<<19)
#define MCF_FMPLL_SYNSR_LOCK			0x8

#define MCF_WTM_WCR				0x140000
#define MCF_WTM_WCNTR				0x140004
#define MCF_WTM_WSR				0x140006
#define MCF_WTM_WCR_EN				0x0001

#define MCF_RCM_RCR				0x110000
#define MCF_RCM_RCR_FRCRSTOUT			0x40
#define MCF_RCM_RCR_SOFTRST			0x80

#define MCF_GPIO_PAR_AD				0x100040
#define MCF_GPIO_PAR_CS				0x100045
#define MCF_GPIO_PAR_SDRAM			0x100046
#define MCF_GPIO_PAR_FECI2C			0x100047
#define MCF_GPIO_PAR_UART			0x100048

#define MCF_CCM_CIR				0x11000A
#define MCF_CCM_CIR_PRN_MASK			0x3F
#define MCF_CCM_CIR_PIN_LEN			6
#define MCF_CCM_CIR_PIN_MCF5270			0x2e
#define MCF_CCM_CIR_PIN_MCF5271			0x80

#define MCF_GPIO_AD_ADDR23			0x80
#define MCF_GPIO_AD_ADDR22			0x40
#define MCF_GPIO_AD_ADDR21			0x20
#define MCF_GPIO_AD_DATAL			0x01
#define MCF_GPIO_AD_MASK			0xe1

#define MCF_GPIO_PAR_CS_PAR_CS2			0x04

#define MCF_GPIO_SDRAM_CSSDCS_00		0x00	/* CS[3:2] pins: CS3, CS2 */
#define MCF_GPIO_SDRAM_CSSDCS_01		0x40	/* CS[3:2] pins: CS3, SD_CS0 */
#define MCF_GPIO_SDRAM_CSSDCS_10		0x80	/* CS[3:2] pins: SD_CS1, SC2 */
#define MCF_GPIO_SDRAM_CSSDCS_11		0xc0	/* CS[3:2] pins: SD_CS1, SD_CS0 */
#define MCF_GPIO_SDRAM_SDWE			0x20	/* WE pin */
#define MCF_GPIO_SDRAM_SCAS			0x10	/* CAS pin */
#define MCF_GPIO_SDRAM_SRAS			0x08	/* RAS pin */
#define MCF_GPIO_SDRAM_SCKE			0x04	/* CKE pin */
#define MCF_GPIO_SDRAM_SDCS_00			0x00	/* SD_CS[0:1] pins: GPIO, GPIO */
#define MCF_GPIO_SDRAM_SDCS_01			0x01	/* SD_CS[0:1] pins: GPIO, SD_CS0 */
#define MCF_GPIO_SDRAM_SDCS_10			0x02	/* SD_CS[0:1] pins: SD_CS1, GPIO */
#define MCF_GPIO_SDRAM_SDCS_11			0x03	/* SD_CS[0:1] pins: SD_CS1, SD_CS0 */

#define MCF_GPIO_PAR_UART_U0RTS			0x0001
#define MCF_GPIO_PAR_UART_U0CTS			0x0002
#define MCF_GPIO_PAR_UART_U0TXD			0x0004
#define MCF_GPIO_PAR_UART_U0RXD			0x0008
#define MCF_GPIO_PAR_UART_U1RXD_UART1		0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1		0x0300

#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)	(((x)&0x03)<<6)

#define MCF_SDRAMC_DCR				0x000040
#define MCF_SDRAMC_DACR0			0x000048
#define MCF_SDRAMC_DMR0				0x00004C

#define MCF_SDRAMC_DCR_RC(x)			(((x)&0x01FF)<<0)
#define MCF_SDRAMC_DCR_RTIM(x)			(((x)&0x0003)<<9)
#define MCF_SDRAMC_DCR_IS			0x0800
#define MCF_SDRAMC_DCR_COC			0x1000
#define MCF_SDRAMC_DCR_NAM			0x2000

#define MCF_SDRAMC_DACRn_IP			0x00000008
#define MCF_SDRAMC_DACRn_PS(x)			(((x)&0x00000003)<<4)
#define MCF_SDRAMC_DACRn_MRS			0x00000040
#define MCF_SDRAMC_DACRn_CBM(x)			(((x)&0x00000007)<<8)
#define MCF_SDRAMC_DACRn_CASL(x)		(((x)&0x00000003)<<12)
#define MCF_SDRAMC_DACRn_RE			0x00008000
#define MCF_SDRAMC_DACRn_BA(x)			(((x)&0x00003FFF)<<18)

#define MCF_SDRAMC_DMRn_BAM_8M			0x007C0000
#define MCF_SDRAMC_DMRn_BAM_16M			0x00FC0000
#define MCF_SDRAMC_DMRn_V			0x00000001

#define MCFSIM_ICR1				0x000C41

/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0			(0)
#define INT0_LO_EPORT1			(1)
#define INT0_LO_EPORT2			(2)
#define INT0_LO_EPORT3			(3)
#define INT0_LO_EPORT4			(4)
#define INT0_LO_EPORT5			(5)
#define INT0_LO_EPORT6			(6)
#define INT0_LO_EPORT7			(7)
#define INT0_LO_SCM			(8)
#define INT0_LO_DMA0			(9)
#define INT0_LO_DMA1			(10)
#define INT0_LO_DMA2			(11)
#define INT0_LO_DMA3			(12)
#define INT0_LO_UART0			(13)
#define INT0_LO_UART1			(14)
#define INT0_LO_UART2			(15)
#define INT0_LO_RSVD1			(16)
#define INT0_LO_I2C			(17)
#define INT0_LO_QSPI			(18)
#define INT0_LO_DTMR0			(19)
#define INT0_LO_DTMR1			(20)
#define INT0_LO_DTMR2			(21)
#define INT0_LO_DTMR3			(22)
#define INT0_LO_FEC_TXF			(23)
#define INT0_LO_FEC_TXB			(24)
#define INT0_LO_FEC_UN			(25)
#define INT0_LO_FEC_RL			(26)
#define INT0_LO_FEC_RXF			(27)
#define INT0_LO_FEC_RXB			(28)
#define INT0_LO_FEC_MII			(29)
#define INT0_LO_FEC_LC			(30)
#define INT0_LO_FEC_HBERR		(31)
#define INT0_HI_FEC_GRA			(32)
#define INT0_HI_FEC_EBERR		(33)
#define INT0_HI_FEC_BABT		(34)
#define INT0_HI_FEC_BABR		(35)
#define INT0_HI_PIT0			(36)
#define INT0_HI_PIT1			(37)
#define INT0_HI_PIT2			(38)
#define INT0_HI_PIT3			(39)
#define INT0_HI_RNG			(40)
#define INT0_HI_SKHA			(41)
#define INT0_HI_MDHA			(42)
#define INT0_HI_CAN1_BUF0I		(43)
#define INT0_HI_CAN1_BUF1I		(44)
#define INT0_HI_CAN1_BUF2I		(45)
#define INT0_HI_CAN1_BUF3I		(46)
#define INT0_HI_CAN1_BUF4I		(47)
#define INT0_HI_CAN1_BUF5I		(48)
#define INT0_HI_CAN1_BUF6I		(49)
#define INT0_HI_CAN1_BUF7I		(50)
#define INT0_HI_CAN1_BUF8I		(51)
#define INT0_HI_CAN1_BUF9I		(52)
#define INT0_HI_CAN1_BUF10I		(53)
#define INT0_HI_CAN1_BUF11I		(54)
#define INT0_HI_CAN1_BUF12I		(55)
#define INT0_HI_CAN1_BUF13I		(56)
#define INT0_HI_CAN1_BUF14I		(57)
#define INT0_HI_CAN1_BUF15I		(58)
#define INT0_HI_CAN1_ERRINT		(59)
#define INT0_HI_CAN1_BOFFINT		(60)
/* 60-63 Reserved */

/* Bit definitions and macros for INTC_IPRL */
#define INTC_IPRL_INT31			(0x80000000)
#define INTC_IPRL_INT30			(0x40000000)
#define INTC_IPRL_INT29			(0x20000000)
#define INTC_IPRL_INT28			(0x10000000)
#define INTC_IPRL_INT27			(0x08000000)
#define INTC_IPRL_INT26			(0x04000000)
#define INTC_IPRL_INT25			(0x02000000)
#define INTC_IPRL_INT24			(0x01000000)
#define INTC_IPRL_INT23			(0x00800000)
#define INTC_IPRL_INT22			(0x00400000)
#define INTC_IPRL_INT21			(0x00200000)
#define INTC_IPRL_INT20			(0x00100000)
#define INTC_IPRL_INT19			(0x00080000)
#define INTC_IPRL_INT18			(0x00040000)
#define INTC_IPRL_INT17			(0x00020000)
#define INTC_IPRL_INT16			(0x00010000)
#define INTC_IPRL_INT15			(0x00008000)
#define INTC_IPRL_INT14			(0x00004000)
#define INTC_IPRL_INT13			(0x00002000)
#define INTC_IPRL_INT12			(0x00001000)
#define INTC_IPRL_INT11			(0x00000800)
#define INTC_IPRL_INT10			(0x00000400)
#define INTC_IPRL_INT9			(0x00000200)
#define INTC_IPRL_INT8			(0x00000100)
#define INTC_IPRL_INT7			(0x00000080)
#define INTC_IPRL_INT6			(0x00000040)
#define INTC_IPRL_INT5			(0x00000020)
#define INTC_IPRL_INT4			(0x00000010)
#define INTC_IPRL_INT3			(0x00000008)
#define INTC_IPRL_INT2			(0x00000004)
#define INTC_IPRL_INT1			(0x00000002)
#define INTC_IPRL_INT0			(0x00000001)

#endif				/* _MCF5271_H_ */
Commit	Line	Data
3a108ed8 ZL	1	/*
	2	* mcf5271.h -- Definitions for Motorola Coldfire 5271
	3	*
	4	* (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
	5	* Based on mcf5272sim.h of uCLinux distribution:
	6	* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
	7	* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
3a108ed8 ZL	28	#ifndef _MCF5271_H_
	29	#define _MCF5271_H_
	30
6d0f6bcf JCPV	31	#define mbar_readLong(x) ((volatile unsigned long ) (CONFIG_SYS_MBAR + x))
	32	#define mbar_readShort(x) ((volatile unsigned short ) (CONFIG_SYS_MBAR + x))
	33	#define mbar_readByte(x) ((volatile unsigned char ) (CONFIG_SYS_MBAR + x))
	34	#define mbar_writeLong(x,y) ((volatile unsigned long ) (CONFIG_SYS_MBAR + x)) = y
	35	#define mbar_writeShort(x,y) ((volatile unsigned short ) (CONFIG_SYS_MBAR + x)) = y
	36	#define mbar_writeByte(x,y) ((volatile unsigned char ) (CONFIG_SYS_MBAR + x)) = y
3a108ed8 ZL	37
	38	#define MCF_FMPLL_SYNCR 0x120000
	39	#define MCF_FMPLL_SYNSR 0x120004
	40	#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
	41	#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
	42	#define MCF_FMPLL_SYNSR_LOCK 0x8
	43
	44	#define MCF_WTM_WCR 0x140000
	45	#define MCF_WTM_WCNTR 0x140004
	46	#define MCF_WTM_WSR 0x140006
	47	#define MCF_WTM_WCR_EN 0x0001
	48
	49	#define MCF_RCM_RCR 0x110000
	50	#define MCF_RCM_RCR_FRCRSTOUT 0x40
	51	#define MCF_RCM_RCR_SOFTRST 0x80
	52
b4853b77	53	#define MCF_GPIO_PAR_AD 0x100040
3a108ed8 ZL	54	#define MCF_GPIO_PAR_CS 0x100045
	55	#define MCF_GPIO_PAR_SDRAM 0x100046
	56	#define MCF_GPIO_PAR_FECI2C 0x100047
	57	#define MCF_GPIO_PAR_UART 0x100048
	58
363d1d8f BS	59	#define MCF_CCM_CIR 0x11000A
	60	#define MCF_CCM_CIR_PRN_MASK 0x3F
	61	#define MCF_CCM_CIR_PIN_LEN 6
	62	#define MCF_CCM_CIR_PIN_MCF5270 0x2e
	63	#define MCF_CCM_CIR_PIN_MCF5271 0x80
	64
b4853b77 MB	65	#define MCF_GPIO_AD_ADDR23 0x80
	66	#define MCF_GPIO_AD_ADDR22 0x40
	67	#define MCF_GPIO_AD_ADDR21 0x20
	68	#define MCF_GPIO_AD_DATAL 0x01
	69	#define MCF_GPIO_AD_MASK 0xe1
	70
	71	#define MCF_GPIO_PAR_CS_PAR_CS2 0x04
	72
	73	#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
	74	#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
	75	#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
	76	#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
	77	#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
	78	#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
	79	#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
	80	#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
	81	#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
	82	#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
	83	#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
	84	#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
	85
	86	#define MCF_GPIO_PAR_UART_U0RTS 0x0001
	87	#define MCF_GPIO_PAR_UART_U0CTS 0x0002
	88	#define MCF_GPIO_PAR_UART_U0TXD 0x0004
	89	#define MCF_GPIO_PAR_UART_U0RXD 0x0008
	90	#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
	91	#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
3a108ed8	92
56115665	93	#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
3a108ed8 ZL	94
	95	#define MCF_SDRAMC_DCR 0x000040
	96	#define MCF_SDRAMC_DACR0 0x000048
	97	#define MCF_SDRAMC_DMR0 0x00004C
	98
	99	#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
	100	#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
b4853b77 MB	101	#define MCF_SDRAMC_DCR_IS 0x0800
	102	#define MCF_SDRAMC_DCR_COC 0x1000
	103	#define MCF_SDRAMC_DCR_NAM 0x2000
3a108ed8	104
b4853b77	105	#define MCF_SDRAMC_DACRn_IP 0x00000008
3a108ed8	106	#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
b4853b77	107	#define MCF_SDRAMC_DACRn_MRS 0x00000040
3a108ed8 ZL	108	#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
3a108ed8 ZL	109	#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
b4853b77	110	#define MCF_SDRAMC_DACRn_RE 0x00008000
3a108ed8 ZL	111	#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
3a108ed8 ZL	112
b4853b77 MB	113	#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
	114	#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
	115	#define MCF_SDRAMC_DMRn_V 0x00000001
3a108ed8	116
b4853b77	117	#define MCFSIM_ICR1 0x000C41
3a108ed8	118
56115665 TL	119	/*********************************************************************
	120	* Interrupt Controller (INTC)
	121	*********************************************************************/
	122	#define INT0_LO_RSVD0 (0)
	123	#define INT0_LO_EPORT1 (1)
	124	#define INT0_LO_EPORT2 (2)
	125	#define INT0_LO_EPORT3 (3)
	126	#define INT0_LO_EPORT4 (4)
	127	#define INT0_LO_EPORT5 (5)
	128	#define INT0_LO_EPORT6 (6)
	129	#define INT0_LO_EPORT7 (7)
	130	#define INT0_LO_SCM (8)
	131	#define INT0_LO_DMA0 (9)
	132	#define INT0_LO_DMA1 (10)
	133	#define INT0_LO_DMA2 (11)
	134	#define INT0_LO_DMA3 (12)
	135	#define INT0_LO_UART0 (13)
	136	#define INT0_LO_UART1 (14)
	137	#define INT0_LO_UART2 (15)
	138	#define INT0_LO_RSVD1 (16)
	139	#define INT0_LO_I2C (17)
	140	#define INT0_LO_QSPI (18)
	141	#define INT0_LO_DTMR0 (19)
	142	#define INT0_LO_DTMR1 (20)
	143	#define INT0_LO_DTMR2 (21)
	144	#define INT0_LO_DTMR3 (22)
	145	#define INT0_LO_FEC_TXF (23)
	146	#define INT0_LO_FEC_TXB (24)
	147	#define INT0_LO_FEC_UN (25)
	148	#define INT0_LO_FEC_RL (26)
	149	#define INT0_LO_FEC_RXF (27)
	150	#define INT0_LO_FEC_RXB (28)
	151	#define INT0_LO_FEC_MII (29)
	152	#define INT0_LO_FEC_LC (30)
	153	#define INT0_LO_FEC_HBERR (31)
	154	#define INT0_HI_FEC_GRA (32)
	155	#define INT0_HI_FEC_EBERR (33)
	156	#define INT0_HI_FEC_BABT (34)
	157	#define INT0_HI_FEC_BABR (35)
	158	#define INT0_HI_PIT0 (36)
	159	#define INT0_HI_PIT1 (37)
	160	#define INT0_HI_PIT2 (38)
	161	#define INT0_HI_PIT3 (39)
	162	#define INT0_HI_RNG (40)
	163	#define INT0_HI_SKHA (41)
	164	#define INT0_HI_MDHA (42)
	165	#define INT0_HI_CAN1_BUF0I (43)
	166	#define INT0_HI_CAN1_BUF1I (44)
	167	#define INT0_HI_CAN1_BUF2I (45)
	168	#define INT0_HI_CAN1_BUF3I (46)
	169	#define INT0_HI_CAN1_BUF4I (47)
	170	#define INT0_HI_CAN1_BUF5I (48)
	171	#define INT0_HI_CAN1_BUF6I (49)
	172	#define INT0_HI_CAN1_BUF7I (50)
	173	#define INT0_HI_CAN1_BUF8I (51)
	174	#define INT0_HI_CAN1_BUF9I (52)
	175	#define INT0_HI_CAN1_BUF10I (53)
	176	#define INT0_HI_CAN1_BUF11I (54)
	177	#define INT0_HI_CAN1_BUF12I (55)
	178	#define INT0_HI_CAN1_BUF13I (56)
	179	#define INT0_HI_CAN1_BUF14I (57)
	180	#define INT0_HI_CAN1_BUF15I (58)
	181	#define INT0_HI_CAN1_ERRINT (59)
	182	#define INT0_HI_CAN1_BOFFINT (60)
183	/* 60-63 Reserved */
184
185	/* Bit definitions and macros for INTC_IPRL */
186	#define INTC_IPRL_INT31 (0x80000000)
187	#define INTC_IPRL_INT30 (0x40000000)
188	#define INTC_IPRL_INT29 (0x20000000)
189	#define INTC_IPRL_INT28 (0x10000000)
190	#define INTC_IPRL_INT27 (0x08000000)
191	#define INTC_IPRL_INT26 (0x04000000)
192	#define INTC_IPRL_INT25 (0x02000000)
193	#define INTC_IPRL_INT24 (0x01000000)
194	#define INTC_IPRL_INT23 (0x00800000)
195	#define INTC_IPRL_INT22 (0x00400000)
196	#define INTC_IPRL_INT21 (0x00200000)
197	#define INTC_IPRL_INT20 (0x00100000)
198	#define INTC_IPRL_INT19 (0x00080000)
199	#define INTC_IPRL_INT18 (0x00040000)
200	#define INTC_IPRL_INT17 (0x00020000)
201	#define INTC_IPRL_INT16 (0x00010000)
202	#define INTC_IPRL_INT15 (0x00008000)
203	#define INTC_IPRL_INT14 (0x00004000)
204	#define INTC_IPRL_INT13 (0x00002000)
205	#define INTC_IPRL_INT12 (0x00001000)
206	#define INTC_IPRL_INT11 (0x00000800)
207	#define INTC_IPRL_INT10 (0x00000400)
208	#define INTC_IPRL_INT9 (0x00000200)
209	#define INTC_IPRL_INT8 (0x00000100)
210	#define INTC_IPRL_INT7 (0x00000080)
211	#define INTC_IPRL_INT6 (0x00000040)
212	#define INTC_IPRL_INT5 (0x00000020)
213	#define INTC_IPRL_INT4 (0x00000010)
214	#define INTC_IPRL_INT3 (0x00000008)
215	#define INTC_IPRL_INT2 (0x00000004)
216	#define INTC_IPRL_INT1 (0x00000002)
217	#define INTC_IPRL_INT0 (0x00000001)
218
219	#endif /* _MCF5271_H_ */