[people/ms/u-boot.git] / include / asm-ppc / global_data.h

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef	__ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H

#include "asm/types.h"

/*
 * The following data structure is placed in some memory wich is
 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
 * some locked parts of the data cache) to allow for a minimum set of
 * global variables during system initialization (until we have set
 * up the memory controller so that we can use RAM).
 *
 * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
 */

typedef	struct	global_data {
	bd_t		*bd;
	unsigned long	flags;
	unsigned long	baudrate;
	unsigned long	cpu_clk;	/* CPU clock in Hz! */
	unsigned long	bus_clk;
#if defined(CONFIG_8xx)
	unsigned long	brg_clk;
#endif
#if defined(CONFIG_CPM2)
	/* There are many clocks on the MPC8260 - see page 9-5 */
	unsigned long	vco_out;
	unsigned long	cpm_clk;
	unsigned long	scc_clk;
	unsigned long	brg_clk;
#ifdef CONFIG_PCI
	unsigned long	pci_clk;
#endif
#endif
	unsigned long   mem_clk;
#if defined(CONFIG_MPC83XX)
	/* There are other clocks in the MPC83XX */
	u32 csb_clk;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
	u32 tsec1_clk;
	u32 tsec2_clk;
	u32 usbdr_clk;
#endif
#if defined (CONFIG_MPC834X)
	u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
#if defined(CONFIG_MPC8315)
	u32 tdm_clk;
#endif
	u32 core_clk;
	u32 enc_clk;
	u32 lbiu_clk;
	u32 lclk_clk;
	u32 pci_clk;
#if defined(CONFIG_MPC837X)
	u32 pciexp1_clk;
	u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
	u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
	u32  mem_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
	u32 sdhc_clk;
#endif
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
	u32 i2c1_clk;
	u32 i2c2_clk;
#endif
#if defined(CONFIG_QE)
	u32 qe_clk;
	u32 brg_clk;
	uint mp_alloc_base;
	uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined(CONFIG_FSL_LAW)
	u32 used_laws;
#endif
#if defined(CONFIG_MPC5xxx)
	unsigned long	ipb_clk;
	unsigned long	pci_clk;
#endif
#if defined(CONFIG_MPC512X)
	u32 ips_clk;
	u32 csb_clk;
	u32 pci_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
	unsigned long   bExtUart;
	unsigned long   inp_clk;
	unsigned long   pci_clk;
	unsigned long   vco_clk;
	unsigned long   pev_clk;
	unsigned long   flb_clk;
#endif
	phys_size_t	ram_size;	/* RAM size */
	unsigned long	reloc_off;	/* Relocation Offset */
	unsigned long	reset_status;	/* reset status register at boot	*/
#if defined(CONFIG_MPC83XX)
	unsigned long	arbiter_event_attributes;
	unsigned long	arbiter_event_address;
#endif
	unsigned long	env_addr;	/* Address  of Environment struct	*/
	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
	unsigned long	have_console;	/* serial_init() was called		*/
#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
	unsigned int	dp_alloc_base;
	unsigned int	dp_alloc_top;
#endif
#if defined(CONFIG_4xx)
	u32  uart_clk;
#endif /* CONFIG_4xx */
#if defined(CONFIG_SYS_GT_6426x)
	unsigned int	mirror_hack[16];
#endif
#if defined(CONFIG_A3000)	|| \
    defined(CONFIG_HIDDEN_DRAGON)  || \
    defined(CONFIG_MUSENKI)	||  \
    defined(CONFIG_SANDPOINT)
	void *		console_addr;
#endif
#ifdef CONFIG_AMIGAONEG3SE
	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
#endif
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
	unsigned long	fb_base;	/* Base address of framebuffer memory	*/
#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
	unsigned long	post_log_word;  /* Record POST activities */
	unsigned long	post_init_f_time;  /* When post_init_f started */
#endif
#ifdef CONFIG_BOARD_TYPES
	unsigned long	board_type;
#endif
#ifdef CONFIG_MODEM_SUPPORT
	unsigned long do_mdm_init;
	unsigned long be_quiet;
#endif
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
	unsigned long kbd_status;
#endif
#if defined(CONFIG_WD_MAX_RATE)
	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
#endif
	void		**jt;		/* jump table */
} gd_t;

/*
 * Global Data Flags
 */
#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
#define	GD_FLG_POSTFAIL	0x00008		/* Critical POST test failed		*/
#define	GD_FLG_POSTSTOP	0x00010		/* POST seqeunce aborted		*/
#define	GD_FLG_LOGINIT	0x00020		/* Log Buffer has been initialized	*/
#define GD_FLG_DISABLE_CONSOLE	0x00040		/* Disable console (in & out)	 */

#if 1
#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
#else /* We could use plain global data, but the resulting code is bigger */
#define XTRN_DECLARE_GLOBAL_DATA_PTR	extern
#define DECLARE_GLOBAL_DATA_PTR     XTRN_DECLARE_GLOBAL_DATA_PTR \
				    gd_t *gd
#endif

#endif /* __ASM_GBL_DATA_H */
Commit	Line	Data
0157cedb WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __ASM_GBL_DATA_H
	25	#define __ASM_GBL_DATA_H
f046ccd1 EL	26
	27	#include "asm/types.h"
	28
0157cedb WD	29	/*
	30	* The following data structure is placed in some memory wich is
	31	* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
	32	* some locked parts of the data cache) to allow for a minimum set of
	33	* global variables during system initialization (until we have set
	34	* up the memory controller so that we can use RAM).
	35	*
6d0f6bcf	36	* Keep it SMALL and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
0157cedb WD	37	*/
	38
	39	typedef struct global_data {
	40	bd_t *bd;
	41	unsigned long flags;
	42	unsigned long baudrate;
77ff7b74	43	unsigned long cpu_clk; /* CPU clock in Hz! */
0157cedb	44	unsigned long bus_clk;
77ff7b74 BD	45	#if defined(CONFIG_8xx)
	46	unsigned long brg_clk;
	47	#endif
9c4c5ae3	48	#if defined(CONFIG_CPM2)
0157cedb WD	49	/* There are many clocks on the MPC8260 - see page 9-5 */
	50	unsigned long vco_out;
	51	unsigned long cpm_clk;
	52	unsigned long scc_clk;
	53	unsigned long brg_clk;
f2302d44 SR	54	#ifdef CONFIG_PCI
	55	unsigned long pci_clk;
	56	#endif
945af8d7	57	#endif
4c52783b	58	unsigned long mem_clk;
f046ccd1 EL	59	#if defined(CONFIG_MPC83XX)
	60	/* There are other clocks in the MPC83XX */
	61	u32 csb_clk;
03051c3d	62	#if defined(CONFIG_MPC834X) \|\| defined(CONFIG_MPC831X) \|\| defined(CONFIG_MPC837X)
f046ccd1 EL	63	u32 tsec1_clk;
f046ccd1 EL	64	u32 tsec2_clk;
f046ccd1	65	u32 usbdr_clk;
0f253283 SW	66	#endif
	67	#if defined (CONFIG_MPC834X)
	68	u32 usbmph_clk;
3e78a31c	69	#endif /* CONFIG_MPC834X */
c86ef2cd	70	#if defined(CONFIG_MPC8315)
555da617	71	u32 tdm_clk;
03051c3d	72	#endif
5f820439	73	u32 core_clk;
f046ccd1 EL	74	u32 enc_clk;
	75	u32 lbiu_clk;
	76	u32 lclk_clk;
6902df56	77	u32 pci_clk;
03051c3d DL	78	#if defined(CONFIG_MPC837X)
	79	u32 pciexp1_clk;
	80	u32 pciexp2_clk;
555da617 DL	81	#endif
555da617 DL	82	#if defined(CONFIG_MPC837X) \|\| defined(CONFIG_MPC8315)
03051c3d DL	83	u32 sata_clk;
03051c3d DL	84	#endif
da9d4610	85	#if defined(CONFIG_MPC8360)
35cf155c	86	u32 mem_sec_clk;
da9d4610 AF	87	#endif /* CONFIG_MPC8360 */
da9d4610 AF	88	#endif
ef50d6c0 KG	89	#if defined(CONFIG_MPC837X) \|\| defined(CONFIG_MPC8536)
	90	u32 sdhc_clk;
	91	#endif
943afa22 TT	92	#if defined(CONFIG_MPC83XX) \|\| defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)
	93	u32 i2c1_clk;
	94	u32 i2c2_clk;
	95	#endif
5f820439 DL	96	#if defined(CONFIG_QE)
	97	u32 qe_clk;
	98	u32 brg_clk;
7737d5c6 DL	99	uint mp_alloc_base;
7737d5c6 DL	100	uint mp_alloc_top;
5f820439	101	#endif /* CONFIG_QE */
f060054d KG	102	#if defined(CONFIG_FSL_LAW)
	103	u32 used_laws;
	104	#endif
cbd8a35c	105	#if defined(CONFIG_MPC5xxx)
945af8d7 WD	106	unsigned long ipb_clk;
945af8d7 WD	107	unsigned long pci_clk;
983fda83	108	#endif
8993e54b	109	#if defined(CONFIG_MPC512X)
5d49e0e1	110	u32 ips_clk;
8993e54b	111	u32 csb_clk;
5f91db7f	112	u32 pci_clk;
8993e54b	113	#endif /* CONFIG_MPC512X */
983fda83 WD	114	#if defined(CONFIG_MPC8220)
	115	unsigned long bExtUart;
	116	unsigned long inp_clk;
	117	unsigned long pci_clk;
	118	unsigned long vco_clk;
	119	unsigned long pev_clk;
	120	unsigned long flb_clk;
0157cedb	121	#endif
b57ca3e1	122	phys_size_t ram_size; /* RAM size */
0157cedb WD	123	unsigned long reloc_off; /* Relocation Offset */
0157cedb WD	124	unsigned long reset_status; /* reset status register at boot */
46497056 NS	125	#if defined(CONFIG_MPC83XX)
	126	unsigned long arbiter_event_attributes;
	127	unsigned long arbiter_event_address;
	128	#endif
0157cedb WD	129	unsigned long env_addr; /* Address of Environment struct */
	130	unsigned long env_valid; /* Checksum of Environment valid? */
	131	unsigned long have_console; /* serial_init() was called */
6d0f6bcf	132	#if defined(CONFIG_SYS_ALLOC_DPRAM) \|\| defined(CONFIG_CPM2)
0157cedb WD	133	unsigned int dp_alloc_base;
	134	unsigned int dp_alloc_top;
	135	#endif
f10493c6 SR	136	#if defined(CONFIG_4xx)
	137	u32 uart_clk;
	138	#endif /* CONFIG_4xx */
6d0f6bcf	139	#if defined(CONFIG_SYS_GT_6426x)
0157cedb WD	140	unsigned int mirror_hack[16];
0157cedb WD	141	#endif
756f586a WD	142	#if defined(CONFIG_A3000) \|\| \
	143	defined(CONFIG_HIDDEN_DRAGON) \|\| \
	144	defined(CONFIG_MUSENKI) \|\| \
	145	defined(CONFIG_SANDPOINT)
0157cedb WD	146	void * console_addr;
0157cedb WD	147	#endif
c7de829c WD	148	#ifdef CONFIG_AMIGAONEG3SE
	149	unsigned long relocaddr; /* Start address of U-Boot in RAM */
	150	#endif
0157cedb WD	151	#if defined(CONFIG_LCD) \|\| defined(CONFIG_VIDEO)
	152	unsigned long fb_base; /* Base address of framebuffer memory */
	153	#endif
667122af	154	#if defined(CONFIG_POST) \|\| defined(CONFIG_LOGBUFFER)
228f29ac	155	unsigned long post_log_word; /* Record POST activities */
4532cb69	156	unsigned long post_init_f_time; /* When post_init_f started */
228f29ac	157	#endif
0157cedb WD	158	#ifdef CONFIG_BOARD_TYPES
	159	unsigned long board_type;
	160	#endif
4532cb69 WD	161	#ifdef CONFIG_MODEM_SUPPORT
	162	unsigned long do_mdm_init;
	163	unsigned long be_quiet;
	164	#endif
3ad63878	165	#if defined(CONFIG_LWMON) \|\| defined(CONFIG_LWMON5)
4532cb69	166	unsigned long kbd_status;
d32a874b YT	167	#endif
	168	#if defined(CONFIG_WD_MAX_RATE)
	169	unsigned long long wdt_last; /* trace watch-dog triggering rate */
8bde7f77	170	#endif
27b207fd	171	void *jt; / jump table */
0157cedb WD	172	} gd_t;
	173
	174	/*
	175	* Global Data Flags
	176	*/
	177	#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
	178	#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
f72da340	179	#define GD_FLG_SILENT 0x00004 /* Silent mode */
b428f6a8	180	#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
28a38506	181	#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
0e15ddd1	182	#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
f5c3ba79	183	#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
0157cedb WD	184
0157cedb WD	185	#if 1
e7670f6c	186	#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
0157cedb WD	187	#else /* We could use plain global data, but the resulting code is bigger */
	188	#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
	189	#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
	190	gd_t *gd
	191	#endif
	192
	193	#endif /* __ASM_GBL_DATA_H */